1/* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * Copyright 2011 Linaro Ltd. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 13#include "skeleton.dtsi" 14#include "imx53-pinfunc.h" 15 16/ { 17 aliases { 18 serial0 = &uart1; 19 serial1 = &uart2; 20 serial2 = &uart3; 21 serial3 = &uart4; 22 serial4 = &uart5; 23 gpio0 = &gpio1; 24 gpio1 = &gpio2; 25 gpio2 = &gpio3; 26 gpio3 = &gpio4; 27 gpio4 = &gpio5; 28 gpio5 = &gpio6; 29 gpio6 = &gpio7; 30 }; 31 32 tzic: tz-interrupt-controller@0fffc000 { 33 compatible = "fsl,imx53-tzic", "fsl,tzic"; 34 interrupt-controller; 35 #interrupt-cells = <1>; 36 reg = <0x0fffc000 0x4000>; 37 }; 38 39 clocks { 40 #address-cells = <1>; 41 #size-cells = <0>; 42 43 ckil { 44 compatible = "fsl,imx-ckil", "fixed-clock"; 45 clock-frequency = <32768>; 46 }; 47 48 ckih1 { 49 compatible = "fsl,imx-ckih1", "fixed-clock"; 50 clock-frequency = <22579200>; 51 }; 52 53 ckih2 { 54 compatible = "fsl,imx-ckih2", "fixed-clock"; 55 clock-frequency = <0>; 56 }; 57 58 osc { 59 compatible = "fsl,imx-osc", "fixed-clock"; 60 clock-frequency = <24000000>; 61 }; 62 }; 63 64 soc { 65 #address-cells = <1>; 66 #size-cells = <1>; 67 compatible = "simple-bus"; 68 interrupt-parent = <&tzic>; 69 ranges; 70 71 ipu: ipu@18000000 { 72 #crtc-cells = <1>; 73 compatible = "fsl,imx53-ipu"; 74 reg = <0x18000000 0x080000000>; 75 interrupts = <11 10>; 76 clocks = <&clks 59>, <&clks 110>, <&clks 61>; 77 clock-names = "bus", "di0", "di1"; 78 resets = <&src 2>; 79 }; 80 81 aips@50000000 { /* AIPS1 */ 82 compatible = "fsl,aips-bus", "simple-bus"; 83 #address-cells = <1>; 84 #size-cells = <1>; 85 reg = <0x50000000 0x10000000>; 86 ranges; 87 88 spba@50000000 { 89 compatible = "fsl,spba-bus", "simple-bus"; 90 #address-cells = <1>; 91 #size-cells = <1>; 92 reg = <0x50000000 0x40000>; 93 ranges; 94 95 esdhc1: esdhc@50004000 { 96 compatible = "fsl,imx53-esdhc"; 97 reg = <0x50004000 0x4000>; 98 interrupts = <1>; 99 clocks = <&clks 44>, <&clks 0>, <&clks 71>; 100 clock-names = "ipg", "ahb", "per"; 101 bus-width = <4>; 102 status = "disabled"; 103 }; 104 105 esdhc2: esdhc@50008000 { 106 compatible = "fsl,imx53-esdhc"; 107 reg = <0x50008000 0x4000>; 108 interrupts = <2>; 109 clocks = <&clks 45>, <&clks 0>, <&clks 72>; 110 clock-names = "ipg", "ahb", "per"; 111 bus-width = <4>; 112 status = "disabled"; 113 }; 114 115 uart3: serial@5000c000 { 116 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 117 reg = <0x5000c000 0x4000>; 118 interrupts = <33>; 119 clocks = <&clks 32>, <&clks 33>; 120 clock-names = "ipg", "per"; 121 status = "disabled"; 122 }; 123 124 ecspi1: ecspi@50010000 { 125 #address-cells = <1>; 126 #size-cells = <0>; 127 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; 128 reg = <0x50010000 0x4000>; 129 interrupts = <36>; 130 clocks = <&clks 51>, <&clks 52>; 131 clock-names = "ipg", "per"; 132 status = "disabled"; 133 }; 134 135 ssi2: ssi@50014000 { 136 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; 137 reg = <0x50014000 0x4000>; 138 interrupts = <30>; 139 clocks = <&clks 49>; 140 fsl,fifo-depth = <15>; 141 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ 142 status = "disabled"; 143 }; 144 145 esdhc3: esdhc@50020000 { 146 compatible = "fsl,imx53-esdhc"; 147 reg = <0x50020000 0x4000>; 148 interrupts = <3>; 149 clocks = <&clks 46>, <&clks 0>, <&clks 73>; 150 clock-names = "ipg", "ahb", "per"; 151 bus-width = <4>; 152 status = "disabled"; 153 }; 154 155 esdhc4: esdhc@50024000 { 156 compatible = "fsl,imx53-esdhc"; 157 reg = <0x50024000 0x4000>; 158 interrupts = <4>; 159 clocks = <&clks 47>, <&clks 0>, <&clks 74>; 160 clock-names = "ipg", "ahb", "per"; 161 bus-width = <4>; 162 status = "disabled"; 163 }; 164 }; 165 166 usbotg: usb@53f80000 { 167 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 168 reg = <0x53f80000 0x0200>; 169 interrupts = <18>; 170 status = "disabled"; 171 }; 172 173 usbh1: usb@53f80200 { 174 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 175 reg = <0x53f80200 0x0200>; 176 interrupts = <14>; 177 status = "disabled"; 178 }; 179 180 usbh2: usb@53f80400 { 181 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 182 reg = <0x53f80400 0x0200>; 183 interrupts = <16>; 184 status = "disabled"; 185 }; 186 187 usbh3: usb@53f80600 { 188 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 189 reg = <0x53f80600 0x0200>; 190 interrupts = <17>; 191 status = "disabled"; 192 }; 193 194 gpio1: gpio@53f84000 { 195 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 196 reg = <0x53f84000 0x4000>; 197 interrupts = <50 51>; 198 gpio-controller; 199 #gpio-cells = <2>; 200 interrupt-controller; 201 #interrupt-cells = <2>; 202 }; 203 204 gpio2: gpio@53f88000 { 205 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 206 reg = <0x53f88000 0x4000>; 207 interrupts = <52 53>; 208 gpio-controller; 209 #gpio-cells = <2>; 210 interrupt-controller; 211 #interrupt-cells = <2>; 212 }; 213 214 gpio3: gpio@53f8c000 { 215 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 216 reg = <0x53f8c000 0x4000>; 217 interrupts = <54 55>; 218 gpio-controller; 219 #gpio-cells = <2>; 220 interrupt-controller; 221 #interrupt-cells = <2>; 222 }; 223 224 gpio4: gpio@53f90000 { 225 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 226 reg = <0x53f90000 0x4000>; 227 interrupts = <56 57>; 228 gpio-controller; 229 #gpio-cells = <2>; 230 interrupt-controller; 231 #interrupt-cells = <2>; 232 }; 233 234 wdog1: wdog@53f98000 { 235 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; 236 reg = <0x53f98000 0x4000>; 237 interrupts = <58>; 238 clocks = <&clks 0>; 239 }; 240 241 wdog2: wdog@53f9c000 { 242 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; 243 reg = <0x53f9c000 0x4000>; 244 interrupts = <59>; 245 clocks = <&clks 0>; 246 status = "disabled"; 247 }; 248 249 gpt: timer@53fa0000 { 250 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; 251 reg = <0x53fa0000 0x4000>; 252 interrupts = <39>; 253 clocks = <&clks 36>, <&clks 41>; 254 clock-names = "ipg", "per"; 255 }; 256 257 iomuxc: iomuxc@53fa8000 { 258 compatible = "fsl,imx53-iomuxc"; 259 reg = <0x53fa8000 0x4000>; 260 261 audmux { 262 pinctrl_audmux_1: audmuxgrp-1 { 263 fsl,pins = < 264 MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 265 MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 266 MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 267 MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 268 >; 269 }; 270 }; 271 272 fec { 273 pinctrl_fec_1: fecgrp-1 { 274 fsl,pins = < 275 MX53_PAD_FEC_MDC__FEC_MDC 0x80000000 276 MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000 277 MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000 278 MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000 279 MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000 280 MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000 281 MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000 282 MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 283 MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000 284 MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000 285 >; 286 }; 287 }; 288 289 csi { 290 pinctrl_csi_1: csigrp-1 { 291 fsl,pins = < 292 MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN 0x1d5 293 MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5 294 MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5 295 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5 296 MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5 297 MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5 298 MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5 299 MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5 300 MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5 301 MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5 302 MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5 303 MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5 304 MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 0x1d5 305 MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 0x1d5 306 MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 0x1d5 307 MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 0x1d5 308 MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 0x1d5 309 MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 0x1d5 310 MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 0x1d5 311 MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 0x1d5 312 MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5 313 >; 314 }; 315 }; 316 317 cspi { 318 pinctrl_cspi_1: cspigrp-1 { 319 fsl,pins = < 320 MX53_PAD_SD1_DATA0__CSPI_MISO 0x1d5 321 MX53_PAD_SD1_CMD__CSPI_MOSI 0x1d5 322 MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5 323 >; 324 }; 325 }; 326 327 ecspi1 { 328 pinctrl_ecspi1_1: ecspi1grp-1 { 329 fsl,pins = < 330 MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000 331 MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000 332 MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000 333 >; 334 }; 335 }; 336 337 esdhc1 { 338 pinctrl_esdhc1_1: esdhc1grp-1 { 339 fsl,pins = < 340 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 341 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 342 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 343 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 344 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 345 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 346 >; 347 }; 348 349 pinctrl_esdhc1_2: esdhc1grp-2 { 350 fsl,pins = < 351 MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 352 MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 353 MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 354 MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 355 MX53_PAD_PATA_DATA8__ESDHC1_DAT4 0x1d5 356 MX53_PAD_PATA_DATA9__ESDHC1_DAT5 0x1d5 357 MX53_PAD_PATA_DATA10__ESDHC1_DAT6 0x1d5 358 MX53_PAD_PATA_DATA11__ESDHC1_DAT7 0x1d5 359 MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 360 MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 361 >; 362 }; 363 }; 364 365 esdhc2 { 366 pinctrl_esdhc2_1: esdhc2grp-1 { 367 fsl,pins = < 368 MX53_PAD_SD2_CMD__ESDHC2_CMD 0x1d5 369 MX53_PAD_SD2_CLK__ESDHC2_CLK 0x1d5 370 MX53_PAD_SD2_DATA0__ESDHC2_DAT0 0x1d5 371 MX53_PAD_SD2_DATA1__ESDHC2_DAT1 0x1d5 372 MX53_PAD_SD2_DATA2__ESDHC2_DAT2 0x1d5 373 MX53_PAD_SD2_DATA3__ESDHC2_DAT3 0x1d5 374 >; 375 }; 376 }; 377 378 esdhc3 { 379 pinctrl_esdhc3_1: esdhc3grp-1 { 380 fsl,pins = < 381 MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5 382 MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5 383 MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5 384 MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5 385 MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5 386 MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5 387 MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5 388 MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5 389 MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5 390 MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5 391 >; 392 }; 393 }; 394 395 can1 { 396 pinctrl_can1_1: can1grp-1 { 397 fsl,pins = < 398 MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x80000000 399 MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x80000000 400 >; 401 }; 402 403 pinctrl_can1_2: can1grp-2 { 404 fsl,pins = < 405 MX53_PAD_KEY_COL2__CAN1_TXCAN 0x80000000 406 MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000 407 >; 408 }; 409 }; 410 411 can2 { 412 pinctrl_can2_1: can2grp-1 { 413 fsl,pins = < 414 MX53_PAD_KEY_COL4__CAN2_TXCAN 0x80000000 415 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x80000000 416 >; 417 }; 418 }; 419 420 i2c1 { 421 pinctrl_i2c1_1: i2c1grp-1 { 422 fsl,pins = < 423 MX53_PAD_CSI0_DAT8__I2C1_SDA 0xc0000000 424 MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000 425 >; 426 }; 427 }; 428 429 i2c2 { 430 pinctrl_i2c2_1: i2c2grp-1 { 431 fsl,pins = < 432 MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000 433 MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000 434 >; 435 }; 436 }; 437 438 i2c3 { 439 pinctrl_i2c3_1: i2c3grp-1 { 440 fsl,pins = < 441 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 442 MX53_PAD_GPIO_5__I2C3_SCL 0xc0000000 443 >; 444 }; 445 }; 446 447 owire { 448 pinctrl_owire_1: owiregrp-1 { 449 fsl,pins = < 450 MX53_PAD_GPIO_18__OWIRE_LINE 0x80000000 451 >; 452 }; 453 }; 454 455 uart1 { 456 pinctrl_uart1_1: uart1grp-1 { 457 fsl,pins = < 458 MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1c5 459 MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1c5 460 >; 461 }; 462 463 pinctrl_uart1_2: uart1grp-2 { 464 fsl,pins = < 465 MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1c5 466 MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5 467 >; 468 }; 469 }; 470 471 uart2 { 472 pinctrl_uart2_1: uart2grp-1 { 473 fsl,pins = < 474 MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5 475 MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5 476 >; 477 }; 478 }; 479 480 uart3 { 481 pinctrl_uart3_1: uart3grp-1 { 482 fsl,pins = < 483 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5 484 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5 485 MX53_PAD_PATA_DA_1__UART3_CTS 0x1c5 486 MX53_PAD_PATA_DA_2__UART3_RTS 0x1c5 487 >; 488 }; 489 490 pinctrl_uart3_2: uart3grp-2 { 491 fsl,pins = < 492 MX53_PAD_PATA_CS_0__UART3_TXD_MUX 0x1c5 493 MX53_PAD_PATA_CS_1__UART3_RXD_MUX 0x1c5 494 >; 495 }; 496 497 }; 498 499 uart4 { 500 pinctrl_uart4_1: uart4grp-1 { 501 fsl,pins = < 502 MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1c5 503 MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1c5 504 >; 505 }; 506 }; 507 508 uart5 { 509 pinctrl_uart5_1: uart5grp-1 { 510 fsl,pins = < 511 MX53_PAD_KEY_COL1__UART5_TXD_MUX 0x1c5 512 MX53_PAD_KEY_ROW1__UART5_RXD_MUX 0x1c5 513 >; 514 }; 515 }; 516 517 }; 518 519 gpr: iomuxc-gpr@53fa8000 { 520 compatible = "fsl,imx53-iomuxc-gpr", "syscon"; 521 reg = <0x53fa8000 0xc>; 522 }; 523 524 ldb: ldb@53fa8008 { 525 #address-cells = <1>; 526 #size-cells = <0>; 527 compatible = "fsl,imx53-ldb"; 528 reg = <0x53fa8008 0x4>; 529 gpr = <&gpr>; 530 clocks = <&clks 122>, <&clks 120>, 531 <&clks 115>, <&clks 116>, 532 <&clks 123>, <&clks 85>; 533 clock-names = "di0_pll", "di1_pll", 534 "di0_sel", "di1_sel", 535 "di0", "di1"; 536 status = "disabled"; 537 538 lvds-channel@0 { 539 reg = <0>; 540 crtcs = <&ipu 0>; 541 status = "disabled"; 542 }; 543 544 lvds-channel@1 { 545 reg = <1>; 546 crtcs = <&ipu 1>; 547 status = "disabled"; 548 }; 549 }; 550 551 pwm1: pwm@53fb4000 { 552 #pwm-cells = <2>; 553 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; 554 reg = <0x53fb4000 0x4000>; 555 clocks = <&clks 37>, <&clks 38>; 556 clock-names = "ipg", "per"; 557 interrupts = <61>; 558 }; 559 560 pwm2: pwm@53fb8000 { 561 #pwm-cells = <2>; 562 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; 563 reg = <0x53fb8000 0x4000>; 564 clocks = <&clks 39>, <&clks 40>; 565 clock-names = "ipg", "per"; 566 interrupts = <94>; 567 }; 568 569 uart1: serial@53fbc000 { 570 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 571 reg = <0x53fbc000 0x4000>; 572 interrupts = <31>; 573 clocks = <&clks 28>, <&clks 29>; 574 clock-names = "ipg", "per"; 575 status = "disabled"; 576 }; 577 578 uart2: serial@53fc0000 { 579 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 580 reg = <0x53fc0000 0x4000>; 581 interrupts = <32>; 582 clocks = <&clks 30>, <&clks 31>; 583 clock-names = "ipg", "per"; 584 status = "disabled"; 585 }; 586 587 can1: can@53fc8000 { 588 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; 589 reg = <0x53fc8000 0x4000>; 590 interrupts = <82>; 591 clocks = <&clks 158>, <&clks 157>; 592 clock-names = "ipg", "per"; 593 status = "disabled"; 594 }; 595 596 can2: can@53fcc000 { 597 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; 598 reg = <0x53fcc000 0x4000>; 599 interrupts = <83>; 600 clocks = <&clks 87>, <&clks 86>; 601 clock-names = "ipg", "per"; 602 status = "disabled"; 603 }; 604 605 src: src@53fd0000 { 606 compatible = "fsl,imx53-src", "fsl,imx51-src"; 607 reg = <0x53fd0000 0x4000>; 608 #reset-cells = <1>; 609 }; 610 611 clks: ccm@53fd4000{ 612 compatible = "fsl,imx53-ccm"; 613 reg = <0x53fd4000 0x4000>; 614 interrupts = <0 71 0x04 0 72 0x04>; 615 #clock-cells = <1>; 616 }; 617 618 gpio5: gpio@53fdc000 { 619 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 620 reg = <0x53fdc000 0x4000>; 621 interrupts = <103 104>; 622 gpio-controller; 623 #gpio-cells = <2>; 624 interrupt-controller; 625 #interrupt-cells = <2>; 626 }; 627 628 gpio6: gpio@53fe0000 { 629 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 630 reg = <0x53fe0000 0x4000>; 631 interrupts = <105 106>; 632 gpio-controller; 633 #gpio-cells = <2>; 634 interrupt-controller; 635 #interrupt-cells = <2>; 636 }; 637 638 gpio7: gpio@53fe4000 { 639 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 640 reg = <0x53fe4000 0x4000>; 641 interrupts = <107 108>; 642 gpio-controller; 643 #gpio-cells = <2>; 644 interrupt-controller; 645 #interrupt-cells = <2>; 646 }; 647 648 i2c3: i2c@53fec000 { 649 #address-cells = <1>; 650 #size-cells = <0>; 651 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; 652 reg = <0x53fec000 0x4000>; 653 interrupts = <64>; 654 clocks = <&clks 88>; 655 status = "disabled"; 656 }; 657 658 uart4: serial@53ff0000 { 659 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 660 reg = <0x53ff0000 0x4000>; 661 interrupts = <13>; 662 clocks = <&clks 65>, <&clks 66>; 663 clock-names = "ipg", "per"; 664 status = "disabled"; 665 }; 666 }; 667 668 aips@60000000 { /* AIPS2 */ 669 compatible = "fsl,aips-bus", "simple-bus"; 670 #address-cells = <1>; 671 #size-cells = <1>; 672 reg = <0x60000000 0x10000000>; 673 ranges; 674 675 uart5: serial@63f90000 { 676 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 677 reg = <0x63f90000 0x4000>; 678 interrupts = <86>; 679 clocks = <&clks 67>, <&clks 68>; 680 clock-names = "ipg", "per"; 681 status = "disabled"; 682 }; 683 684 owire: owire@63fa4000 { 685 compatible = "fsl,imx53-owire", "fsl,imx21-owire"; 686 reg = <0x63fa4000 0x4000>; 687 clocks = <&clks 159>; 688 status = "disabled"; 689 }; 690 691 ecspi2: ecspi@63fac000 { 692 #address-cells = <1>; 693 #size-cells = <0>; 694 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; 695 reg = <0x63fac000 0x4000>; 696 interrupts = <37>; 697 clocks = <&clks 53>, <&clks 54>; 698 clock-names = "ipg", "per"; 699 status = "disabled"; 700 }; 701 702 sdma: sdma@63fb0000 { 703 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; 704 reg = <0x63fb0000 0x4000>; 705 interrupts = <6>; 706 clocks = <&clks 56>, <&clks 56>; 707 clock-names = "ipg", "ahb"; 708 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; 709 }; 710 711 cspi: cspi@63fc0000 { 712 #address-cells = <1>; 713 #size-cells = <0>; 714 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; 715 reg = <0x63fc0000 0x4000>; 716 interrupts = <38>; 717 clocks = <&clks 55>, <&clks 55>; 718 clock-names = "ipg", "per"; 719 status = "disabled"; 720 }; 721 722 i2c2: i2c@63fc4000 { 723 #address-cells = <1>; 724 #size-cells = <0>; 725 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; 726 reg = <0x63fc4000 0x4000>; 727 interrupts = <63>; 728 clocks = <&clks 35>; 729 status = "disabled"; 730 }; 731 732 i2c1: i2c@63fc8000 { 733 #address-cells = <1>; 734 #size-cells = <0>; 735 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; 736 reg = <0x63fc8000 0x4000>; 737 interrupts = <62>; 738 clocks = <&clks 34>; 739 status = "disabled"; 740 }; 741 742 ssi1: ssi@63fcc000 { 743 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; 744 reg = <0x63fcc000 0x4000>; 745 interrupts = <29>; 746 clocks = <&clks 48>; 747 fsl,fifo-depth = <15>; 748 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ 749 status = "disabled"; 750 }; 751 752 audmux: audmux@63fd0000 { 753 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; 754 reg = <0x63fd0000 0x4000>; 755 status = "disabled"; 756 }; 757 758 nfc: nand@63fdb000 { 759 compatible = "fsl,imx53-nand"; 760 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; 761 interrupts = <8>; 762 clocks = <&clks 60>; 763 status = "disabled"; 764 }; 765 766 ssi3: ssi@63fe8000 { 767 compatible = "fsl,imx53-ssi", "fsl,imx21-ssi"; 768 reg = <0x63fe8000 0x4000>; 769 interrupts = <96>; 770 clocks = <&clks 50>; 771 fsl,fifo-depth = <15>; 772 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */ 773 status = "disabled"; 774 }; 775 776 fec: ethernet@63fec000 { 777 compatible = "fsl,imx53-fec", "fsl,imx25-fec"; 778 reg = <0x63fec000 0x4000>; 779 interrupts = <87>; 780 clocks = <&clks 42>, <&clks 42>, <&clks 42>; 781 clock-names = "ipg", "ahb", "ptp"; 782 status = "disabled"; 783 }; 784 }; 785 }; 786}; 787