1 /*
2 * arch/arm/mach-at91/at91sam9263.c
3 *
4 * Copyright (C) 2007 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13 #include <linux/module.h>
14
15 #include <asm/proc-fns.h>
16 #include <asm/irq.h>
17 #include <asm/mach/arch.h>
18 #include <asm/mach/map.h>
19 #include <asm/system_misc.h>
20 #include <mach/at91sam9263.h>
21 #include <mach/at91_pmc.h>
22
23 #include "at91_aic.h"
24 #include "at91_rstc.h"
25 #include "soc.h"
26 #include "generic.h"
27 #include "clock.h"
28 #include "sam9_smc.h"
29
30 /* --------------------------------------------------------------------
31 * Clocks
32 * -------------------------------------------------------------------- */
33
34 /*
35 * The peripheral clocks.
36 */
37 static struct clk pioA_clk = {
38 .name = "pioA_clk",
39 .pmc_mask = 1 << AT91SAM9263_ID_PIOA,
40 .type = CLK_TYPE_PERIPHERAL,
41 };
42 static struct clk pioB_clk = {
43 .name = "pioB_clk",
44 .pmc_mask = 1 << AT91SAM9263_ID_PIOB,
45 .type = CLK_TYPE_PERIPHERAL,
46 };
47 static struct clk pioCDE_clk = {
48 .name = "pioCDE_clk",
49 .pmc_mask = 1 << AT91SAM9263_ID_PIOCDE,
50 .type = CLK_TYPE_PERIPHERAL,
51 };
52 static struct clk usart0_clk = {
53 .name = "usart0_clk",
54 .pmc_mask = 1 << AT91SAM9263_ID_US0,
55 .type = CLK_TYPE_PERIPHERAL,
56 };
57 static struct clk usart1_clk = {
58 .name = "usart1_clk",
59 .pmc_mask = 1 << AT91SAM9263_ID_US1,
60 .type = CLK_TYPE_PERIPHERAL,
61 };
62 static struct clk usart2_clk = {
63 .name = "usart2_clk",
64 .pmc_mask = 1 << AT91SAM9263_ID_US2,
65 .type = CLK_TYPE_PERIPHERAL,
66 };
67 static struct clk mmc0_clk = {
68 .name = "mci0_clk",
69 .pmc_mask = 1 << AT91SAM9263_ID_MCI0,
70 .type = CLK_TYPE_PERIPHERAL,
71 };
72 static struct clk mmc1_clk = {
73 .name = "mci1_clk",
74 .pmc_mask = 1 << AT91SAM9263_ID_MCI1,
75 .type = CLK_TYPE_PERIPHERAL,
76 };
77 static struct clk can_clk = {
78 .name = "can_clk",
79 .pmc_mask = 1 << AT91SAM9263_ID_CAN,
80 .type = CLK_TYPE_PERIPHERAL,
81 };
82 static struct clk twi_clk = {
83 .name = "twi_clk",
84 .pmc_mask = 1 << AT91SAM9263_ID_TWI,
85 .type = CLK_TYPE_PERIPHERAL,
86 };
87 static struct clk spi0_clk = {
88 .name = "spi0_clk",
89 .pmc_mask = 1 << AT91SAM9263_ID_SPI0,
90 .type = CLK_TYPE_PERIPHERAL,
91 };
92 static struct clk spi1_clk = {
93 .name = "spi1_clk",
94 .pmc_mask = 1 << AT91SAM9263_ID_SPI1,
95 .type = CLK_TYPE_PERIPHERAL,
96 };
97 static struct clk ssc0_clk = {
98 .name = "ssc0_clk",
99 .pmc_mask = 1 << AT91SAM9263_ID_SSC0,
100 .type = CLK_TYPE_PERIPHERAL,
101 };
102 static struct clk ssc1_clk = {
103 .name = "ssc1_clk",
104 .pmc_mask = 1 << AT91SAM9263_ID_SSC1,
105 .type = CLK_TYPE_PERIPHERAL,
106 };
107 static struct clk ac97_clk = {
108 .name = "ac97_clk",
109 .pmc_mask = 1 << AT91SAM9263_ID_AC97C,
110 .type = CLK_TYPE_PERIPHERAL,
111 };
112 static struct clk tcb_clk = {
113 .name = "tcb_clk",
114 .pmc_mask = 1 << AT91SAM9263_ID_TCB,
115 .type = CLK_TYPE_PERIPHERAL,
116 };
117 static struct clk pwm_clk = {
118 .name = "pwm_clk",
119 .pmc_mask = 1 << AT91SAM9263_ID_PWMC,
120 .type = CLK_TYPE_PERIPHERAL,
121 };
122 static struct clk macb_clk = {
123 .name = "pclk",
124 .pmc_mask = 1 << AT91SAM9263_ID_EMAC,
125 .type = CLK_TYPE_PERIPHERAL,
126 };
127 static struct clk dma_clk = {
128 .name = "dma_clk",
129 .pmc_mask = 1 << AT91SAM9263_ID_DMA,
130 .type = CLK_TYPE_PERIPHERAL,
131 };
132 static struct clk twodge_clk = {
133 .name = "2dge_clk",
134 .pmc_mask = 1 << AT91SAM9263_ID_2DGE,
135 .type = CLK_TYPE_PERIPHERAL,
136 };
137 static struct clk udc_clk = {
138 .name = "udc_clk",
139 .pmc_mask = 1 << AT91SAM9263_ID_UDP,
140 .type = CLK_TYPE_PERIPHERAL,
141 };
142 static struct clk isi_clk = {
143 .name = "isi_clk",
144 .pmc_mask = 1 << AT91SAM9263_ID_ISI,
145 .type = CLK_TYPE_PERIPHERAL,
146 };
147 static struct clk lcdc_clk = {
148 .name = "lcdc_clk",
149 .pmc_mask = 1 << AT91SAM9263_ID_LCDC,
150 .type = CLK_TYPE_PERIPHERAL,
151 };
152 static struct clk ohci_clk = {
153 .name = "ohci_clk",
154 .pmc_mask = 1 << AT91SAM9263_ID_UHP,
155 .type = CLK_TYPE_PERIPHERAL,
156 };
157
158 static struct clk *periph_clocks[] __initdata = {
159 &pioA_clk,
160 &pioB_clk,
161 &pioCDE_clk,
162 &usart0_clk,
163 &usart1_clk,
164 &usart2_clk,
165 &mmc0_clk,
166 &mmc1_clk,
167 &can_clk,
168 &twi_clk,
169 &spi0_clk,
170 &spi1_clk,
171 &ssc0_clk,
172 &ssc1_clk,
173 &ac97_clk,
174 &tcb_clk,
175 &pwm_clk,
176 &macb_clk,
177 &twodge_clk,
178 &udc_clk,
179 &isi_clk,
180 &lcdc_clk,
181 &dma_clk,
182 &ohci_clk,
183 // irq0 .. irq1
184 };
185
186 static struct clk_lookup periph_clocks_lookups[] = {
187 /* One additional fake clock for macb_hclk */
188 CLKDEV_CON_ID("hclk", &macb_clk),
189 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
190 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
191 CLKDEV_CON_DEV_ID("pclk", "fff98000.ssc", &ssc0_clk),
192 CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc1_clk),
193 CLKDEV_CON_DEV_ID("hclk", "at91sam9263-lcdfb.0", &lcdc_clk),
194 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
195 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
196 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
197 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
198 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
199 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
200 /* fake hclk clock */
201 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
202 CLKDEV_CON_ID("pioA", &pioA_clk),
203 CLKDEV_CON_ID("pioB", &pioB_clk),
204 CLKDEV_CON_ID("pioC", &pioCDE_clk),
205 CLKDEV_CON_ID("pioD", &pioCDE_clk),
206 CLKDEV_CON_ID("pioE", &pioCDE_clk),
207 /* more usart lookup table for DT entries */
208 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
209 CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
210 CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
211 CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
212 /* more tc lookup table for DT entries */
213 CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb_clk),
214 CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
215 CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
216 CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
217 CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
218 CLKDEV_CON_DEV_ID("mci_clk", "fff84000.mmc", &mmc1_clk),
219 CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk),
220 CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
221 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
222 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioCDE_clk),
223 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCDE_clk),
224 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCDE_clk),
225 };
226
227 static struct clk_lookup usart_clocks_lookups[] = {
228 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
229 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
230 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
231 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
232 };
233
234 /*
235 * The four programmable clocks.
236 * You must configure pin multiplexing to bring these signals out.
237 */
238 static struct clk pck0 = {
239 .name = "pck0",
240 .pmc_mask = AT91_PMC_PCK0,
241 .type = CLK_TYPE_PROGRAMMABLE,
242 .id = 0,
243 };
244 static struct clk pck1 = {
245 .name = "pck1",
246 .pmc_mask = AT91_PMC_PCK1,
247 .type = CLK_TYPE_PROGRAMMABLE,
248 .id = 1,
249 };
250 static struct clk pck2 = {
251 .name = "pck2",
252 .pmc_mask = AT91_PMC_PCK2,
253 .type = CLK_TYPE_PROGRAMMABLE,
254 .id = 2,
255 };
256 static struct clk pck3 = {
257 .name = "pck3",
258 .pmc_mask = AT91_PMC_PCK3,
259 .type = CLK_TYPE_PROGRAMMABLE,
260 .id = 3,
261 };
262
at91sam9263_register_clocks(void)263 static void __init at91sam9263_register_clocks(void)
264 {
265 int i;
266
267 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
268 clk_register(periph_clocks[i]);
269
270 clkdev_add_table(periph_clocks_lookups,
271 ARRAY_SIZE(periph_clocks_lookups));
272 clkdev_add_table(usart_clocks_lookups,
273 ARRAY_SIZE(usart_clocks_lookups));
274
275 clk_register(&pck0);
276 clk_register(&pck1);
277 clk_register(&pck2);
278 clk_register(&pck3);
279 }
280
281 /* --------------------------------------------------------------------
282 * GPIO
283 * -------------------------------------------------------------------- */
284
285 static struct at91_gpio_bank at91sam9263_gpio[] __initdata = {
286 {
287 .id = AT91SAM9263_ID_PIOA,
288 .regbase = AT91SAM9263_BASE_PIOA,
289 }, {
290 .id = AT91SAM9263_ID_PIOB,
291 .regbase = AT91SAM9263_BASE_PIOB,
292 }, {
293 .id = AT91SAM9263_ID_PIOCDE,
294 .regbase = AT91SAM9263_BASE_PIOC,
295 }, {
296 .id = AT91SAM9263_ID_PIOCDE,
297 .regbase = AT91SAM9263_BASE_PIOD,
298 }, {
299 .id = AT91SAM9263_ID_PIOCDE,
300 .regbase = AT91SAM9263_BASE_PIOE,
301 }
302 };
303
304 /* --------------------------------------------------------------------
305 * AT91SAM9263 processor initialization
306 * -------------------------------------------------------------------- */
307
at91sam9263_map_io(void)308 static void __init at91sam9263_map_io(void)
309 {
310 at91_init_sram(0, AT91SAM9263_SRAM0_BASE, AT91SAM9263_SRAM0_SIZE);
311 at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
312 }
313
at91sam9263_ioremap_registers(void)314 static void __init at91sam9263_ioremap_registers(void)
315 {
316 at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
317 at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
318 at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
319 at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
320 at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
321 at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
322 at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
323 at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
324 }
325
at91sam9263_initialize(void)326 static void __init at91sam9263_initialize(void)
327 {
328 arm_pm_idle = at91sam9_idle;
329 arm_pm_restart = at91sam9_alt_restart;
330 at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
331
332 /* Register GPIO subsystem */
333 at91_gpio_init(at91sam9263_gpio, 5);
334 }
335
336 /* --------------------------------------------------------------------
337 * Interrupt initialization
338 * -------------------------------------------------------------------- */
339
340 /*
341 * The default interrupt priority levels (0 = lowest, 7 = highest).
342 */
343 static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
344 7, /* Advanced Interrupt Controller (FIQ) */
345 7, /* System Peripherals */
346 1, /* Parallel IO Controller A */
347 1, /* Parallel IO Controller B */
348 1, /* Parallel IO Controller C, D and E */
349 0,
350 0,
351 5, /* USART 0 */
352 5, /* USART 1 */
353 5, /* USART 2 */
354 0, /* Multimedia Card Interface 0 */
355 0, /* Multimedia Card Interface 1 */
356 3, /* CAN */
357 6, /* Two-Wire Interface */
358 5, /* Serial Peripheral Interface 0 */
359 5, /* Serial Peripheral Interface 1 */
360 4, /* Serial Synchronous Controller 0 */
361 4, /* Serial Synchronous Controller 1 */
362 5, /* AC97 Controller */
363 0, /* Timer Counter 0, 1 and 2 */
364 0, /* Pulse Width Modulation Controller */
365 3, /* Ethernet */
366 0,
367 0, /* 2D Graphic Engine */
368 2, /* USB Device Port */
369 0, /* Image Sensor Interface */
370 3, /* LDC Controller */
371 0, /* DMA Controller */
372 0,
373 2, /* USB Host port */
374 0, /* Advanced Interrupt Controller (IRQ0) */
375 0, /* Advanced Interrupt Controller (IRQ1) */
376 };
377
378 AT91_SOC_START(at91sam9263)
379 .map_io = at91sam9263_map_io,
380 .default_irq_priority = at91sam9263_default_irq_priority,
381 .ioremap_registers = at91sam9263_ioremap_registers,
382 .register_clocks = at91sam9263_register_clocks,
383 .init = at91sam9263_initialize,
384 AT91_SOC_END
385