1 /*
2 * arch/arm/mach-at91/at91sam9rl.c
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2007 Atmel Corporation
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
9 * more details.
10 */
11
12 #include <linux/module.h>
13
14 #include <asm/proc-fns.h>
15 #include <asm/irq.h>
16 #include <asm/mach/arch.h>
17 #include <asm/mach/map.h>
18 #include <asm/system_misc.h>
19 #include <mach/cpu.h>
20 #include <mach/at91_dbgu.h>
21 #include <mach/at91sam9rl.h>
22 #include <mach/at91_pmc.h>
23
24 #include "at91_aic.h"
25 #include "at91_rstc.h"
26 #include "soc.h"
27 #include "generic.h"
28 #include "clock.h"
29 #include "sam9_smc.h"
30
31 /* --------------------------------------------------------------------
32 * Clocks
33 * -------------------------------------------------------------------- */
34
35 /*
36 * The peripheral clocks.
37 */
38 static struct clk pioA_clk = {
39 .name = "pioA_clk",
40 .pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
41 .type = CLK_TYPE_PERIPHERAL,
42 };
43 static struct clk pioB_clk = {
44 .name = "pioB_clk",
45 .pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
46 .type = CLK_TYPE_PERIPHERAL,
47 };
48 static struct clk pioC_clk = {
49 .name = "pioC_clk",
50 .pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
51 .type = CLK_TYPE_PERIPHERAL,
52 };
53 static struct clk pioD_clk = {
54 .name = "pioD_clk",
55 .pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
56 .type = CLK_TYPE_PERIPHERAL,
57 };
58 static struct clk usart0_clk = {
59 .name = "usart0_clk",
60 .pmc_mask = 1 << AT91SAM9RL_ID_US0,
61 .type = CLK_TYPE_PERIPHERAL,
62 };
63 static struct clk usart1_clk = {
64 .name = "usart1_clk",
65 .pmc_mask = 1 << AT91SAM9RL_ID_US1,
66 .type = CLK_TYPE_PERIPHERAL,
67 };
68 static struct clk usart2_clk = {
69 .name = "usart2_clk",
70 .pmc_mask = 1 << AT91SAM9RL_ID_US2,
71 .type = CLK_TYPE_PERIPHERAL,
72 };
73 static struct clk usart3_clk = {
74 .name = "usart3_clk",
75 .pmc_mask = 1 << AT91SAM9RL_ID_US3,
76 .type = CLK_TYPE_PERIPHERAL,
77 };
78 static struct clk mmc_clk = {
79 .name = "mci_clk",
80 .pmc_mask = 1 << AT91SAM9RL_ID_MCI,
81 .type = CLK_TYPE_PERIPHERAL,
82 };
83 static struct clk twi0_clk = {
84 .name = "twi0_clk",
85 .pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
86 .type = CLK_TYPE_PERIPHERAL,
87 };
88 static struct clk twi1_clk = {
89 .name = "twi1_clk",
90 .pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
91 .type = CLK_TYPE_PERIPHERAL,
92 };
93 static struct clk spi_clk = {
94 .name = "spi_clk",
95 .pmc_mask = 1 << AT91SAM9RL_ID_SPI,
96 .type = CLK_TYPE_PERIPHERAL,
97 };
98 static struct clk ssc0_clk = {
99 .name = "ssc0_clk",
100 .pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
101 .type = CLK_TYPE_PERIPHERAL,
102 };
103 static struct clk ssc1_clk = {
104 .name = "ssc1_clk",
105 .pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
106 .type = CLK_TYPE_PERIPHERAL,
107 };
108 static struct clk tc0_clk = {
109 .name = "tc0_clk",
110 .pmc_mask = 1 << AT91SAM9RL_ID_TC0,
111 .type = CLK_TYPE_PERIPHERAL,
112 };
113 static struct clk tc1_clk = {
114 .name = "tc1_clk",
115 .pmc_mask = 1 << AT91SAM9RL_ID_TC1,
116 .type = CLK_TYPE_PERIPHERAL,
117 };
118 static struct clk tc2_clk = {
119 .name = "tc2_clk",
120 .pmc_mask = 1 << AT91SAM9RL_ID_TC2,
121 .type = CLK_TYPE_PERIPHERAL,
122 };
123 static struct clk pwm_clk = {
124 .name = "pwm_clk",
125 .pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
126 .type = CLK_TYPE_PERIPHERAL,
127 };
128 static struct clk tsc_clk = {
129 .name = "tsc_clk",
130 .pmc_mask = 1 << AT91SAM9RL_ID_TSC,
131 .type = CLK_TYPE_PERIPHERAL,
132 };
133 static struct clk dma_clk = {
134 .name = "dma_clk",
135 .pmc_mask = 1 << AT91SAM9RL_ID_DMA,
136 .type = CLK_TYPE_PERIPHERAL,
137 };
138 static struct clk udphs_clk = {
139 .name = "udphs_clk",
140 .pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
141 .type = CLK_TYPE_PERIPHERAL,
142 };
143 static struct clk lcdc_clk = {
144 .name = "lcdc_clk",
145 .pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
146 .type = CLK_TYPE_PERIPHERAL,
147 };
148 static struct clk ac97_clk = {
149 .name = "ac97_clk",
150 .pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
151 .type = CLK_TYPE_PERIPHERAL,
152 };
153
154 static struct clk *periph_clocks[] __initdata = {
155 &pioA_clk,
156 &pioB_clk,
157 &pioC_clk,
158 &pioD_clk,
159 &usart0_clk,
160 &usart1_clk,
161 &usart2_clk,
162 &usart3_clk,
163 &mmc_clk,
164 &twi0_clk,
165 &twi1_clk,
166 &spi_clk,
167 &ssc0_clk,
168 &ssc1_clk,
169 &tc0_clk,
170 &tc1_clk,
171 &tc2_clk,
172 &pwm_clk,
173 &tsc_clk,
174 &dma_clk,
175 &udphs_clk,
176 &lcdc_clk,
177 &ac97_clk,
178 // irq0
179 };
180
181 static struct clk_lookup periph_clocks_lookups[] = {
182 CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
183 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
184 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
185 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
186 CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
187 CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
188 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
189 CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
190 CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc0_clk),
191 CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc1_clk),
192 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
193 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
194 CLKDEV_CON_ID("pioA", &pioA_clk),
195 CLKDEV_CON_ID("pioB", &pioB_clk),
196 CLKDEV_CON_ID("pioC", &pioC_clk),
197 CLKDEV_CON_ID("pioD", &pioD_clk),
198 };
199
200 static struct clk_lookup usart_clocks_lookups[] = {
201 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
202 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
203 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
204 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
205 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
206 };
207
208 /*
209 * The two programmable clocks.
210 * You must configure pin multiplexing to bring these signals out.
211 */
212 static struct clk pck0 = {
213 .name = "pck0",
214 .pmc_mask = AT91_PMC_PCK0,
215 .type = CLK_TYPE_PROGRAMMABLE,
216 .id = 0,
217 };
218 static struct clk pck1 = {
219 .name = "pck1",
220 .pmc_mask = AT91_PMC_PCK1,
221 .type = CLK_TYPE_PROGRAMMABLE,
222 .id = 1,
223 };
224
at91sam9rl_register_clocks(void)225 static void __init at91sam9rl_register_clocks(void)
226 {
227 int i;
228
229 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
230 clk_register(periph_clocks[i]);
231
232 clkdev_add_table(periph_clocks_lookups,
233 ARRAY_SIZE(periph_clocks_lookups));
234 clkdev_add_table(usart_clocks_lookups,
235 ARRAY_SIZE(usart_clocks_lookups));
236
237 clk_register(&pck0);
238 clk_register(&pck1);
239 }
240
241 /* --------------------------------------------------------------------
242 * GPIO
243 * -------------------------------------------------------------------- */
244
245 static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
246 {
247 .id = AT91SAM9RL_ID_PIOA,
248 .regbase = AT91SAM9RL_BASE_PIOA,
249 }, {
250 .id = AT91SAM9RL_ID_PIOB,
251 .regbase = AT91SAM9RL_BASE_PIOB,
252 }, {
253 .id = AT91SAM9RL_ID_PIOC,
254 .regbase = AT91SAM9RL_BASE_PIOC,
255 }, {
256 .id = AT91SAM9RL_ID_PIOD,
257 .regbase = AT91SAM9RL_BASE_PIOD,
258 }
259 };
260
261 /* --------------------------------------------------------------------
262 * AT91SAM9RL processor initialization
263 * -------------------------------------------------------------------- */
264
at91sam9rl_map_io(void)265 static void __init at91sam9rl_map_io(void)
266 {
267 unsigned long sram_size;
268
269 switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
270 case AT91_CIDR_SRAMSIZ_32K:
271 sram_size = 2 * SZ_16K;
272 break;
273 case AT91_CIDR_SRAMSIZ_16K:
274 default:
275 sram_size = SZ_16K;
276 }
277
278 /* Map SRAM */
279 at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
280 }
281
at91sam9rl_ioremap_registers(void)282 static void __init at91sam9rl_ioremap_registers(void)
283 {
284 at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
285 at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
286 at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
287 at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
288 at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
289 at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
290 }
291
at91sam9rl_initialize(void)292 static void __init at91sam9rl_initialize(void)
293 {
294 arm_pm_idle = at91sam9_idle;
295 arm_pm_restart = at91sam9_alt_restart;
296 at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
297
298 /* Register GPIO subsystem */
299 at91_gpio_init(at91sam9rl_gpio, 4);
300 }
301
302 /* --------------------------------------------------------------------
303 * Interrupt initialization
304 * -------------------------------------------------------------------- */
305
306 /*
307 * The default interrupt priority levels (0 = lowest, 7 = highest).
308 */
309 static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
310 7, /* Advanced Interrupt Controller */
311 7, /* System Peripherals */
312 1, /* Parallel IO Controller A */
313 1, /* Parallel IO Controller B */
314 1, /* Parallel IO Controller C */
315 1, /* Parallel IO Controller D */
316 5, /* USART 0 */
317 5, /* USART 1 */
318 5, /* USART 2 */
319 5, /* USART 3 */
320 0, /* Multimedia Card Interface */
321 6, /* Two-Wire Interface 0 */
322 6, /* Two-Wire Interface 1 */
323 5, /* Serial Peripheral Interface */
324 4, /* Serial Synchronous Controller 0 */
325 4, /* Serial Synchronous Controller 1 */
326 0, /* Timer Counter 0 */
327 0, /* Timer Counter 1 */
328 0, /* Timer Counter 2 */
329 0,
330 0, /* Touch Screen Controller */
331 0, /* DMA Controller */
332 2, /* USB Device High speed port */
333 2, /* LCD Controller */
334 6, /* AC97 Controller */
335 0,
336 0,
337 0,
338 0,
339 0,
340 0,
341 0, /* Advanced Interrupt Controller */
342 };
343
344 AT91_SOC_START(at91sam9rl)
345 .map_io = at91sam9rl_map_io,
346 .default_irq_priority = at91sam9rl_default_irq_priority,
347 .ioremap_registers = at91sam9rl_ioremap_registers,
348 .register_clocks = at91sam9rl_register_clocks,
349 .init = at91sam9rl_initialize,
350 AT91_SOC_END
351