1 /*
2 * arch/arm/mach-dove/common.c
3 *
4 * Core functions for Marvell Dove 88AP510 System On Chip
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11 #include <linux/clk-provider.h>
12 #include <linux/clk/mvebu.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/init.h>
15 #include <linux/of.h>
16 #include <linux/of_platform.h>
17 #include <linux/platform_data/dma-mv_xor.h>
18 #include <linux/platform_data/usb-ehci-orion.h>
19 #include <linux/platform_device.h>
20 #include <asm/hardware/cache-tauros2.h>
21 #include <asm/mach/arch.h>
22 #include <asm/mach/map.h>
23 #include <asm/mach/time.h>
24 #include <mach/bridge-regs.h>
25 #include <mach/pm.h>
26 #include <plat/common.h>
27 #include <plat/irq.h>
28 #include <plat/time.h>
29 #include "common.h"
30
31 /*****************************************************************************
32 * I/O Address Mapping
33 ****************************************************************************/
34 static struct map_desc dove_io_desc[] __initdata = {
35 {
36 .virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE,
37 .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
38 .length = DOVE_SB_REGS_SIZE,
39 .type = MT_DEVICE,
40 }, {
41 .virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE,
42 .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
43 .length = DOVE_NB_REGS_SIZE,
44 .type = MT_DEVICE,
45 },
46 };
47
dove_map_io(void)48 void __init dove_map_io(void)
49 {
50 iotable_init(dove_io_desc, ARRAY_SIZE(dove_io_desc));
51 }
52
53 /*****************************************************************************
54 * CLK tree
55 ****************************************************************************/
56 static int dove_tclk;
57
58 static DEFINE_SPINLOCK(gating_lock);
59 static struct clk *tclk;
60
dove_register_gate(const char * name,const char * parent,u8 bit_idx)61 static struct clk __init *dove_register_gate(const char *name,
62 const char *parent, u8 bit_idx)
63 {
64 return clk_register_gate(NULL, name, parent, 0,
65 (void __iomem *)CLOCK_GATING_CONTROL,
66 bit_idx, 0, &gating_lock);
67 }
68
dove_clk_init(void)69 static void __init dove_clk_init(void)
70 {
71 struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
72 struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
73 struct clk *xor0, *xor1, *ge, *gephy;
74
75 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
76 dove_tclk);
77
78 usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
79 usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
80 sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
81 pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
82 pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
83 sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
84 sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
85 nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
86 camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
87 i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
88 i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
89 crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
90 ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
91 pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
92 xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
93 xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
94 gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
95 ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
96
97 orion_clkdev_add(NULL, "orion_spi.0", tclk);
98 orion_clkdev_add(NULL, "orion_spi.1", tclk);
99 orion_clkdev_add(NULL, "orion_wdt", tclk);
100 orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
101
102 orion_clkdev_add(NULL, "orion-ehci.0", usb0);
103 orion_clkdev_add(NULL, "orion-ehci.1", usb1);
104 orion_clkdev_add(NULL, "mv643xx_eth_port.0", ge);
105 orion_clkdev_add(NULL, "sata_mv.0", sata);
106 orion_clkdev_add("0", "pcie", pex0);
107 orion_clkdev_add("1", "pcie", pex1);
108 orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
109 orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
110 orion_clkdev_add(NULL, "orion_nand", nand);
111 orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
112 orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0);
113 orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1);
114 orion_clkdev_add(NULL, "mv_crypto", crypto);
115 orion_clkdev_add(NULL, "dove-ac97", ac97);
116 orion_clkdev_add(NULL, "dove-pdma", pdma);
117 orion_clkdev_add(NULL, MV_XOR_NAME ".0", xor0);
118 orion_clkdev_add(NULL, MV_XOR_NAME ".1", xor1);
119 }
120
121 /*****************************************************************************
122 * EHCI0
123 ****************************************************************************/
dove_ehci0_init(void)124 void __init dove_ehci0_init(void)
125 {
126 orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0, EHCI_PHY_NA);
127 }
128
129 /*****************************************************************************
130 * EHCI1
131 ****************************************************************************/
dove_ehci1_init(void)132 void __init dove_ehci1_init(void)
133 {
134 orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
135 }
136
137 /*****************************************************************************
138 * GE00
139 ****************************************************************************/
dove_ge00_init(struct mv643xx_eth_platform_data * eth_data)140 void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
141 {
142 orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE,
143 IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR,
144 1600);
145 }
146
147 /*****************************************************************************
148 * SoC RTC
149 ****************************************************************************/
dove_rtc_init(void)150 void __init dove_rtc_init(void)
151 {
152 orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
153 }
154
155 /*****************************************************************************
156 * SATA
157 ****************************************************************************/
dove_sata_init(struct mv_sata_platform_data * sata_data)158 void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
159 {
160 orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
161
162 }
163
164 /*****************************************************************************
165 * UART0
166 ****************************************************************************/
dove_uart0_init(void)167 void __init dove_uart0_init(void)
168 {
169 orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
170 IRQ_DOVE_UART_0, tclk);
171 }
172
173 /*****************************************************************************
174 * UART1
175 ****************************************************************************/
dove_uart1_init(void)176 void __init dove_uart1_init(void)
177 {
178 orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
179 IRQ_DOVE_UART_1, tclk);
180 }
181
182 /*****************************************************************************
183 * UART2
184 ****************************************************************************/
dove_uart2_init(void)185 void __init dove_uart2_init(void)
186 {
187 orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
188 IRQ_DOVE_UART_2, tclk);
189 }
190
191 /*****************************************************************************
192 * UART3
193 ****************************************************************************/
dove_uart3_init(void)194 void __init dove_uart3_init(void)
195 {
196 orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
197 IRQ_DOVE_UART_3, tclk);
198 }
199
200 /*****************************************************************************
201 * SPI
202 ****************************************************************************/
dove_spi0_init(void)203 void __init dove_spi0_init(void)
204 {
205 orion_spi_init(DOVE_SPI0_PHYS_BASE);
206 }
207
dove_spi1_init(void)208 void __init dove_spi1_init(void)
209 {
210 orion_spi_1_init(DOVE_SPI1_PHYS_BASE);
211 }
212
213 /*****************************************************************************
214 * I2C
215 ****************************************************************************/
dove_i2c_init(void)216 void __init dove_i2c_init(void)
217 {
218 orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
219 }
220
221 /*****************************************************************************
222 * Time handling
223 ****************************************************************************/
dove_init_early(void)224 void __init dove_init_early(void)
225 {
226 orion_time_set_base(TIMER_VIRT_BASE);
227 mvebu_mbus_init("marvell,dove-mbus",
228 BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
229 DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ);
230 }
231
dove_find_tclk(void)232 static int __init dove_find_tclk(void)
233 {
234 return 166666667;
235 }
236
dove_timer_init(void)237 void __init dove_timer_init(void)
238 {
239 dove_tclk = dove_find_tclk();
240 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
241 IRQ_DOVE_BRIDGE, dove_tclk);
242 }
243
244 /*****************************************************************************
245 * Cryptographic Engines and Security Accelerator (CESA)
246 ****************************************************************************/
dove_crypto_init(void)247 void __init dove_crypto_init(void)
248 {
249 orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE,
250 DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO);
251 }
252
253 /*****************************************************************************
254 * XOR 0
255 ****************************************************************************/
dove_xor0_init(void)256 void __init dove_xor0_init(void)
257 {
258 orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
259 IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
260 }
261
262 /*****************************************************************************
263 * XOR 1
264 ****************************************************************************/
dove_xor1_init(void)265 void __init dove_xor1_init(void)
266 {
267 orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
268 IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
269 }
270
271 /*****************************************************************************
272 * SDIO
273 ****************************************************************************/
274 static u64 sdio_dmamask = DMA_BIT_MASK(32);
275
276 static struct resource dove_sdio0_resources[] = {
277 {
278 .start = DOVE_SDIO0_PHYS_BASE,
279 .end = DOVE_SDIO0_PHYS_BASE + 0xff,
280 .flags = IORESOURCE_MEM,
281 }, {
282 .start = IRQ_DOVE_SDIO0,
283 .end = IRQ_DOVE_SDIO0,
284 .flags = IORESOURCE_IRQ,
285 },
286 };
287
288 static struct platform_device dove_sdio0 = {
289 .name = "sdhci-dove",
290 .id = 0,
291 .dev = {
292 .dma_mask = &sdio_dmamask,
293 .coherent_dma_mask = DMA_BIT_MASK(32),
294 },
295 .resource = dove_sdio0_resources,
296 .num_resources = ARRAY_SIZE(dove_sdio0_resources),
297 };
298
dove_sdio0_init(void)299 void __init dove_sdio0_init(void)
300 {
301 platform_device_register(&dove_sdio0);
302 }
303
304 static struct resource dove_sdio1_resources[] = {
305 {
306 .start = DOVE_SDIO1_PHYS_BASE,
307 .end = DOVE_SDIO1_PHYS_BASE + 0xff,
308 .flags = IORESOURCE_MEM,
309 }, {
310 .start = IRQ_DOVE_SDIO1,
311 .end = IRQ_DOVE_SDIO1,
312 .flags = IORESOURCE_IRQ,
313 },
314 };
315
316 static struct platform_device dove_sdio1 = {
317 .name = "sdhci-dove",
318 .id = 1,
319 .dev = {
320 .dma_mask = &sdio_dmamask,
321 .coherent_dma_mask = DMA_BIT_MASK(32),
322 },
323 .resource = dove_sdio1_resources,
324 .num_resources = ARRAY_SIZE(dove_sdio1_resources),
325 };
326
dove_sdio1_init(void)327 void __init dove_sdio1_init(void)
328 {
329 platform_device_register(&dove_sdio1);
330 }
331
dove_setup_cpu_wins(void)332 void __init dove_setup_cpu_wins(void)
333 {
334 /*
335 * The PCIe windows will no longer be statically allocated
336 * here once Dove is migrated to the pci-mvebu driver.
337 */
338 mvebu_mbus_add_window_remap_flags("pcie0.0",
339 DOVE_PCIE0_IO_PHYS_BASE,
340 DOVE_PCIE0_IO_SIZE,
341 DOVE_PCIE0_IO_BUS_BASE,
342 MVEBU_MBUS_PCI_IO);
343 mvebu_mbus_add_window_remap_flags("pcie1.0",
344 DOVE_PCIE1_IO_PHYS_BASE,
345 DOVE_PCIE1_IO_SIZE,
346 DOVE_PCIE1_IO_BUS_BASE,
347 MVEBU_MBUS_PCI_IO);
348 mvebu_mbus_add_window_remap_flags("pcie0.0",
349 DOVE_PCIE0_MEM_PHYS_BASE,
350 DOVE_PCIE0_MEM_SIZE,
351 MVEBU_MBUS_NO_REMAP,
352 MVEBU_MBUS_PCI_MEM);
353 mvebu_mbus_add_window_remap_flags("pcie1.0",
354 DOVE_PCIE1_MEM_PHYS_BASE,
355 DOVE_PCIE1_MEM_SIZE,
356 MVEBU_MBUS_NO_REMAP,
357 MVEBU_MBUS_PCI_MEM);
358 mvebu_mbus_add_window("cesa", DOVE_CESA_PHYS_BASE,
359 DOVE_CESA_SIZE);
360 mvebu_mbus_add_window("bootrom", DOVE_BOOTROM_PHYS_BASE,
361 DOVE_BOOTROM_SIZE);
362 mvebu_mbus_add_window("scratchpad", DOVE_SCRATCHPAD_PHYS_BASE,
363 DOVE_SCRATCHPAD_SIZE);
364 }
365
dove_init(void)366 void __init dove_init(void)
367 {
368 pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
369 (dove_tclk + 499999) / 1000000);
370
371 #ifdef CONFIG_CACHE_TAUROS2
372 tauros2_init(0);
373 #endif
374 dove_setup_cpu_wins();
375
376 /* Setup root of clk tree */
377 dove_clk_init();
378
379 /* internal devices that every board has */
380 dove_rtc_init();
381 dove_xor0_init();
382 dove_xor1_init();
383 }
384
dove_restart(char mode,const char * cmd)385 void dove_restart(char mode, const char *cmd)
386 {
387 /*
388 * Enable soft reset to assert RSTOUTn.
389 */
390 writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
391
392 /*
393 * Assert soft reset.
394 */
395 writel(SOFT_RESET, SYSTEM_SOFT_RESET);
396
397 while (1)
398 ;
399 }
400