1 /*
2 * Copyright (C) 2009 by Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/clk.h>
23 #include <linux/io.h>
24 #include <linux/clkdev.h>
25 #include <linux/err.h>
26 #include <linux/of.h>
27 #include <linux/of_address.h>
28 #include <linux/of_irq.h>
29
30 #include "clk.h"
31 #include "common.h"
32 #include "hardware.h"
33 #include "mx25.h"
34
35 #define CRM_BASE MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)
36
37 #define CCM_MPCTL 0x00
38 #define CCM_UPCTL 0x04
39 #define CCM_CCTL 0x08
40 #define CCM_CGCR0 0x0C
41 #define CCM_CGCR1 0x10
42 #define CCM_CGCR2 0x14
43 #define CCM_PCDR0 0x18
44 #define CCM_PCDR1 0x1C
45 #define CCM_PCDR2 0x20
46 #define CCM_PCDR3 0x24
47 #define CCM_RCSR 0x28
48 #define CCM_CRDR 0x2C
49 #define CCM_DCVR0 0x30
50 #define CCM_DCVR1 0x34
51 #define CCM_DCVR2 0x38
52 #define CCM_DCVR3 0x3c
53 #define CCM_LTR0 0x40
54 #define CCM_LTR1 0x44
55 #define CCM_LTR2 0x48
56 #define CCM_LTR3 0x4c
57 #define CCM_MCR 0x64
58
59 #define ccm(x) (CRM_BASE + (x))
60
61 static struct clk_onecell_data clk_data;
62
63 static const char *cpu_sel_clks[] = { "mpll", "mpll_cpu_3_4", };
64 static const char *per_sel_clks[] = { "ahb", "upll", };
65
66 enum mx25_clks {
67 dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg,
68 per0_sel, per1_sel, per2_sel, per3_sel, per4_sel, per5_sel, per6_sel,
69 per7_sel, per8_sel, per9_sel, per10_sel, per11_sel, per12_sel,
70 per13_sel, per14_sel, per15_sel, per0, per1, per2, per3, per4, per5,
71 per6, per7, per8, per9, per10, per11, per12, per13, per14, per15,
72 csi_ipg_per, epit_ipg_per, esai_ipg_per, esdhc1_ipg_per, esdhc2_ipg_per,
73 gpt_ipg_per, i2c_ipg_per, lcdc_ipg_per, nfc_ipg_per, owire_ipg_per,
74 pwm_ipg_per, sim1_ipg_per, sim2_ipg_per, ssi1_ipg_per, ssi2_ipg_per,
75 uart_ipg_per, ata_ahb, reserved1, csi_ahb, emi_ahb, esai_ahb, esdhc1_ahb,
76 esdhc2_ahb, fec_ahb, lcdc_ahb, rtic_ahb, sdma_ahb, slcdc_ahb, usbotg_ahb,
77 reserved2, reserved3, reserved4, reserved5, can1_ipg, can2_ipg, csi_ipg,
78 cspi1_ipg, cspi2_ipg, cspi3_ipg, dryice_ipg, ect_ipg, epit1_ipg, epit2_ipg,
79 reserved6, esdhc1_ipg, esdhc2_ipg, fec_ipg, reserved7, reserved8, reserved9,
80 gpt1_ipg, gpt2_ipg, gpt3_ipg, gpt4_ipg, reserved10, reserved11, reserved12,
81 iim_ipg, reserved13, reserved14, kpp_ipg, lcdc_ipg, reserved15, pwm1_ipg,
82 pwm2_ipg, pwm3_ipg, pwm4_ipg, rngb_ipg, reserved16, scc_ipg, sdma_ipg,
83 sim1_ipg, sim2_ipg, slcdc_ipg, spba_ipg, ssi1_ipg, ssi2_ipg, tsc_ipg,
84 uart1_ipg, uart2_ipg, uart3_ipg, uart4_ipg, uart5_ipg, reserved17,
85 wdt_ipg, clk_max
86 };
87
88 static struct clk *clk[clk_max];
89
__mx25_clocks_init(unsigned long osc_rate)90 static int __init __mx25_clocks_init(unsigned long osc_rate)
91 {
92 int i;
93
94 clk[dummy] = imx_clk_fixed("dummy", 0);
95 clk[osc] = imx_clk_fixed("osc", osc_rate);
96 clk[mpll] = imx_clk_pllv1("mpll", "osc", ccm(CCM_MPCTL));
97 clk[upll] = imx_clk_pllv1("upll", "osc", ccm(CCM_UPCTL));
98 clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4);
99 clk[cpu_sel] = imx_clk_mux("cpu_sel", ccm(CCM_CCTL), 14, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
100 clk[cpu] = imx_clk_divider("cpu", "cpu_sel", ccm(CCM_CCTL), 30, 2);
101 clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2);
102 clk[usb_div] = imx_clk_divider("usb_div", "upll", ccm(CCM_CCTL), 16, 6);
103 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
104 clk[per0_sel] = imx_clk_mux("per0_sel", ccm(CCM_MCR), 0, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
105 clk[per1_sel] = imx_clk_mux("per1_sel", ccm(CCM_MCR), 1, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
106 clk[per2_sel] = imx_clk_mux("per2_sel", ccm(CCM_MCR), 2, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
107 clk[per3_sel] = imx_clk_mux("per3_sel", ccm(CCM_MCR), 3, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
108 clk[per4_sel] = imx_clk_mux("per4_sel", ccm(CCM_MCR), 4, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
109 clk[per5_sel] = imx_clk_mux("per5_sel", ccm(CCM_MCR), 5, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
110 clk[per6_sel] = imx_clk_mux("per6_sel", ccm(CCM_MCR), 6, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
111 clk[per7_sel] = imx_clk_mux("per7_sel", ccm(CCM_MCR), 7, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
112 clk[per8_sel] = imx_clk_mux("per8_sel", ccm(CCM_MCR), 8, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
113 clk[per9_sel] = imx_clk_mux("per9_sel", ccm(CCM_MCR), 9, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
114 clk[per10_sel] = imx_clk_mux("per10_sel", ccm(CCM_MCR), 10, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
115 clk[per11_sel] = imx_clk_mux("per11_sel", ccm(CCM_MCR), 11, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
116 clk[per12_sel] = imx_clk_mux("per12_sel", ccm(CCM_MCR), 12, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
117 clk[per13_sel] = imx_clk_mux("per13_sel", ccm(CCM_MCR), 13, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
118 clk[per14_sel] = imx_clk_mux("per14_sel", ccm(CCM_MCR), 14, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
119 clk[per15_sel] = imx_clk_mux("per15_sel", ccm(CCM_MCR), 15, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
120 clk[per0] = imx_clk_divider("per0", "per0_sel", ccm(CCM_PCDR0), 0, 6);
121 clk[per1] = imx_clk_divider("per1", "per1_sel", ccm(CCM_PCDR0), 8, 6);
122 clk[per2] = imx_clk_divider("per2", "per2_sel", ccm(CCM_PCDR0), 16, 6);
123 clk[per3] = imx_clk_divider("per3", "per3_sel", ccm(CCM_PCDR0), 24, 6);
124 clk[per4] = imx_clk_divider("per4", "per4_sel", ccm(CCM_PCDR1), 0, 6);
125 clk[per5] = imx_clk_divider("per5", "per5_sel", ccm(CCM_PCDR1), 8, 6);
126 clk[per6] = imx_clk_divider("per6", "per6_sel", ccm(CCM_PCDR1), 16, 6);
127 clk[per7] = imx_clk_divider("per7", "per7_sel", ccm(CCM_PCDR1), 24, 6);
128 clk[per8] = imx_clk_divider("per8", "per8_sel", ccm(CCM_PCDR2), 0, 6);
129 clk[per9] = imx_clk_divider("per9", "per9_sel", ccm(CCM_PCDR2), 8, 6);
130 clk[per10] = imx_clk_divider("per10", "per10_sel", ccm(CCM_PCDR2), 16, 6);
131 clk[per11] = imx_clk_divider("per11", "per11_sel", ccm(CCM_PCDR2), 24, 6);
132 clk[per12] = imx_clk_divider("per12", "per12_sel", ccm(CCM_PCDR3), 0, 6);
133 clk[per13] = imx_clk_divider("per13", "per13_sel", ccm(CCM_PCDR3), 8, 6);
134 clk[per14] = imx_clk_divider("per14", "per14_sel", ccm(CCM_PCDR3), 16, 6);
135 clk[per15] = imx_clk_divider("per15", "per15_sel", ccm(CCM_PCDR3), 24, 6);
136 clk[csi_ipg_per] = imx_clk_gate("csi_ipg_per", "per0", ccm(CCM_CGCR0), 0);
137 clk[epit_ipg_per] = imx_clk_gate("epit_ipg_per", "per1", ccm(CCM_CGCR0), 1);
138 clk[esai_ipg_per] = imx_clk_gate("esai_ipg_per", "per2", ccm(CCM_CGCR0), 2);
139 clk[esdhc1_ipg_per] = imx_clk_gate("esdhc1_ipg_per", "per3", ccm(CCM_CGCR0), 3);
140 clk[esdhc2_ipg_per] = imx_clk_gate("esdhc2_ipg_per", "per4", ccm(CCM_CGCR0), 4);
141 clk[gpt_ipg_per] = imx_clk_gate("gpt_ipg_per", "per5", ccm(CCM_CGCR0), 5);
142 clk[i2c_ipg_per] = imx_clk_gate("i2c_ipg_per", "per6", ccm(CCM_CGCR0), 6);
143 clk[lcdc_ipg_per] = imx_clk_gate("lcdc_ipg_per", "per7", ccm(CCM_CGCR0), 7);
144 clk[nfc_ipg_per] = imx_clk_gate("nfc_ipg_per", "per8", ccm(CCM_CGCR0), 8);
145 clk[owire_ipg_per] = imx_clk_gate("owire_ipg_per", "per9", ccm(CCM_CGCR0), 9);
146 clk[pwm_ipg_per] = imx_clk_gate("pwm_ipg_per", "per10", ccm(CCM_CGCR0), 10);
147 clk[sim1_ipg_per] = imx_clk_gate("sim1_ipg_per", "per11", ccm(CCM_CGCR0), 11);
148 clk[sim2_ipg_per] = imx_clk_gate("sim2_ipg_per", "per12", ccm(CCM_CGCR0), 12);
149 clk[ssi1_ipg_per] = imx_clk_gate("ssi1_ipg_per", "per13", ccm(CCM_CGCR0), 13);
150 clk[ssi2_ipg_per] = imx_clk_gate("ssi2_ipg_per", "per14", ccm(CCM_CGCR0), 14);
151 clk[uart_ipg_per] = imx_clk_gate("uart_ipg_per", "per15", ccm(CCM_CGCR0), 15);
152 clk[ata_ahb] = imx_clk_gate("ata_ahb", "ahb", ccm(CCM_CGCR0), 16);
153 /* CCM_CGCR0(17): reserved */
154 clk[csi_ahb] = imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18);
155 clk[emi_ahb] = imx_clk_gate("emi_ahb", "ahb", ccm(CCM_CGCR0), 19);
156 clk[esai_ahb] = imx_clk_gate("esai_ahb", "ahb", ccm(CCM_CGCR0), 20);
157 clk[esdhc1_ahb] = imx_clk_gate("esdhc1_ahb", "ahb", ccm(CCM_CGCR0), 21);
158 clk[esdhc2_ahb] = imx_clk_gate("esdhc2_ahb", "ahb", ccm(CCM_CGCR0), 22);
159 clk[fec_ahb] = imx_clk_gate("fec_ahb", "ahb", ccm(CCM_CGCR0), 23);
160 clk[lcdc_ahb] = imx_clk_gate("lcdc_ahb", "ahb", ccm(CCM_CGCR0), 24);
161 clk[rtic_ahb] = imx_clk_gate("rtic_ahb", "ahb", ccm(CCM_CGCR0), 25);
162 clk[sdma_ahb] = imx_clk_gate("sdma_ahb", "ahb", ccm(CCM_CGCR0), 26);
163 clk[slcdc_ahb] = imx_clk_gate("slcdc_ahb", "ahb", ccm(CCM_CGCR0), 27);
164 clk[usbotg_ahb] = imx_clk_gate("usbotg_ahb", "ahb", ccm(CCM_CGCR0), 28);
165 /* CCM_CGCR0(29-31): reserved */
166 /* CCM_CGCR1(0): reserved in datasheet, used as audmux in FSL kernel */
167 clk[can1_ipg] = imx_clk_gate("can1_ipg", "ipg", ccm(CCM_CGCR1), 2);
168 clk[can2_ipg] = imx_clk_gate("can2_ipg", "ipg", ccm(CCM_CGCR1), 3);
169 clk[csi_ipg] = imx_clk_gate("csi_ipg", "ipg", ccm(CCM_CGCR1), 4);
170 clk[cspi1_ipg] = imx_clk_gate("cspi1_ipg", "ipg", ccm(CCM_CGCR1), 5);
171 clk[cspi2_ipg] = imx_clk_gate("cspi2_ipg", "ipg", ccm(CCM_CGCR1), 6);
172 clk[cspi3_ipg] = imx_clk_gate("cspi3_ipg", "ipg", ccm(CCM_CGCR1), 7);
173 clk[dryice_ipg] = imx_clk_gate("dryice_ipg", "ipg", ccm(CCM_CGCR1), 8);
174 clk[ect_ipg] = imx_clk_gate("ect_ipg", "ipg", ccm(CCM_CGCR1), 9);
175 clk[epit1_ipg] = imx_clk_gate("epit1_ipg", "ipg", ccm(CCM_CGCR1), 10);
176 clk[epit2_ipg] = imx_clk_gate("epit2_ipg", "ipg", ccm(CCM_CGCR1), 11);
177 /* CCM_CGCR1(12): reserved in datasheet, used as esai in FSL kernel */
178 clk[esdhc1_ipg] = imx_clk_gate("esdhc1_ipg", "ipg", ccm(CCM_CGCR1), 13);
179 clk[esdhc2_ipg] = imx_clk_gate("esdhc2_ipg", "ipg", ccm(CCM_CGCR1), 14);
180 clk[fec_ipg] = imx_clk_gate("fec_ipg", "ipg", ccm(CCM_CGCR1), 15);
181 /* CCM_CGCR1(16): reserved in datasheet, used as gpio1 in FSL kernel */
182 /* CCM_CGCR1(17): reserved in datasheet, used as gpio2 in FSL kernel */
183 /* CCM_CGCR1(18): reserved in datasheet, used as gpio3 in FSL kernel */
184 clk[gpt1_ipg] = imx_clk_gate("gpt1_ipg", "ipg", ccm(CCM_CGCR1), 19);
185 clk[gpt2_ipg] = imx_clk_gate("gpt2_ipg", "ipg", ccm(CCM_CGCR1), 20);
186 clk[gpt3_ipg] = imx_clk_gate("gpt3_ipg", "ipg", ccm(CCM_CGCR1), 21);
187 clk[gpt4_ipg] = imx_clk_gate("gpt4_ipg", "ipg", ccm(CCM_CGCR1), 22);
188 /* CCM_CGCR1(23): reserved in datasheet, used as i2c1 in FSL kernel */
189 /* CCM_CGCR1(24): reserved in datasheet, used as i2c2 in FSL kernel */
190 /* CCM_CGCR1(25): reserved in datasheet, used as i2c3 in FSL kernel */
191 clk[iim_ipg] = imx_clk_gate("iim_ipg", "ipg", ccm(CCM_CGCR1), 26);
192 /* CCM_CGCR1(27): reserved in datasheet, used as iomuxc in FSL kernel */
193 /* CCM_CGCR1(28): reserved in datasheet, used as kpp in FSL kernel */
194 clk[kpp_ipg] = imx_clk_gate("kpp_ipg", "ipg", ccm(CCM_CGCR1), 28);
195 clk[lcdc_ipg] = imx_clk_gate("lcdc_ipg", "ipg", ccm(CCM_CGCR1), 29);
196 /* CCM_CGCR1(30): reserved in datasheet, used as owire in FSL kernel */
197 clk[pwm1_ipg] = imx_clk_gate("pwm1_ipg", "ipg", ccm(CCM_CGCR1), 31);
198 clk[pwm2_ipg] = imx_clk_gate("pwm2_ipg", "ipg", ccm(CCM_CGCR2), 0);
199 clk[pwm3_ipg] = imx_clk_gate("pwm3_ipg", "ipg", ccm(CCM_CGCR2), 1);
200 clk[pwm4_ipg] = imx_clk_gate("pwm4_ipg", "ipg", ccm(CCM_CGCR2), 2);
201 clk[rngb_ipg] = imx_clk_gate("rngb_ipg", "ipg", ccm(CCM_CGCR2), 3);
202 /* CCM_CGCR2(4): reserved in datasheet, used as rtic in FSL kernel */
203 clk[scc_ipg] = imx_clk_gate("scc_ipg", "ipg", ccm(CCM_CGCR2), 5);
204 clk[sdma_ipg] = imx_clk_gate("sdma_ipg", "ipg", ccm(CCM_CGCR2), 6);
205 clk[sim1_ipg] = imx_clk_gate("sim1_ipg", "ipg", ccm(CCM_CGCR2), 7);
206 clk[sim2_ipg] = imx_clk_gate("sim2_ipg", "ipg", ccm(CCM_CGCR2), 8);
207 clk[slcdc_ipg] = imx_clk_gate("slcdc_ipg", "ipg", ccm(CCM_CGCR2), 9);
208 clk[spba_ipg] = imx_clk_gate("spba_ipg", "ipg", ccm(CCM_CGCR2), 10);
209 clk[ssi1_ipg] = imx_clk_gate("ssi1_ipg", "ipg", ccm(CCM_CGCR2), 11);
210 clk[ssi2_ipg] = imx_clk_gate("ssi2_ipg", "ipg", ccm(CCM_CGCR2), 12);
211 clk[tsc_ipg] = imx_clk_gate("tsc_ipg", "ipg", ccm(CCM_CGCR2), 13);
212 clk[uart1_ipg] = imx_clk_gate("uart1_ipg", "ipg", ccm(CCM_CGCR2), 14);
213 clk[uart2_ipg] = imx_clk_gate("uart2_ipg", "ipg", ccm(CCM_CGCR2), 15);
214 clk[uart3_ipg] = imx_clk_gate("uart3_ipg", "ipg", ccm(CCM_CGCR2), 16);
215 clk[uart4_ipg] = imx_clk_gate("uart4_ipg", "ipg", ccm(CCM_CGCR2), 17);
216 clk[uart5_ipg] = imx_clk_gate("uart5_ipg", "ipg", ccm(CCM_CGCR2), 18);
217 /* CCM_CGCR2(19): reserved in datasheet, but used as wdt in FSL kernel */
218 clk[wdt_ipg] = imx_clk_gate("wdt_ipg", "ipg", ccm(CCM_CGCR2), 19);
219
220 for (i = 0; i < ARRAY_SIZE(clk); i++)
221 if (IS_ERR(clk[i]))
222 pr_err("i.MX25 clk %d: register failed with %ld\n",
223 i, PTR_ERR(clk[i]));
224
225 clk_prepare_enable(clk[emi_ahb]);
226
227 /* Clock source for gpt must be derived from AHB */
228 clk_set_parent(clk[per5_sel], clk[ahb]);
229
230 clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
231 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
232
233 return 0;
234 }
235
mx25_clocks_init(void)236 int __init mx25_clocks_init(void)
237 {
238 __mx25_clocks_init(24000000);
239
240 /* i.mx25 has the i.mx21 type uart */
241 clk_register_clkdev(clk[uart1_ipg], "ipg", "imx21-uart.0");
242 clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.0");
243 clk_register_clkdev(clk[uart2_ipg], "ipg", "imx21-uart.1");
244 clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.1");
245 clk_register_clkdev(clk[uart3_ipg], "ipg", "imx21-uart.2");
246 clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.2");
247 clk_register_clkdev(clk[uart4_ipg], "ipg", "imx21-uart.3");
248 clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.3");
249 clk_register_clkdev(clk[uart5_ipg], "ipg", "imx21-uart.4");
250 clk_register_clkdev(clk[uart_ipg_per], "per", "imx21-uart.4");
251 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
252 clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.0");
253 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
254 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1");
255 clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.1");
256 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
257 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2");
258 clk_register_clkdev(clk[usbotg_ahb], "ahb", "mxc-ehci.2");
259 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
260 clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27");
261 clk_register_clkdev(clk[usbotg_ahb], "ahb", "imx-udc-mx27");
262 clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27");
263 clk_register_clkdev(clk[nfc_ipg_per], NULL, "imx25-nand.0");
264 /* i.mx25 has the i.mx35 type cspi */
265 clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0");
266 clk_register_clkdev(clk[cspi2_ipg], NULL, "imx35-cspi.1");
267 clk_register_clkdev(clk[cspi3_ipg], NULL, "imx35-cspi.2");
268 clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.0");
269 clk_register_clkdev(clk[per10], "per", "mxc_pwm.0");
270 clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.1");
271 clk_register_clkdev(clk[per10], "per", "mxc_pwm.1");
272 clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.2");
273 clk_register_clkdev(clk[per10], "per", "mxc_pwm.2");
274 clk_register_clkdev(clk[pwm1_ipg], "ipg", "mxc_pwm.3");
275 clk_register_clkdev(clk[per10], "per", "mxc_pwm.3");
276 clk_register_clkdev(clk[kpp_ipg], NULL, "imx-keypad");
277 clk_register_clkdev(clk[tsc_ipg], NULL, "mx25-adc");
278 clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.0");
279 clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.1");
280 clk_register_clkdev(clk[i2c_ipg_per], NULL, "imx21-i2c.2");
281 clk_register_clkdev(clk[fec_ipg], "ipg", "imx25-fec.0");
282 clk_register_clkdev(clk[fec_ahb], "ahb", "imx25-fec.0");
283 clk_register_clkdev(clk[dryice_ipg], NULL, "imxdi_rtc.0");
284 clk_register_clkdev(clk[lcdc_ipg_per], "per", "imx21-fb.0");
285 clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx21-fb.0");
286 clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx21-fb.0");
287 clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0");
288 clk_register_clkdev(clk[ssi1_ipg], NULL, "imx-ssi.0");
289 clk_register_clkdev(clk[ssi2_ipg], NULL, "imx-ssi.1");
290 clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0");
291 clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0");
292 clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0");
293 clk_register_clkdev(clk[esdhc2_ipg_per], "per", "sdhci-esdhc-imx25.1");
294 clk_register_clkdev(clk[esdhc2_ipg], "ipg", "sdhci-esdhc-imx25.1");
295 clk_register_clkdev(clk[esdhc2_ahb], "ahb", "sdhci-esdhc-imx25.1");
296 clk_register_clkdev(clk[csi_ipg_per], "per", "imx25-camera.0");
297 clk_register_clkdev(clk[csi_ipg], "ipg", "imx25-camera.0");
298 clk_register_clkdev(clk[csi_ahb], "ahb", "imx25-camera.0");
299 clk_register_clkdev(clk[dummy], "audmux", NULL);
300 clk_register_clkdev(clk[can1_ipg], NULL, "flexcan.0");
301 clk_register_clkdev(clk[can2_ipg], NULL, "flexcan.1");
302 /* i.mx25 has the i.mx35 type sdma */
303 clk_register_clkdev(clk[sdma_ipg], "ipg", "imx35-sdma");
304 clk_register_clkdev(clk[sdma_ahb], "ahb", "imx35-sdma");
305 clk_register_clkdev(clk[iim_ipg], "iim", NULL);
306
307 mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), MX25_INT_GPT1);
308
309 return 0;
310 }
311
mx25_clocks_init_dt(void)312 int __init mx25_clocks_init_dt(void)
313 {
314 struct device_node *np;
315 void __iomem *base;
316 int irq;
317 unsigned long osc_rate = 24000000;
318
319 /* retrieve the freqency of fixed clocks from device tree */
320 for_each_compatible_node(np, NULL, "fixed-clock") {
321 u32 rate;
322 if (of_property_read_u32(np, "clock-frequency", &rate))
323 continue;
324
325 if (of_device_is_compatible(np, "fsl,imx-osc"))
326 osc_rate = rate;
327 }
328
329 np = of_find_compatible_node(NULL, NULL, "fsl,imx25-ccm");
330 clk_data.clks = clk;
331 clk_data.clk_num = ARRAY_SIZE(clk);
332 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
333
334 __mx25_clocks_init(osc_rate);
335
336 np = of_find_compatible_node(NULL, NULL, "fsl,imx25-gpt");
337 base = of_iomap(np, 0);
338 WARN_ON(!base);
339 irq = irq_of_parse_and_map(np, 0);
340
341 mxc_timer_init(base, irq);
342
343 return 0;
344 }
345