1 /*
2 * arch/arm/mach-ixp4xx/ixdp425-setup.c
3 *
4 * IXDP425/IXCDP1100 board-setup
5 *
6 * Copyright (C) 2003-2005 MontaVista Software, Inc.
7 *
8 * Author: Deepak Saxena <dsaxena@plexity.net>
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/device.h>
14 #include <linux/serial.h>
15 #include <linux/tty.h>
16 #include <linux/serial_8250.h>
17 #include <linux/i2c-gpio.h>
18 #include <linux/io.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/nand.h>
21 #include <linux/mtd/partitions.h>
22 #include <linux/delay.h>
23 #include <asm/types.h>
24 #include <asm/setup.h>
25 #include <asm/memory.h>
26 #include <mach/hardware.h>
27 #include <asm/mach-types.h>
28 #include <asm/irq.h>
29 #include <asm/mach/arch.h>
30 #include <asm/mach/flash.h>
31
32 #define IXDP425_SDA_PIN 7
33 #define IXDP425_SCL_PIN 6
34
35 /* NAND Flash pins */
36 #define IXDP425_NAND_NCE_PIN 12
37
38 #define IXDP425_NAND_CMD_BYTE 0x01
39 #define IXDP425_NAND_ADDR_BYTE 0x02
40
41 static struct flash_platform_data ixdp425_flash_data = {
42 .map_name = "cfi_probe",
43 .width = 2,
44 };
45
46 static struct resource ixdp425_flash_resource = {
47 .flags = IORESOURCE_MEM,
48 };
49
50 static struct platform_device ixdp425_flash = {
51 .name = "IXP4XX-Flash",
52 .id = 0,
53 .dev = {
54 .platform_data = &ixdp425_flash_data,
55 },
56 .num_resources = 1,
57 .resource = &ixdp425_flash_resource,
58 };
59
60 #if defined(CONFIG_MTD_NAND_PLATFORM) || \
61 defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
62
63 static struct mtd_partition ixdp425_partitions[] = {
64 {
65 .name = "ixp400 NAND FS 0",
66 .offset = 0,
67 .size = SZ_8M
68 }, {
69 .name = "ixp400 NAND FS 1",
70 .offset = MTDPART_OFS_APPEND,
71 .size = MTDPART_SIZ_FULL
72 },
73 };
74
75 static void
ixdp425_flash_nand_cmd_ctrl(struct mtd_info * mtd,int cmd,unsigned int ctrl)76 ixdp425_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
77 {
78 struct nand_chip *this = mtd->priv;
79 int offset = (int)this->priv;
80
81 if (ctrl & NAND_CTRL_CHANGE) {
82 if (ctrl & NAND_NCE) {
83 gpio_line_set(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_LOW);
84 udelay(5);
85 } else
86 gpio_line_set(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_HIGH);
87
88 offset = (ctrl & NAND_CLE) ? IXDP425_NAND_CMD_BYTE : 0;
89 offset |= (ctrl & NAND_ALE) ? IXDP425_NAND_ADDR_BYTE : 0;
90 this->priv = (void *)offset;
91 }
92
93 if (cmd != NAND_CMD_NONE)
94 writeb(cmd, this->IO_ADDR_W + offset);
95 }
96
97 static struct platform_nand_data ixdp425_flash_nand_data = {
98 .chip = {
99 .nr_chips = 1,
100 .chip_delay = 30,
101 .partitions = ixdp425_partitions,
102 .nr_partitions = ARRAY_SIZE(ixdp425_partitions),
103 },
104 .ctrl = {
105 .cmd_ctrl = ixdp425_flash_nand_cmd_ctrl
106 }
107 };
108
109 static struct resource ixdp425_flash_nand_resource = {
110 .flags = IORESOURCE_MEM,
111 };
112
113 static struct platform_device ixdp425_flash_nand = {
114 .name = "gen_nand",
115 .id = -1,
116 .dev = {
117 .platform_data = &ixdp425_flash_nand_data,
118 },
119 .num_resources = 1,
120 .resource = &ixdp425_flash_nand_resource,
121 };
122 #endif /* CONFIG_MTD_NAND_PLATFORM */
123
124 static struct i2c_gpio_platform_data ixdp425_i2c_gpio_data = {
125 .sda_pin = IXDP425_SDA_PIN,
126 .scl_pin = IXDP425_SCL_PIN,
127 };
128
129 static struct platform_device ixdp425_i2c_gpio = {
130 .name = "i2c-gpio",
131 .id = 0,
132 .dev = {
133 .platform_data = &ixdp425_i2c_gpio_data,
134 },
135 };
136
137 static struct resource ixdp425_uart_resources[] = {
138 {
139 .start = IXP4XX_UART1_BASE_PHYS,
140 .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
141 .flags = IORESOURCE_MEM
142 },
143 {
144 .start = IXP4XX_UART2_BASE_PHYS,
145 .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
146 .flags = IORESOURCE_MEM
147 }
148 };
149
150 static struct plat_serial8250_port ixdp425_uart_data[] = {
151 {
152 .mapbase = IXP4XX_UART1_BASE_PHYS,
153 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
154 .irq = IRQ_IXP4XX_UART1,
155 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
156 .iotype = UPIO_MEM,
157 .regshift = 2,
158 .uartclk = IXP4XX_UART_XTAL,
159 },
160 {
161 .mapbase = IXP4XX_UART2_BASE_PHYS,
162 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
163 .irq = IRQ_IXP4XX_UART2,
164 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
165 .iotype = UPIO_MEM,
166 .regshift = 2,
167 .uartclk = IXP4XX_UART_XTAL,
168 },
169 { },
170 };
171
172 static struct platform_device ixdp425_uart = {
173 .name = "serial8250",
174 .id = PLAT8250_DEV_PLATFORM,
175 .dev.platform_data = ixdp425_uart_data,
176 .num_resources = 2,
177 .resource = ixdp425_uart_resources
178 };
179
180 /* Built-in 10/100 Ethernet MAC interfaces */
181 static struct eth_plat_info ixdp425_plat_eth[] = {
182 {
183 .phy = 0,
184 .rxq = 3,
185 .txreadyq = 20,
186 }, {
187 .phy = 1,
188 .rxq = 4,
189 .txreadyq = 21,
190 }
191 };
192
193 static struct platform_device ixdp425_eth[] = {
194 {
195 .name = "ixp4xx_eth",
196 .id = IXP4XX_ETH_NPEB,
197 .dev.platform_data = ixdp425_plat_eth,
198 }, {
199 .name = "ixp4xx_eth",
200 .id = IXP4XX_ETH_NPEC,
201 .dev.platform_data = ixdp425_plat_eth + 1,
202 }
203 };
204
205 static struct platform_device *ixdp425_devices[] __initdata = {
206 &ixdp425_i2c_gpio,
207 &ixdp425_flash,
208 #if defined(CONFIG_MTD_NAND_PLATFORM) || \
209 defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
210 &ixdp425_flash_nand,
211 #endif
212 &ixdp425_uart,
213 &ixdp425_eth[0],
214 &ixdp425_eth[1],
215 };
216
ixdp425_init(void)217 static void __init ixdp425_init(void)
218 {
219 ixp4xx_sys_init();
220
221 ixdp425_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
222 ixdp425_flash_resource.end =
223 IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
224
225 #if defined(CONFIG_MTD_NAND_PLATFORM) || \
226 defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
227 ixdp425_flash_nand_resource.start = IXP4XX_EXP_BUS_BASE(3),
228 ixdp425_flash_nand_resource.end = IXP4XX_EXP_BUS_BASE(3) + 0x10 - 1;
229
230 gpio_line_config(IXDP425_NAND_NCE_PIN, IXP4XX_GPIO_OUT);
231
232 /* Configure expansion bus for NAND Flash */
233 *IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN |
234 IXP4XX_EXP_BUS_STROBE_T(1) | /* extend by 1 clock */
235 IXP4XX_EXP_BUS_CYCLES(0) | /* Intel cycles */
236 IXP4XX_EXP_BUS_SIZE(0) | /* 512bytes addr space*/
237 IXP4XX_EXP_BUS_WR_EN |
238 IXP4XX_EXP_BUS_BYTE_EN; /* 8 bit data bus */
239 #endif
240
241 if (cpu_is_ixp43x()) {
242 ixdp425_uart.num_resources = 1;
243 ixdp425_uart_data[1].flags = 0;
244 }
245
246 platform_add_devices(ixdp425_devices, ARRAY_SIZE(ixdp425_devices));
247 }
248
249 #ifdef CONFIG_ARCH_IXDP425
250 MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
251 /* Maintainer: MontaVista Software, Inc. */
252 .map_io = ixp4xx_map_io,
253 .init_early = ixp4xx_init_early,
254 .init_irq = ixp4xx_init_irq,
255 .init_time = ixp4xx_timer_init,
256 .atag_offset = 0x100,
257 .init_machine = ixdp425_init,
258 #if defined(CONFIG_PCI)
259 .dma_zone_size = SZ_64M,
260 #endif
261 .restart = ixp4xx_restart,
262 MACHINE_END
263 #endif
264
265 #ifdef CONFIG_MACH_IXDP465
266 MACHINE_START(IXDP465, "Intel IXDP465 Development Platform")
267 /* Maintainer: MontaVista Software, Inc. */
268 .map_io = ixp4xx_map_io,
269 .init_early = ixp4xx_init_early,
270 .init_irq = ixp4xx_init_irq,
271 .init_time = ixp4xx_timer_init,
272 .atag_offset = 0x100,
273 .init_machine = ixdp425_init,
274 #if defined(CONFIG_PCI)
275 .dma_zone_size = SZ_64M,
276 #endif
277 MACHINE_END
278 #endif
279
280 #ifdef CONFIG_ARCH_PRPMC1100
281 MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
282 /* Maintainer: MontaVista Software, Inc. */
283 .map_io = ixp4xx_map_io,
284 .init_early = ixp4xx_init_early,
285 .init_irq = ixp4xx_init_irq,
286 .init_time = ixp4xx_timer_init,
287 .atag_offset = 0x100,
288 .init_machine = ixdp425_init,
289 #if defined(CONFIG_PCI)
290 .dma_zone_size = SZ_64M,
291 #endif
292 MACHINE_END
293 #endif
294
295 #ifdef CONFIG_MACH_KIXRP435
296 MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")
297 /* Maintainer: MontaVista Software, Inc. */
298 .map_io = ixp4xx_map_io,
299 .init_early = ixp4xx_init_early,
300 .init_irq = ixp4xx_init_irq,
301 .init_time = ixp4xx_timer_init,
302 .atag_offset = 0x100,
303 .init_machine = ixdp425_init,
304 #if defined(CONFIG_PCI)
305 .dma_zone_size = SZ_64M,
306 #endif
307 MACHINE_END
308 #endif
309