1 /*
2 * arch/arm/mach-orion5x/common.c
3 *
4 * Core functions for Marvell Orion 5x SoCs
5 *
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/serial_8250.h>
18 #include <linux/mv643xx_i2c.h>
19 #include <linux/ata_platform.h>
20 #include <linux/delay.h>
21 #include <linux/clk-provider.h>
22 #include <linux/cpu.h>
23 #include <net/dsa.h>
24 #include <asm/page.h>
25 #include <asm/setup.h>
26 #include <asm/system_misc.h>
27 #include <asm/timex.h>
28 #include <asm/mach/arch.h>
29 #include <asm/mach/map.h>
30 #include <asm/mach/time.h>
31 #include <mach/bridge-regs.h>
32 #include <mach/hardware.h>
33 #include <mach/orion5x.h>
34 #include <linux/platform_data/mtd-orion_nand.h>
35 #include <linux/platform_data/usb-ehci-orion.h>
36 #include <plat/time.h>
37 #include <plat/common.h>
38 #include "common.h"
39
40 /*****************************************************************************
41 * I/O Address Mapping
42 ****************************************************************************/
43 static struct map_desc orion5x_io_desc[] __initdata = {
44 {
45 .virtual = (unsigned long) ORION5X_REGS_VIRT_BASE,
46 .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
47 .length = ORION5X_REGS_SIZE,
48 .type = MT_DEVICE,
49 }, {
50 .virtual = (unsigned long) ORION5X_PCIE_WA_VIRT_BASE,
51 .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
52 .length = ORION5X_PCIE_WA_SIZE,
53 .type = MT_DEVICE,
54 },
55 };
56
orion5x_map_io(void)57 void __init orion5x_map_io(void)
58 {
59 iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
60 }
61
62
63 /*****************************************************************************
64 * CLK tree
65 ****************************************************************************/
66 static struct clk *tclk;
67
clk_init(void)68 void __init clk_init(void)
69 {
70 tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
71 orion5x_tclk);
72
73 orion_clkdev_init(tclk);
74 }
75
76 /*****************************************************************************
77 * EHCI0
78 ****************************************************************************/
orion5x_ehci0_init(void)79 void __init orion5x_ehci0_init(void)
80 {
81 orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL,
82 EHCI_PHY_ORION);
83 }
84
85
86 /*****************************************************************************
87 * EHCI1
88 ****************************************************************************/
orion5x_ehci1_init(void)89 void __init orion5x_ehci1_init(void)
90 {
91 orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
92 }
93
94
95 /*****************************************************************************
96 * GE00
97 ****************************************************************************/
orion5x_eth_init(struct mv643xx_eth_platform_data * eth_data)98 void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
99 {
100 orion_ge00_init(eth_data,
101 ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
102 IRQ_ORION5X_ETH_ERR,
103 MV643XX_TX_CSUM_DEFAULT_LIMIT);
104 }
105
106
107 /*****************************************************************************
108 * Ethernet switch
109 ****************************************************************************/
orion5x_eth_switch_init(struct dsa_platform_data * d,int irq)110 void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
111 {
112 orion_ge00_switch_init(d, irq);
113 }
114
115
116 /*****************************************************************************
117 * I2C
118 ****************************************************************************/
orion5x_i2c_init(void)119 void __init orion5x_i2c_init(void)
120 {
121 orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8);
122
123 }
124
125
126 /*****************************************************************************
127 * SATA
128 ****************************************************************************/
orion5x_sata_init(struct mv_sata_platform_data * sata_data)129 void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
130 {
131 orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
132 }
133
134
135 /*****************************************************************************
136 * SPI
137 ****************************************************************************/
orion5x_spi_init()138 void __init orion5x_spi_init()
139 {
140 orion_spi_init(SPI_PHYS_BASE);
141 }
142
143
144 /*****************************************************************************
145 * UART0
146 ****************************************************************************/
orion5x_uart0_init(void)147 void __init orion5x_uart0_init(void)
148 {
149 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
150 IRQ_ORION5X_UART0, tclk);
151 }
152
153 /*****************************************************************************
154 * UART1
155 ****************************************************************************/
orion5x_uart1_init(void)156 void __init orion5x_uart1_init(void)
157 {
158 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
159 IRQ_ORION5X_UART1, tclk);
160 }
161
162 /*****************************************************************************
163 * XOR engine
164 ****************************************************************************/
orion5x_xor_init(void)165 void __init orion5x_xor_init(void)
166 {
167 orion_xor0_init(ORION5X_XOR_PHYS_BASE,
168 ORION5X_XOR_PHYS_BASE + 0x200,
169 IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
170 }
171
172 /*****************************************************************************
173 * Cryptographic Engines and Security Accelerator (CESA)
174 ****************************************************************************/
orion5x_crypto_init(void)175 static void __init orion5x_crypto_init(void)
176 {
177 mvebu_mbus_add_window("sram", ORION5X_SRAM_PHYS_BASE,
178 ORION5X_SRAM_SIZE);
179 orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
180 SZ_8K, IRQ_ORION5X_CESA);
181 }
182
183 /*****************************************************************************
184 * Watchdog
185 ****************************************************************************/
orion5x_wdt_init(void)186 void __init orion5x_wdt_init(void)
187 {
188 orion_wdt_init();
189 }
190
191
192 /*****************************************************************************
193 * Time handling
194 ****************************************************************************/
orion5x_init_early(void)195 void __init orion5x_init_early(void)
196 {
197 u32 rev, dev;
198 const char *mbus_soc_name;
199
200 orion_time_set_base(TIMER_VIRT_BASE);
201
202 /* Initialize the MBUS driver */
203 orion5x_pcie_id(&dev, &rev);
204 if (dev == MV88F5281_DEV_ID)
205 mbus_soc_name = "marvell,orion5x-88f5281-mbus";
206 else if (dev == MV88F5182_DEV_ID)
207 mbus_soc_name = "marvell,orion5x-88f5182-mbus";
208 else if (dev == MV88F5181_DEV_ID)
209 mbus_soc_name = "marvell,orion5x-88f5181-mbus";
210 else if (dev == MV88F6183_DEV_ID)
211 mbus_soc_name = "marvell,orion5x-88f6183-mbus";
212 else
213 mbus_soc_name = NULL;
214 mvebu_mbus_init(mbus_soc_name, ORION5X_BRIDGE_WINS_BASE,
215 ORION5X_BRIDGE_WINS_SZ,
216 ORION5X_DDR_WINS_BASE, ORION5X_DDR_WINS_SZ);
217 }
218
orion5x_setup_wins(void)219 void orion5x_setup_wins(void)
220 {
221 /*
222 * The PCIe windows will no longer be statically allocated
223 * here once Orion5x is migrated to the pci-mvebu driver.
224 */
225 mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_IO_PHYS_BASE,
226 ORION5X_PCIE_IO_SIZE,
227 ORION5X_PCIE_IO_BUS_BASE,
228 MVEBU_MBUS_PCI_IO);
229 mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_MEM_PHYS_BASE,
230 ORION5X_PCIE_MEM_SIZE,
231 MVEBU_MBUS_NO_REMAP,
232 MVEBU_MBUS_PCI_MEM);
233 mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_IO_PHYS_BASE,
234 ORION5X_PCI_IO_SIZE,
235 ORION5X_PCI_IO_BUS_BASE,
236 MVEBU_MBUS_PCI_IO);
237 mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_MEM_PHYS_BASE,
238 ORION5X_PCI_MEM_SIZE,
239 MVEBU_MBUS_NO_REMAP,
240 MVEBU_MBUS_PCI_MEM);
241 }
242
243 int orion5x_tclk;
244
orion5x_find_tclk(void)245 int __init orion5x_find_tclk(void)
246 {
247 u32 dev, rev;
248
249 orion5x_pcie_id(&dev, &rev);
250 if (dev == MV88F6183_DEV_ID &&
251 (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
252 return 133333333;
253
254 return 166666667;
255 }
256
orion5x_timer_init(void)257 void __init orion5x_timer_init(void)
258 {
259 orion5x_tclk = orion5x_find_tclk();
260
261 orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
262 IRQ_ORION5X_BRIDGE, orion5x_tclk);
263 }
264
265
266 /*****************************************************************************
267 * General
268 ****************************************************************************/
269 /*
270 * Identify device ID and rev from PCIe configuration header space '0'.
271 */
orion5x_id(u32 * dev,u32 * rev,char ** dev_name)272 void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
273 {
274 orion5x_pcie_id(dev, rev);
275
276 if (*dev == MV88F5281_DEV_ID) {
277 if (*rev == MV88F5281_REV_D2) {
278 *dev_name = "MV88F5281-D2";
279 } else if (*rev == MV88F5281_REV_D1) {
280 *dev_name = "MV88F5281-D1";
281 } else if (*rev == MV88F5281_REV_D0) {
282 *dev_name = "MV88F5281-D0";
283 } else {
284 *dev_name = "MV88F5281-Rev-Unsupported";
285 }
286 } else if (*dev == MV88F5182_DEV_ID) {
287 if (*rev == MV88F5182_REV_A2) {
288 *dev_name = "MV88F5182-A2";
289 } else {
290 *dev_name = "MV88F5182-Rev-Unsupported";
291 }
292 } else if (*dev == MV88F5181_DEV_ID) {
293 if (*rev == MV88F5181_REV_B1) {
294 *dev_name = "MV88F5181-Rev-B1";
295 } else if (*rev == MV88F5181L_REV_A1) {
296 *dev_name = "MV88F5181L-Rev-A1";
297 } else {
298 *dev_name = "MV88F5181(L)-Rev-Unsupported";
299 }
300 } else if (*dev == MV88F6183_DEV_ID) {
301 if (*rev == MV88F6183_REV_B0) {
302 *dev_name = "MV88F6183-Rev-B0";
303 } else {
304 *dev_name = "MV88F6183-Rev-Unsupported";
305 }
306 } else {
307 *dev_name = "Device-Unknown";
308 }
309 }
310
orion5x_init(void)311 void __init orion5x_init(void)
312 {
313 char *dev_name;
314 u32 dev, rev;
315
316 orion5x_id(&dev, &rev, &dev_name);
317 printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
318
319 /*
320 * Setup Orion address map
321 */
322 orion5x_setup_wins();
323
324 /* Setup root of clk tree */
325 clk_init();
326
327 /*
328 * Don't issue "Wait for Interrupt" instruction if we are
329 * running on D0 5281 silicon.
330 */
331 if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
332 printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
333 cpu_idle_poll_ctrl(true);
334 }
335
336 /*
337 * The 5082/5181l/5182/6082/6082l/6183 have crypto
338 * while 5180n/5181/5281 don't have crypto.
339 */
340 if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) ||
341 dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID)
342 orion5x_crypto_init();
343
344 /*
345 * Register watchdog driver
346 */
347 orion5x_wdt_init();
348 }
349
orion5x_restart(char mode,const char * cmd)350 void orion5x_restart(char mode, const char *cmd)
351 {
352 /*
353 * Enable and issue soft reset
354 */
355 orion5x_setbits(RSTOUTn_MASK, (1 << 2));
356 orion5x_setbits(CPU_SOFT_RESET, 1);
357 mdelay(200);
358 orion5x_clrbits(CPU_SOFT_RESET, 1);
359 }
360
361 /*
362 * Many orion-based systems have buggy bootloader implementations.
363 * This is a common fixup for bogus memory tags.
364 */
tag_fixup_mem32(struct tag * t,char ** from,struct meminfo * meminfo)365 void __init tag_fixup_mem32(struct tag *t, char **from,
366 struct meminfo *meminfo)
367 {
368 for (; t->hdr.size; t = tag_next(t))
369 if (t->hdr.tag == ATAG_MEM &&
370 (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
371 t->u.mem.start & ~PAGE_MASK)) {
372 printk(KERN_WARNING
373 "Clearing invalid memory bank %dKB@0x%08x\n",
374 t->u.mem.size / 1024, t->u.mem.start);
375 t->hdr.tag = 0;
376 }
377 }
378