1 /* linux/arch/arm/mach-s3c2440/clock.c
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C2440 Clock support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24 #include <linux/init.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/list.h>
28 #include <linux/errno.h>
29 #include <linux/err.h>
30 #include <linux/device.h>
31 #include <linux/interrupt.h>
32 #include <linux/ioport.h>
33 #include <linux/mutex.h>
34 #include <linux/clk.h>
35 #include <linux/io.h>
36 #include <linux/serial_core.h>
37
38 #include <mach/hardware.h>
39 #include <linux/atomic.h>
40 #include <asm/irq.h>
41
42 #include <mach/regs-clock.h>
43
44 #include <plat/clock.h>
45 #include <plat/cpu.h>
46 #include <plat/regs-serial.h>
47
48 /* S3C2440 extended clock support */
49
s3c2440_camif_upll_round(struct clk * clk,unsigned long rate)50 static unsigned long s3c2440_camif_upll_round(struct clk *clk,
51 unsigned long rate)
52 {
53 unsigned long parent_rate = clk_get_rate(clk->parent);
54 int div;
55
56 if (rate > parent_rate)
57 return parent_rate;
58
59 /* note, we remove the +/- 1 calculations for the divisor */
60
61 div = (parent_rate / rate) / 2;
62
63 if (div < 1)
64 div = 1;
65 else if (div > 16)
66 div = 16;
67
68 return parent_rate / (div * 2);
69 }
70
s3c2440_camif_upll_setrate(struct clk * clk,unsigned long rate)71 static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
72 {
73 unsigned long parent_rate = clk_get_rate(clk->parent);
74 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
75
76 rate = s3c2440_camif_upll_round(clk, rate);
77
78 camdivn &= ~(S3C2440_CAMDIVN_CAMCLK_SEL | S3C2440_CAMDIVN_CAMCLK_MASK);
79
80 if (rate != parent_rate) {
81 camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
82 camdivn |= (((parent_rate / rate) / 2) - 1);
83 }
84
85 __raw_writel(camdivn, S3C2440_CAMDIVN);
86
87 return 0;
88 }
89
s3c2440_camif_upll_getrate(struct clk * clk)90 static unsigned long s3c2440_camif_upll_getrate(struct clk *clk)
91 {
92 unsigned long parent_rate = clk_get_rate(clk->parent);
93 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
94
95 if (!(camdivn & S3C2440_CAMDIVN_CAMCLK_SEL))
96 return parent_rate;
97
98 camdivn &= S3C2440_CAMDIVN_CAMCLK_MASK;
99
100 return parent_rate / (camdivn + 1) / 2;
101 }
102
103 /* Extra S3C2440 clocks */
104
105 static struct clk s3c2440_clk_cam = {
106 .name = "camif",
107 .enable = s3c2410_clkcon_enable,
108 .ctrlbit = S3C2440_CLKCON_CAMERA,
109 };
110
111 static struct clk s3c2440_clk_cam_upll = {
112 .name = "camif-upll",
113 .ops = &(struct clk_ops) {
114 .set_rate = s3c2440_camif_upll_setrate,
115 .get_rate = s3c2440_camif_upll_getrate,
116 .round_rate = s3c2440_camif_upll_round,
117 },
118 };
119
120 static struct clk s3c2440_clk_ac97 = {
121 .name = "ac97",
122 .enable = s3c2410_clkcon_enable,
123 .ctrlbit = S3C2440_CLKCON_AC97,
124 };
125
126 #define S3C24XX_VA_UART0 (S3C_VA_UART)
127 #define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 )
128 #define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 )
129 #define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000 )
130
s3c2440_fclk_n_getrate(struct clk * clk)131 static unsigned long s3c2440_fclk_n_getrate(struct clk *clk)
132 {
133 unsigned long ucon0, ucon1, ucon2, divisor;
134
135 /* the fun of calculating the uart divisors on the s3c2440 */
136 ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
137 ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
138 ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
139
140 ucon0 &= S3C2440_UCON0_DIVMASK;
141 ucon1 &= S3C2440_UCON1_DIVMASK;
142 ucon2 &= S3C2440_UCON2_DIVMASK;
143
144 if (ucon0 != 0)
145 divisor = (ucon0 >> S3C2440_UCON_DIVSHIFT) + 6;
146 else if (ucon1 != 0)
147 divisor = (ucon1 >> S3C2440_UCON_DIVSHIFT) + 21;
148 else if (ucon2 != 0)
149 divisor = (ucon2 >> S3C2440_UCON_DIVSHIFT) + 36;
150 else
151 /* manual calims 44, seems to be 9 */
152 divisor = 9;
153
154 return clk_get_rate(clk->parent) / divisor;
155 }
156
157 static struct clk s3c2440_clk_fclk_n = {
158 .name = "fclk_n",
159 .parent = &clk_f,
160 .ops = &(struct clk_ops) {
161 .get_rate = s3c2440_fclk_n_getrate,
162 },
163 };
164
165 static struct clk_lookup s3c2440_clk_lookup[] = {
166 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
167 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
168 CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),
169 CLKDEV_INIT("s3c2440-camif", "camera", &s3c2440_clk_cam_upll),
170 };
171
s3c2440_clk_add(struct device * dev,struct subsys_interface * sif)172 static int __init_refok s3c2440_clk_add(struct device *dev, struct subsys_interface *sif)
173 {
174 struct clk *clock_upll;
175 struct clk *clock_h;
176 struct clk *clock_p;
177
178 clock_p = clk_get(NULL, "pclk");
179 clock_h = clk_get(NULL, "hclk");
180 clock_upll = clk_get(NULL, "upll");
181
182 if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) {
183 printk(KERN_ERR "S3C2440: Failed to get parent clocks\n");
184 return -EINVAL;
185 }
186
187 s3c2440_clk_cam.parent = clock_h;
188 s3c2440_clk_ac97.parent = clock_p;
189 s3c2440_clk_cam_upll.parent = clock_upll;
190 s3c24xx_register_clock(&s3c2440_clk_fclk_n);
191
192 s3c24xx_register_clock(&s3c2440_clk_ac97);
193 s3c24xx_register_clock(&s3c2440_clk_cam);
194 s3c24xx_register_clock(&s3c2440_clk_cam_upll);
195 clkdev_add_table(s3c2440_clk_lookup, ARRAY_SIZE(s3c2440_clk_lookup));
196
197 clk_disable(&s3c2440_clk_ac97);
198 clk_disable(&s3c2440_clk_cam);
199
200 return 0;
201 }
202
203 static struct subsys_interface s3c2440_clk_interface = {
204 .name = "s3c2440_clk",
205 .subsys = &s3c2440_subsys,
206 .add_dev = s3c2440_clk_add,
207 };
208
s3c24xx_clk_init(void)209 static __init int s3c24xx_clk_init(void)
210 {
211 return subsys_interface_register(&s3c2440_clk_interface);
212 }
213
214 arch_initcall(s3c24xx_clk_init);
215