1 /* linux/arch/arm/mach-s3c2410/pm.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 (and compatible) Power Manager (Suspend-To-RAM) support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23 #include <linux/init.h>
24 #include <linux/suspend.h>
25 #include <linux/errno.h>
26 #include <linux/time.h>
27 #include <linux/device.h>
28 #include <linux/syscore_ops.h>
29 #include <linux/gpio.h>
30 #include <linux/io.h>
31
32 #include <asm/mach-types.h>
33
34 #include <mach/hardware.h>
35 #include <mach/regs-gpio.h>
36
37 #include <plat/cpu.h>
38 #include <plat/pm.h>
39
40 #include "h1940.h"
41
s3c2410_pm_prepare(void)42 static void s3c2410_pm_prepare(void)
43 {
44 /* ensure at least GSTATUS3 has the resume address */
45
46 __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3);
47
48 S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
49 S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
50
51 if (machine_is_h1940()) {
52 void *base = phys_to_virt(H1940_SUSPEND_CHECK);
53 unsigned long ptr;
54 unsigned long calc = 0;
55
56 /* generate check for the bootloader to check on resume */
57
58 for (ptr = 0; ptr < 0x40000; ptr += 0x400)
59 calc += __raw_readl(base+ptr);
60
61 __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
62 }
63
64 /* RX3715 and RX1950 use similar to H1940 code and the
65 * same offsets for resume and checksum pointers */
66
67 if (machine_is_rx3715() || machine_is_rx1950()) {
68 void *base = phys_to_virt(H1940_SUSPEND_CHECK);
69 unsigned long ptr;
70 unsigned long calc = 0;
71
72 /* generate check for the bootloader to check on resume */
73
74 for (ptr = 0; ptr < 0x40000; ptr += 0x4)
75 calc += __raw_readl(base+ptr);
76
77 __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
78 }
79
80 if (machine_is_aml_m5900()) {
81 gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_HIGH, NULL);
82 gpio_free(S3C2410_GPF(2));
83 }
84
85 if (machine_is_rx1950()) {
86 /* According to S3C2442 user's manual, page 7-17,
87 * when the system is operating in NAND boot mode,
88 * the hardware pin configuration - EINT[23:21] –
89 * must be set as input for starting up after
90 * wakeup from sleep mode
91 */
92 s3c_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_INPUT);
93 s3c_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPIO_INPUT);
94 s3c_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPIO_INPUT);
95 }
96 }
97
s3c2410_pm_resume(void)98 static void s3c2410_pm_resume(void)
99 {
100 unsigned long tmp;
101
102 /* unset the return-from-sleep flag, to ensure reset */
103
104 tmp = __raw_readl(S3C2410_GSTATUS2);
105 tmp &= S3C2410_GSTATUS2_OFFRESET;
106 __raw_writel(tmp, S3C2410_GSTATUS2);
107
108 if (machine_is_aml_m5900()) {
109 gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_LOW, NULL);
110 gpio_free(S3C2410_GPF(2));
111 }
112 }
113
114 struct syscore_ops s3c2410_pm_syscore_ops = {
115 .resume = s3c2410_pm_resume,
116 };
117
s3c2410_pm_add(struct device * dev,struct subsys_interface * sif)118 static int s3c2410_pm_add(struct device *dev, struct subsys_interface *sif)
119 {
120 pm_cpu_prep = s3c2410_pm_prepare;
121 pm_cpu_sleep = s3c2410_cpu_suspend;
122
123 return 0;
124 }
125
126 #if defined(CONFIG_CPU_S3C2410)
127 static struct subsys_interface s3c2410_pm_interface = {
128 .name = "s3c2410_pm",
129 .subsys = &s3c2410_subsys,
130 .add_dev = s3c2410_pm_add,
131 };
132
133 /* register ourselves */
134
s3c2410_pm_drvinit(void)135 static int __init s3c2410_pm_drvinit(void)
136 {
137 return subsys_interface_register(&s3c2410_pm_interface);
138 }
139
140 arch_initcall(s3c2410_pm_drvinit);
141
142 static struct subsys_interface s3c2410a_pm_interface = {
143 .name = "s3c2410a_pm",
144 .subsys = &s3c2410a_subsys,
145 .add_dev = s3c2410_pm_add,
146 };
147
s3c2410a_pm_drvinit(void)148 static int __init s3c2410a_pm_drvinit(void)
149 {
150 return subsys_interface_register(&s3c2410a_pm_interface);
151 }
152
153 arch_initcall(s3c2410a_pm_drvinit);
154 #endif
155
156 #if defined(CONFIG_CPU_S3C2440)
157 static struct subsys_interface s3c2440_pm_interface = {
158 .name = "s3c2440_pm",
159 .subsys = &s3c2440_subsys,
160 .add_dev = s3c2410_pm_add,
161 };
162
s3c2440_pm_drvinit(void)163 static int __init s3c2440_pm_drvinit(void)
164 {
165 return subsys_interface_register(&s3c2440_pm_interface);
166 }
167
168 arch_initcall(s3c2440_pm_drvinit);
169 #endif
170
171 #if defined(CONFIG_CPU_S3C2442)
172 static struct subsys_interface s3c2442_pm_interface = {
173 .name = "s3c2442_pm",
174 .subsys = &s3c2442_subsys,
175 .add_dev = s3c2410_pm_add,
176 };
177
s3c2442_pm_drvinit(void)178 static int __init s3c2442_pm_drvinit(void)
179 {
180 return subsys_interface_register(&s3c2442_pm_interface);
181 }
182
183 arch_initcall(s3c2442_pm_drvinit);
184 #endif
185