1 /*
2 * linux/arch/arm/mach-sa1100/irq.c
3 *
4 * Copyright (C) 1999-2001 Nicolas Pitre
5 *
6 * Generic IRQ handling for the SA11x0, GPIO 11-27 IRQ demultiplexing.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/irq.h>
17 #include <linux/ioport.h>
18 #include <linux/syscore_ops.h>
19
20 #include <mach/hardware.h>
21 #include <mach/irqs.h>
22 #include <asm/mach/irq.h>
23
24 #include "generic.h"
25
26
27 /*
28 * SA1100 GPIO edge detection for IRQs:
29 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
30 * Use this instead of directly setting GRER/GFER.
31 */
32 static int GPIO_IRQ_rising_edge;
33 static int GPIO_IRQ_falling_edge;
34 static int GPIO_IRQ_mask = (1 << 11) - 1;
35
36 /*
37 * To get the GPIO number from an IRQ number
38 */
39 #define GPIO_11_27_IRQ(i) ((i) - 21)
40 #define GPIO11_27_MASK(irq) (1 << GPIO_11_27_IRQ(irq))
41
sa1100_gpio_type(struct irq_data * d,unsigned int type)42 static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
43 {
44 unsigned int mask;
45
46 if (d->irq <= 10)
47 mask = 1 << d->irq;
48 else
49 mask = GPIO11_27_MASK(d->irq);
50
51 if (type == IRQ_TYPE_PROBE) {
52 if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
53 return 0;
54 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
55 }
56
57 if (type & IRQ_TYPE_EDGE_RISING) {
58 GPIO_IRQ_rising_edge |= mask;
59 } else
60 GPIO_IRQ_rising_edge &= ~mask;
61 if (type & IRQ_TYPE_EDGE_FALLING) {
62 GPIO_IRQ_falling_edge |= mask;
63 } else
64 GPIO_IRQ_falling_edge &= ~mask;
65
66 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
67 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
68
69 return 0;
70 }
71
72 /*
73 * GPIO IRQs must be acknowledged. This is for IRQs from 0 to 10.
74 */
sa1100_low_gpio_ack(struct irq_data * d)75 static void sa1100_low_gpio_ack(struct irq_data *d)
76 {
77 GEDR = (1 << d->irq);
78 }
79
sa1100_low_gpio_mask(struct irq_data * d)80 static void sa1100_low_gpio_mask(struct irq_data *d)
81 {
82 ICMR &= ~(1 << d->irq);
83 }
84
sa1100_low_gpio_unmask(struct irq_data * d)85 static void sa1100_low_gpio_unmask(struct irq_data *d)
86 {
87 ICMR |= 1 << d->irq;
88 }
89
sa1100_low_gpio_wake(struct irq_data * d,unsigned int on)90 static int sa1100_low_gpio_wake(struct irq_data *d, unsigned int on)
91 {
92 if (on)
93 PWER |= 1 << d->irq;
94 else
95 PWER &= ~(1 << d->irq);
96 return 0;
97 }
98
99 static struct irq_chip sa1100_low_gpio_chip = {
100 .name = "GPIO-l",
101 .irq_ack = sa1100_low_gpio_ack,
102 .irq_mask = sa1100_low_gpio_mask,
103 .irq_unmask = sa1100_low_gpio_unmask,
104 .irq_set_type = sa1100_gpio_type,
105 .irq_set_wake = sa1100_low_gpio_wake,
106 };
107
108 /*
109 * IRQ11 (GPIO11 through 27) handler. We enter here with the
110 * irq_controller_lock held, and IRQs disabled. Decode the IRQ
111 * and call the handler.
112 */
113 static void
sa1100_high_gpio_handler(unsigned int irq,struct irq_desc * desc)114 sa1100_high_gpio_handler(unsigned int irq, struct irq_desc *desc)
115 {
116 unsigned int mask;
117
118 mask = GEDR & 0xfffff800;
119 do {
120 /*
121 * clear down all currently active IRQ sources.
122 * We will be processing them all.
123 */
124 GEDR = mask;
125
126 irq = IRQ_GPIO11;
127 mask >>= 11;
128 do {
129 if (mask & 1)
130 generic_handle_irq(irq);
131 mask >>= 1;
132 irq++;
133 } while (mask);
134
135 mask = GEDR & 0xfffff800;
136 } while (mask);
137 }
138
139 /*
140 * Like GPIO0 to 10, GPIO11-27 IRQs need to be handled specially.
141 * In addition, the IRQs are all collected up into one bit in the
142 * interrupt controller registers.
143 */
sa1100_high_gpio_ack(struct irq_data * d)144 static void sa1100_high_gpio_ack(struct irq_data *d)
145 {
146 unsigned int mask = GPIO11_27_MASK(d->irq);
147
148 GEDR = mask;
149 }
150
sa1100_high_gpio_mask(struct irq_data * d)151 static void sa1100_high_gpio_mask(struct irq_data *d)
152 {
153 unsigned int mask = GPIO11_27_MASK(d->irq);
154
155 GPIO_IRQ_mask &= ~mask;
156
157 GRER &= ~mask;
158 GFER &= ~mask;
159 }
160
sa1100_high_gpio_unmask(struct irq_data * d)161 static void sa1100_high_gpio_unmask(struct irq_data *d)
162 {
163 unsigned int mask = GPIO11_27_MASK(d->irq);
164
165 GPIO_IRQ_mask |= mask;
166
167 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
168 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
169 }
170
sa1100_high_gpio_wake(struct irq_data * d,unsigned int on)171 static int sa1100_high_gpio_wake(struct irq_data *d, unsigned int on)
172 {
173 if (on)
174 PWER |= GPIO11_27_MASK(d->irq);
175 else
176 PWER &= ~GPIO11_27_MASK(d->irq);
177 return 0;
178 }
179
180 static struct irq_chip sa1100_high_gpio_chip = {
181 .name = "GPIO-h",
182 .irq_ack = sa1100_high_gpio_ack,
183 .irq_mask = sa1100_high_gpio_mask,
184 .irq_unmask = sa1100_high_gpio_unmask,
185 .irq_set_type = sa1100_gpio_type,
186 .irq_set_wake = sa1100_high_gpio_wake,
187 };
188
189 /*
190 * We don't need to ACK IRQs on the SA1100 unless they're GPIOs
191 * this is for internal IRQs i.e. from 11 to 31.
192 */
sa1100_mask_irq(struct irq_data * d)193 static void sa1100_mask_irq(struct irq_data *d)
194 {
195 ICMR &= ~(1 << d->irq);
196 }
197
sa1100_unmask_irq(struct irq_data * d)198 static void sa1100_unmask_irq(struct irq_data *d)
199 {
200 ICMR |= (1 << d->irq);
201 }
202
203 /*
204 * Apart form GPIOs, only the RTC alarm can be a wakeup event.
205 */
sa1100_set_wake(struct irq_data * d,unsigned int on)206 static int sa1100_set_wake(struct irq_data *d, unsigned int on)
207 {
208 if (d->irq == IRQ_RTCAlrm) {
209 if (on)
210 PWER |= PWER_RTC;
211 else
212 PWER &= ~PWER_RTC;
213 return 0;
214 }
215 return -EINVAL;
216 }
217
218 static struct irq_chip sa1100_normal_chip = {
219 .name = "SC",
220 .irq_ack = sa1100_mask_irq,
221 .irq_mask = sa1100_mask_irq,
222 .irq_unmask = sa1100_unmask_irq,
223 .irq_set_wake = sa1100_set_wake,
224 };
225
226 static struct resource irq_resource =
227 DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
228
229 static struct sa1100irq_state {
230 unsigned int saved;
231 unsigned int icmr;
232 unsigned int iclr;
233 unsigned int iccr;
234 } sa1100irq_state;
235
sa1100irq_suspend(void)236 static int sa1100irq_suspend(void)
237 {
238 struct sa1100irq_state *st = &sa1100irq_state;
239
240 st->saved = 1;
241 st->icmr = ICMR;
242 st->iclr = ICLR;
243 st->iccr = ICCR;
244
245 /*
246 * Disable all GPIO-based interrupts.
247 */
248 ICMR &= ~(IC_GPIO11_27|IC_GPIO10|IC_GPIO9|IC_GPIO8|IC_GPIO7|
249 IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2|
250 IC_GPIO1|IC_GPIO0);
251
252 /*
253 * Set the appropriate edges for wakeup.
254 */
255 GRER = PWER & GPIO_IRQ_rising_edge;
256 GFER = PWER & GPIO_IRQ_falling_edge;
257
258 /*
259 * Clear any pending GPIO interrupts.
260 */
261 GEDR = GEDR;
262
263 return 0;
264 }
265
sa1100irq_resume(void)266 static void sa1100irq_resume(void)
267 {
268 struct sa1100irq_state *st = &sa1100irq_state;
269
270 if (st->saved) {
271 ICCR = st->iccr;
272 ICLR = st->iclr;
273
274 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
275 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
276
277 ICMR = st->icmr;
278 }
279 }
280
281 static struct syscore_ops sa1100irq_syscore_ops = {
282 .suspend = sa1100irq_suspend,
283 .resume = sa1100irq_resume,
284 };
285
sa1100irq_init_devicefs(void)286 static int __init sa1100irq_init_devicefs(void)
287 {
288 register_syscore_ops(&sa1100irq_syscore_ops);
289 return 0;
290 }
291
292 device_initcall(sa1100irq_init_devicefs);
293
sa1100_init_irq(void)294 void __init sa1100_init_irq(void)
295 {
296 unsigned int irq;
297
298 request_resource(&iomem_resource, &irq_resource);
299
300 /* disable all IRQs */
301 ICMR = 0;
302
303 /* all IRQs are IRQ, not FIQ */
304 ICLR = 0;
305
306 /* clear all GPIO edge detects */
307 GFER = 0;
308 GRER = 0;
309 GEDR = -1;
310
311 /*
312 * Whatever the doc says, this has to be set for the wait-on-irq
313 * instruction to work... on a SA1100 rev 9 at least.
314 */
315 ICCR = 1;
316
317 for (irq = 0; irq <= 10; irq++) {
318 irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip,
319 handle_edge_irq);
320 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
321 }
322
323 for (irq = 12; irq <= 31; irq++) {
324 irq_set_chip_and_handler(irq, &sa1100_normal_chip,
325 handle_level_irq);
326 set_irq_flags(irq, IRQF_VALID);
327 }
328
329 for (irq = 32; irq <= 48; irq++) {
330 irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip,
331 handle_edge_irq);
332 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
333 }
334
335 /*
336 * Install handler for GPIO 11-27 edge detect interrupts
337 */
338 irq_set_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
339 irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
340
341 sa1100_init_gpio();
342 }
343