1/* 2 * sh7372 lowlevel sleep code for "Core Standby Mode" 3 * 4 * Copyright (C) 2011 Magnus Damm 5 * 6 * In "Core Standby Mode" the ARM core is off, but L2 cache is still on 7 * 8 * Based on mach-omap2/sleep34xx.S 9 * 10 * (C) Copyright 2007 Texas Instruments 11 * Karthik Dasu <karthik-dp@ti.com> 12 * 13 * (C) Copyright 2004 Texas Instruments, <www.ti.com> 14 * Richard Woodruff <r-woodruff2@ti.com> 15 * 16 * This program is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation; either version 2 of 19 * the License, or (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 29 * MA 02111-1307 USA 30 */ 31 32#include <linux/linkage.h> 33#include <linux/init.h> 34#include <asm/memory.h> 35#include <asm/assembler.h> 36 37#if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE) 38 .align 12 39 .text 40 .global sh7372_resume_core_standby_sysc 41sh7372_resume_core_standby_sysc: 42 ldr pc, 1f 431: .long cpu_resume - PAGE_OFFSET + PLAT_PHYS_OFFSET 44 45#define SPDCR 0xe6180008 46 47 /* A3SM & A4S power down */ 48 .global sh7372_do_idle_sysc 49sh7372_do_idle_sysc: 50 mov r8, r0 /* sleep mode passed in r0 */ 51 52 /* 53 * Clear the SCTLR.C bit to prevent further data cache 54 * allocation. Clearing SCTLR.C would make all the data accesses 55 * strongly ordered and would not hit the cache. 56 */ 57 mrc p15, 0, r0, c1, c0, 0 58 bic r0, r0, #(1 << 2) @ Disable the C bit 59 mcr p15, 0, r0, c1, c0, 0 60 isb 61 62 /* 63 * Clean and invalidate data cache again. 64 */ 65 ldr r1, kernel_flush 66 blx r1 67 68 /* disable L2 cache in the aux control register */ 69 mrc p15, 0, r10, c1, c0, 1 70 bic r10, r10, #2 71 mcr p15, 0, r10, c1, c0, 1 72 isb 73 74 /* 75 * The kernel doesn't interwork: v7_flush_dcache_all in particluar will 76 * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled. 77 * This sequence switches back to ARM. Note that .align may insert a 78 * nop: bx pc needs to be word-aligned in order to work. 79 */ 80 THUMB( .thumb ) 81 THUMB( .align ) 82 THUMB( bx pc ) 83 THUMB( nop ) 84 .arm 85 86 /* Data memory barrier and Data sync barrier */ 87 dsb 88 dmb 89 90 /* SYSC power down */ 91 ldr r0, =SPDCR 92 str r8, [r0] 931: 94 b 1b 95 96kernel_flush: 97 .word v7_flush_dcache_all 98#endif 99