1 /* 2 * Copyright 2004-2009 Analog Devices Inc. 3 * Tony Kou (tonyko@lineo.ca) 4 * 5 * Licensed under the GPL-2 or later 6 */ 7 8 #ifndef _BLACKFIN_BARRIER_H 9 #define _BLACKFIN_BARRIER_H 10 11 #include <asm/cache.h> 12 13 #define nop() __asm__ __volatile__ ("nop;\n\t" : : ) 14 15 /* 16 * Force strict CPU ordering. 17 */ 18 #ifdef CONFIG_SMP 19 20 #ifdef __ARCH_SYNC_CORE_DCACHE 21 /* Force Core data cache coherence */ 22 # define mb() do { barrier(); smp_check_barrier(); smp_mark_barrier(); } while (0) 23 # define rmb() do { barrier(); smp_check_barrier(); } while (0) 24 # define wmb() do { barrier(); smp_mark_barrier(); } while (0) 25 # define read_barrier_depends() do { barrier(); smp_check_barrier(); } while (0) 26 #else 27 # define mb() barrier() 28 # define rmb() barrier() 29 # define wmb() barrier() 30 # define read_barrier_depends() do { } while (0) 31 #endif 32 33 #else /* !CONFIG_SMP */ 34 35 #define mb() barrier() 36 #define rmb() barrier() 37 #define wmb() barrier() 38 #define read_barrier_depends() do { } while (0) 39 40 #endif /* !CONFIG_SMP */ 41 42 #define smp_mb() mb() 43 #define smp_rmb() rmb() 44 #define smp_wmb() wmb() 45 #define set_mb(var, value) do { var = value; mb(); } while (0) 46 #define smp_read_barrier_depends() read_barrier_depends() 47 48 #endif /* _BLACKFIN_BARRIER_H */ 49