1 /*
2 * Copyright 2004-2009 Analog Devices Inc.
3 * 2005 National ICT Australia (NICTA)
4 * Aidan Williams <aidan@nicta.com.au>
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9 #include <linux/device.h>
10 #include <linux/export.h>
11 #include <linux/platform_device.h>
12 #include <linux/mtd/mtd.h>
13 #include <linux/mtd/partitions.h>
14 #include <linux/mtd/physmap.h>
15 #include <linux/spi/spi.h>
16 #include <linux/spi/flash.h>
17
18 #include <linux/i2c.h>
19 #include <linux/irq.h>
20 #include <linux/interrupt.h>
21 #include <linux/usb/musb.h>
22 #include <asm/dma.h>
23 #include <asm/bfin5xx_spi.h>
24 #include <asm/reboot.h>
25 #include <asm/nand.h>
26 #include <asm/portmux.h>
27 #include <asm/dpmc.h>
28 #include <linux/spi/ad7877.h>
29
30 /*
31 * Name the Board for the /proc/cpuinfo
32 */
33 const char bfin_board_name[] = "ADI BF526-EZBRD";
34
35 /*
36 * Driver needs to know address, irq and flag pin.
37 */
38
39 #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
40 static struct resource musb_resources[] = {
41 [0] = {
42 .start = 0xffc03800,
43 .end = 0xffc03cff,
44 .flags = IORESOURCE_MEM,
45 },
46 [1] = { /* general IRQ */
47 .start = IRQ_USB_INT0,
48 .end = IRQ_USB_INT0,
49 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
50 .name = "mc"
51 },
52 [2] = { /* DMA IRQ */
53 .start = IRQ_USB_DMA,
54 .end = IRQ_USB_DMA,
55 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
56 .name = "dma"
57 },
58 };
59
60 static struct musb_hdrc_config musb_config = {
61 .multipoint = 0,
62 .dyn_fifo = 0,
63 .soft_con = 1,
64 .dma = 1,
65 .num_eps = 8,
66 .dma_channels = 8,
67 .gpio_vrsel = GPIO_PG13,
68 /* Some custom boards need to be active low, just set it to "0"
69 * if it is the case.
70 */
71 .gpio_vrsel_active = 1,
72 .clkin = 24, /* musb CLKIN in MHZ */
73 };
74
75 static struct musb_hdrc_platform_data musb_plat = {
76 #if defined(CONFIG_USB_MUSB_OTG)
77 .mode = MUSB_OTG,
78 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
79 .mode = MUSB_HOST,
80 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
81 .mode = MUSB_PERIPHERAL,
82 #endif
83 .config = &musb_config,
84 };
85
86 static u64 musb_dmamask = ~(u32)0;
87
88 static struct platform_device musb_device = {
89 .name = "musb-blackfin",
90 .id = 0,
91 .dev = {
92 .dma_mask = &musb_dmamask,
93 .coherent_dma_mask = 0xffffffff,
94 .platform_data = &musb_plat,
95 },
96 .num_resources = ARRAY_SIZE(musb_resources),
97 .resource = musb_resources,
98 };
99 #endif
100
101 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
102 static struct mtd_partition ezbrd_partitions[] = {
103 {
104 .name = "bootloader(nor)",
105 .size = 0x40000,
106 .offset = 0,
107 }, {
108 .name = "linux kernel(nor)",
109 .size = 0x1C0000,
110 .offset = MTDPART_OFS_APPEND,
111 }, {
112 .name = "file system(nor)",
113 .size = MTDPART_SIZ_FULL,
114 .offset = MTDPART_OFS_APPEND,
115 }
116 };
117
118 static struct physmap_flash_data ezbrd_flash_data = {
119 .width = 2,
120 .parts = ezbrd_partitions,
121 .nr_parts = ARRAY_SIZE(ezbrd_partitions),
122 };
123
124 static struct resource ezbrd_flash_resource = {
125 .start = 0x20000000,
126 .end = 0x203fffff,
127 .flags = IORESOURCE_MEM,
128 };
129
130 static struct platform_device ezbrd_flash_device = {
131 .name = "physmap-flash",
132 .id = 0,
133 .dev = {
134 .platform_data = &ezbrd_flash_data,
135 },
136 .num_resources = 1,
137 .resource = &ezbrd_flash_resource,
138 };
139 #endif
140
141 #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
142 static struct mtd_partition partition_info[] = {
143 {
144 .name = "bootloader(nand)",
145 .offset = 0,
146 .size = 0x40000,
147 }, {
148 .name = "linux kernel(nand)",
149 .offset = MTDPART_OFS_APPEND,
150 .size = 4 * 1024 * 1024,
151 },
152 {
153 .name = "file system(nand)",
154 .offset = MTDPART_OFS_APPEND,
155 .size = MTDPART_SIZ_FULL,
156 },
157 };
158
159 static struct bf5xx_nand_platform bf5xx_nand_platform = {
160 .data_width = NFC_NWIDTH_8,
161 .partitions = partition_info,
162 .nr_partitions = ARRAY_SIZE(partition_info),
163 .rd_dly = 3,
164 .wr_dly = 3,
165 };
166
167 static struct resource bf5xx_nand_resources[] = {
168 {
169 .start = NFC_CTL,
170 .end = NFC_DATA_RD + 2,
171 .flags = IORESOURCE_MEM,
172 },
173 {
174 .start = CH_NFC,
175 .end = CH_NFC,
176 .flags = IORESOURCE_IRQ,
177 },
178 };
179
180 static struct platform_device bf5xx_nand_device = {
181 .name = "bf5xx-nand",
182 .id = 0,
183 .num_resources = ARRAY_SIZE(bf5xx_nand_resources),
184 .resource = bf5xx_nand_resources,
185 .dev = {
186 .platform_data = &bf5xx_nand_platform,
187 },
188 };
189 #endif
190
191 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
192 static struct platform_device rtc_device = {
193 .name = "rtc-bfin",
194 .id = -1,
195 };
196 #endif
197
198
199 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
200 #include <linux/bfin_mac.h>
201 static const unsigned short bfin_mac_peripherals[] = P_RMII0;
202
203 static struct bfin_phydev_platform_data bfin_phydev_data[] = {
204 {
205 .addr = 1,
206 .irq = IRQ_MAC_PHYINT,
207 },
208 };
209
210 static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
211 .phydev_number = 1,
212 .phydev_data = bfin_phydev_data,
213 .phy_mode = PHY_INTERFACE_MODE_RMII,
214 .mac_peripherals = bfin_mac_peripherals,
215 };
216
217 static struct platform_device bfin_mii_bus = {
218 .name = "bfin_mii_bus",
219 .dev = {
220 .platform_data = &bfin_mii_bus_data,
221 }
222 };
223
224 static struct platform_device bfin_mac_device = {
225 .name = "bfin_mac",
226 .dev = {
227 .platform_data = &bfin_mii_bus,
228 }
229 };
230 #endif
231
232 #if defined(CONFIG_MTD_M25P80) \
233 || defined(CONFIG_MTD_M25P80_MODULE)
234 static struct mtd_partition bfin_spi_flash_partitions[] = {
235 {
236 .name = "bootloader(spi)",
237 .size = 0x00040000,
238 .offset = 0,
239 .mask_flags = MTD_CAP_ROM
240 }, {
241 .name = "linux kernel(spi)",
242 .size = MTDPART_SIZ_FULL,
243 .offset = MTDPART_OFS_APPEND,
244 }
245 };
246
247 static struct flash_platform_data bfin_spi_flash_data = {
248 .name = "m25p80",
249 .parts = bfin_spi_flash_partitions,
250 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
251 .type = "sst25wf040",
252 };
253
254 /* SPI flash chip (sst25wf040) */
255 static struct bfin5xx_spi_chip spi_flash_chip_info = {
256 .enable_dma = 0, /* use dma transfer with this chip*/
257 };
258 #endif
259
260 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
261 static struct bfin5xx_spi_chip mmc_spi_chip_info = {
262 .enable_dma = 0,
263 };
264 #endif
265
266 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
267 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
268 .model = 7877,
269 .vref_delay_usecs = 50, /* internal, no capacitor */
270 .x_plate_ohms = 419,
271 .y_plate_ohms = 486,
272 .pressure_max = 1000,
273 .pressure_min = 0,
274 .stopacq_polarity = 1,
275 .first_conversion_delay = 3,
276 .acquisition_time = 1,
277 .averaging = 1,
278 .pen_down_acc_interval = 1,
279 };
280 #endif
281
282 #if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
283 #include <linux/spi/ad7879.h>
284 static const struct ad7879_platform_data bfin_ad7879_ts_info = {
285 .model = 7879, /* Model = AD7879 */
286 .x_plate_ohms = 620, /* 620 Ohm from the touch datasheet */
287 .pressure_max = 10000,
288 .pressure_min = 0,
289 .first_conversion_delay = 3, /* wait 512us before do a first conversion */
290 .acquisition_time = 1, /* 4us acquisition time per sample */
291 .median = 2, /* do 8 measurements */
292 .averaging = 1, /* take the average of 4 middle samples */
293 .pen_down_acc_interval = 255, /* 9.4 ms */
294 .gpio_export = 1, /* Export GPIO to gpiolib */
295 .gpio_base = -1, /* Dynamic allocation */
296 };
297 #endif
298
299 static struct spi_board_info bfin_spi_board_info[] __initdata = {
300 #if defined(CONFIG_MTD_M25P80) \
301 || defined(CONFIG_MTD_M25P80_MODULE)
302 {
303 /* the modalias must be the same as spi device driver name */
304 .modalias = "m25p80", /* Name of spi_driver for this device */
305 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
306 .bus_num = 0, /* Framework bus number */
307 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
308 .platform_data = &bfin_spi_flash_data,
309 .controller_data = &spi_flash_chip_info,
310 .mode = SPI_MODE_3,
311 },
312 #endif
313
314 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
315 {
316 .modalias = "mmc_spi",
317 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
318 .bus_num = 0,
319 .chip_select = 5,
320 .controller_data = &mmc_spi_chip_info,
321 .mode = SPI_MODE_3,
322 },
323 #endif
324 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
325 {
326 .modalias = "ad7877",
327 .platform_data = &bfin_ad7877_ts_info,
328 .irq = IRQ_PF8,
329 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
330 .bus_num = 0,
331 .chip_select = 2,
332 },
333 #endif
334 #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
335 {
336 .modalias = "ad7879",
337 .platform_data = &bfin_ad7879_ts_info,
338 .irq = IRQ_PG0,
339 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
340 .bus_num = 0,
341 .chip_select = 5,
342 .mode = SPI_CPHA | SPI_CPOL,
343 },
344 #endif
345 #if defined(CONFIG_SND_SOC_WM8731) || defined(CONFIG_SND_SOC_WM8731_MODULE) \
346 && defined(CONFIG_SND_SOC_WM8731_SPI)
347 {
348 .modalias = "wm8731",
349 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
350 .bus_num = 0,
351 .chip_select = 5,
352 .mode = SPI_MODE_0,
353 },
354 #endif
355 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
356 {
357 .modalias = "spidev",
358 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
359 .bus_num = 0,
360 .chip_select = 1,
361 },
362 #endif
363 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
364 {
365 .modalias = "bfin-lq035q1-spi",
366 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
367 .bus_num = 0,
368 .chip_select = 1,
369 .mode = SPI_CPHA | SPI_CPOL,
370 },
371 #endif
372 };
373
374 #if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
375 /* SPI controller data */
376 static struct bfin5xx_spi_master bfin_spi0_info = {
377 .num_chipselect = 8,
378 .enable_dma = 1, /* master has the ability to do dma transfer */
379 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
380 };
381
382 /* SPI (0) */
383 static struct resource bfin_spi0_resource[] = {
384 [0] = {
385 .start = SPI0_REGBASE,
386 .end = SPI0_REGBASE + 0xFF,
387 .flags = IORESOURCE_MEM,
388 },
389 [1] = {
390 .start = CH_SPI,
391 .end = CH_SPI,
392 .flags = IORESOURCE_DMA,
393 },
394 [2] = {
395 .start = IRQ_SPI,
396 .end = IRQ_SPI,
397 .flags = IORESOURCE_IRQ,
398 },
399 };
400
401 static struct platform_device bfin_spi0_device = {
402 .name = "bfin-spi",
403 .id = 0, /* Bus number */
404 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
405 .resource = bfin_spi0_resource,
406 .dev = {
407 .platform_data = &bfin_spi0_info, /* Passed to driver */
408 },
409 };
410 #endif /* spi master and devices */
411
412 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
413 #ifdef CONFIG_SERIAL_BFIN_UART0
414 static struct resource bfin_uart0_resources[] = {
415 {
416 .start = UART0_THR,
417 .end = UART0_GCTL+2,
418 .flags = IORESOURCE_MEM,
419 },
420 {
421 .start = IRQ_UART0_TX,
422 .end = IRQ_UART0_TX,
423 .flags = IORESOURCE_IRQ,
424 },
425 {
426 .start = IRQ_UART0_RX,
427 .end = IRQ_UART0_RX,
428 .flags = IORESOURCE_IRQ,
429 },
430 {
431 .start = IRQ_UART0_ERROR,
432 .end = IRQ_UART0_ERROR,
433 .flags = IORESOURCE_IRQ,
434 },
435 {
436 .start = CH_UART0_TX,
437 .end = CH_UART0_TX,
438 .flags = IORESOURCE_DMA,
439 },
440 {
441 .start = CH_UART0_RX,
442 .end = CH_UART0_RX,
443 .flags = IORESOURCE_DMA,
444 },
445 };
446
447 static unsigned short bfin_uart0_peripherals[] = {
448 P_UART0_TX, P_UART0_RX, 0
449 };
450
451 static struct platform_device bfin_uart0_device = {
452 .name = "bfin-uart",
453 .id = 0,
454 .num_resources = ARRAY_SIZE(bfin_uart0_resources),
455 .resource = bfin_uart0_resources,
456 .dev = {
457 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
458 },
459 };
460 #endif
461 #ifdef CONFIG_SERIAL_BFIN_UART1
462 static struct resource bfin_uart1_resources[] = {
463 {
464 .start = UART1_THR,
465 .end = UART1_GCTL+2,
466 .flags = IORESOURCE_MEM,
467 },
468 {
469 .start = IRQ_UART1_TX,
470 .end = IRQ_UART1_TX,
471 .flags = IORESOURCE_IRQ,
472 },
473 {
474 .start = IRQ_UART1_RX,
475 .end = IRQ_UART1_RX,
476 .flags = IORESOURCE_IRQ,
477 },
478 {
479 .start = IRQ_UART1_ERROR,
480 .end = IRQ_UART1_ERROR,
481 .flags = IORESOURCE_IRQ,
482 },
483 {
484 .start = CH_UART1_TX,
485 .end = CH_UART1_TX,
486 .flags = IORESOURCE_DMA,
487 },
488 {
489 .start = CH_UART1_RX,
490 .end = CH_UART1_RX,
491 .flags = IORESOURCE_DMA,
492 },
493 #ifdef CONFIG_BFIN_UART1_CTSRTS
494 { /* CTS pin */
495 .start = GPIO_PG0,
496 .end = GPIO_PG0,
497 .flags = IORESOURCE_IO,
498 },
499 { /* RTS pin */
500 .start = GPIO_PF10,
501 .end = GPIO_PF10,
502 .flags = IORESOURCE_IO,
503 },
504 #endif
505 };
506
507 static unsigned short bfin_uart1_peripherals[] = {
508 P_UART1_TX, P_UART1_RX, 0
509 };
510
511 static struct platform_device bfin_uart1_device = {
512 .name = "bfin-uart",
513 .id = 1,
514 .num_resources = ARRAY_SIZE(bfin_uart1_resources),
515 .resource = bfin_uart1_resources,
516 .dev = {
517 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
518 },
519 };
520 #endif
521 #endif
522
523 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
524 #ifdef CONFIG_BFIN_SIR0
525 static struct resource bfin_sir0_resources[] = {
526 {
527 .start = 0xFFC00400,
528 .end = 0xFFC004FF,
529 .flags = IORESOURCE_MEM,
530 },
531 {
532 .start = IRQ_UART0_RX,
533 .end = IRQ_UART0_RX+1,
534 .flags = IORESOURCE_IRQ,
535 },
536 {
537 .start = CH_UART0_RX,
538 .end = CH_UART0_RX+1,
539 .flags = IORESOURCE_DMA,
540 },
541 };
542
543 static struct platform_device bfin_sir0_device = {
544 .name = "bfin_sir",
545 .id = 0,
546 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
547 .resource = bfin_sir0_resources,
548 };
549 #endif
550 #ifdef CONFIG_BFIN_SIR1
551 static struct resource bfin_sir1_resources[] = {
552 {
553 .start = 0xFFC02000,
554 .end = 0xFFC020FF,
555 .flags = IORESOURCE_MEM,
556 },
557 {
558 .start = IRQ_UART1_RX,
559 .end = IRQ_UART1_RX+1,
560 .flags = IORESOURCE_IRQ,
561 },
562 {
563 .start = CH_UART1_RX,
564 .end = CH_UART1_RX+1,
565 .flags = IORESOURCE_DMA,
566 },
567 };
568
569 static struct platform_device bfin_sir1_device = {
570 .name = "bfin_sir",
571 .id = 1,
572 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
573 .resource = bfin_sir1_resources,
574 };
575 #endif
576 #endif
577
578 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
579 static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
580
581 static struct resource bfin_twi0_resource[] = {
582 [0] = {
583 .start = TWI0_REGBASE,
584 .end = TWI0_REGBASE,
585 .flags = IORESOURCE_MEM,
586 },
587 [1] = {
588 .start = IRQ_TWI,
589 .end = IRQ_TWI,
590 .flags = IORESOURCE_IRQ,
591 },
592 };
593
594 static struct platform_device i2c_bfin_twi_device = {
595 .name = "i2c-bfin-twi",
596 .id = 0,
597 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
598 .resource = bfin_twi0_resource,
599 .dev = {
600 .platform_data = &bfin_twi0_pins,
601 },
602 };
603 #endif
604
605 static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
606 #if defined(CONFIG_BFIN_TWI_LCD) || defined(CONFIG_BFIN_TWI_LCD_MODULE)
607 {
608 I2C_BOARD_INFO("pcf8574_lcd", 0x22),
609 },
610 #endif
611 #if defined(CONFIG_INPUT_PCF8574) || defined(CONFIG_INPUT_PCF8574_MODULE)
612 {
613 I2C_BOARD_INFO("pcf8574_keypad", 0x27),
614 .irq = IRQ_PF8,
615 },
616 #endif
617 };
618
619 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
620 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
621 static struct resource bfin_sport0_uart_resources[] = {
622 {
623 .start = SPORT0_TCR1,
624 .end = SPORT0_MRCS3+4,
625 .flags = IORESOURCE_MEM,
626 },
627 {
628 .start = IRQ_SPORT0_RX,
629 .end = IRQ_SPORT0_RX+1,
630 .flags = IORESOURCE_IRQ,
631 },
632 {
633 .start = IRQ_SPORT0_ERROR,
634 .end = IRQ_SPORT0_ERROR,
635 .flags = IORESOURCE_IRQ,
636 },
637 };
638
639 static unsigned short bfin_sport0_peripherals[] = {
640 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
641 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
642 };
643
644 static struct platform_device bfin_sport0_uart_device = {
645 .name = "bfin-sport-uart",
646 .id = 0,
647 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
648 .resource = bfin_sport0_uart_resources,
649 .dev = {
650 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
651 },
652 };
653 #endif
654 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
655 static struct resource bfin_sport1_uart_resources[] = {
656 {
657 .start = SPORT1_TCR1,
658 .end = SPORT1_MRCS3+4,
659 .flags = IORESOURCE_MEM,
660 },
661 {
662 .start = IRQ_SPORT1_RX,
663 .end = IRQ_SPORT1_RX+1,
664 .flags = IORESOURCE_IRQ,
665 },
666 {
667 .start = IRQ_SPORT1_ERROR,
668 .end = IRQ_SPORT1_ERROR,
669 .flags = IORESOURCE_IRQ,
670 },
671 };
672
673 static unsigned short bfin_sport1_peripherals[] = {
674 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
675 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
676 };
677
678 static struct platform_device bfin_sport1_uart_device = {
679 .name = "bfin-sport-uart",
680 .id = 1,
681 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
682 .resource = bfin_sport1_uart_resources,
683 .dev = {
684 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
685 },
686 };
687 #endif
688 #endif
689
690 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
691 #include <linux/input.h>
692 #include <linux/gpio_keys.h>
693
694 static struct gpio_keys_button bfin_gpio_keys_table[] = {
695 {BTN_0, GPIO_PG0, 1, "gpio-keys: BTN0"},
696 {BTN_1, GPIO_PG13, 1, "gpio-keys: BTN1"},
697 };
698
699 static struct gpio_keys_platform_data bfin_gpio_keys_data = {
700 .buttons = bfin_gpio_keys_table,
701 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table),
702 };
703
704 static struct platform_device bfin_device_gpiokeys = {
705 .name = "gpio-keys",
706 .dev = {
707 .platform_data = &bfin_gpio_keys_data,
708 },
709 };
710 #endif
711
712 static const unsigned int cclk_vlev_datasheet[] =
713 {
714 VRPAIR(VLEV_100, 400000000),
715 VRPAIR(VLEV_105, 426000000),
716 VRPAIR(VLEV_110, 500000000),
717 VRPAIR(VLEV_115, 533000000),
718 VRPAIR(VLEV_120, 600000000),
719 };
720
721 static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
722 .tuple_tab = cclk_vlev_datasheet,
723 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
724 .vr_settling_time = 25 /* us */,
725 };
726
727 static struct platform_device bfin_dpmc = {
728 .name = "bfin dpmc",
729 .dev = {
730 .platform_data = &bfin_dmpc_vreg_data,
731 },
732 };
733
734 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
735 #include <asm/bfin-lq035q1.h>
736
737 static struct bfin_lq035q1fb_disp_info bfin_lq035q1_data = {
738 .mode = LQ035_NORM | LQ035_RGB | LQ035_RL | LQ035_TB,
739 .ppi_mode = USE_RGB565_16_BIT_PPI,
740 .use_bl = 1,
741 .gpio_bl = GPIO_PG12,
742 };
743
744 static struct resource bfin_lq035q1_resources[] = {
745 {
746 .start = IRQ_PPI_ERROR,
747 .end = IRQ_PPI_ERROR,
748 .flags = IORESOURCE_IRQ,
749 },
750 };
751
752 static struct platform_device bfin_lq035q1_device = {
753 .name = "bfin-lq035q1",
754 .id = -1,
755 .num_resources = ARRAY_SIZE(bfin_lq035q1_resources),
756 .resource = bfin_lq035q1_resources,
757 .dev = {
758 .platform_data = &bfin_lq035q1_data,
759 },
760 };
761 #endif
762
763 static struct platform_device *stamp_devices[] __initdata = {
764
765 &bfin_dpmc,
766
767 #if defined(CONFIG_MTD_NAND_BF5XX) || defined(CONFIG_MTD_NAND_BF5XX_MODULE)
768 &bf5xx_nand_device,
769 #endif
770
771 #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
772 &rtc_device,
773 #endif
774
775 #if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
776 &musb_device,
777 #endif
778
779 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
780 &bfin_mii_bus,
781 &bfin_mac_device,
782 #endif
783
784 #if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
785 &bfin_spi0_device,
786 #endif
787
788 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
789 #ifdef CONFIG_SERIAL_BFIN_UART0
790 &bfin_uart0_device,
791 #endif
792 #ifdef CONFIG_SERIAL_BFIN_UART1
793 &bfin_uart1_device,
794 #endif
795 #endif
796
797 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
798 &bfin_lq035q1_device,
799 #endif
800
801 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
802 #ifdef CONFIG_BFIN_SIR0
803 &bfin_sir0_device,
804 #endif
805 #ifdef CONFIG_BFIN_SIR1
806 &bfin_sir1_device,
807 #endif
808 #endif
809
810 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
811 &i2c_bfin_twi_device,
812 #endif
813
814 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
815 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
816 &bfin_sport0_uart_device,
817 #endif
818 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
819 &bfin_sport1_uart_device,
820 #endif
821 #endif
822
823 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
824 &bfin_device_gpiokeys,
825 #endif
826
827 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
828 &ezbrd_flash_device,
829 #endif
830 };
831
ezbrd_init(void)832 static int __init ezbrd_init(void)
833 {
834 printk(KERN_INFO "%s(): registering device resources\n", __func__);
835 i2c_register_board_info(0, bfin_i2c_board_info,
836 ARRAY_SIZE(bfin_i2c_board_info));
837 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
838 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
839 return 0;
840 }
841
842 arch_initcall(ezbrd_init);
843
844 static struct platform_device *ezbrd_early_devices[] __initdata = {
845 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
846 #ifdef CONFIG_SERIAL_BFIN_UART0
847 &bfin_uart0_device,
848 #endif
849 #ifdef CONFIG_SERIAL_BFIN_UART1
850 &bfin_uart1_device,
851 #endif
852 #endif
853
854 #if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
855 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
856 &bfin_sport0_uart_device,
857 #endif
858 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
859 &bfin_sport1_uart_device,
860 #endif
861 #endif
862 };
863
native_machine_early_platform_add_devices(void)864 void __init native_machine_early_platform_add_devices(void)
865 {
866 printk(KERN_INFO "register early platform devices\n");
867 early_platform_add_devices(ezbrd_early_devices,
868 ARRAY_SIZE(ezbrd_early_devices));
869 }
870
native_machine_restart(char * cmd)871 void native_machine_restart(char *cmd)
872 {
873 /* workaround reboot hang when booting from SPI */
874 if ((bfin_read_SYSCR() & 0x7) == 0x3)
875 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
876 }
877
bfin_get_ether_addr(char * addr)878 int bfin_get_ether_addr(char *addr)
879 {
880 /* the MAC is stored in OTP memory page 0xDF */
881 u32 ret;
882 u64 otp_mac;
883 u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
884
885 ret = otp_read(0xDF, 0x00, &otp_mac);
886 if (!(ret & 0x1)) {
887 char *otp_mac_p = (char *)&otp_mac;
888 for (ret = 0; ret < 6; ++ret)
889 addr[ret] = otp_mac_p[5 - ret];
890 }
891 return 0;
892 }
893 EXPORT_SYMBOL(bfin_get_ether_addr);
894