1 /* 2 * Port on Texas Instruments TMS320C6x architecture 3 * 4 * Copyright (C) 2005, 2006, 2009, 2010, 2012 Texas Instruments Incorporated 5 * Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com) 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #ifndef _ASM_C6X_CACHE_H 12 #define _ASM_C6X_CACHE_H 13 14 #include <linux/irqflags.h> 15 16 /* 17 * Cache line size 18 */ 19 #define L1D_CACHE_SHIFT 6 20 #define L1D_CACHE_BYTES (1 << L1D_CACHE_SHIFT) 21 22 #define L1P_CACHE_SHIFT 5 23 #define L1P_CACHE_BYTES (1 << L1P_CACHE_SHIFT) 24 25 #define L2_CACHE_SHIFT 7 26 #define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT) 27 28 /* 29 * L2 used as cache 30 */ 31 #define L2MODE_SIZE L2MODE_256K_CACHE 32 33 /* 34 * For practical reasons the L1_CACHE_BYTES defines should not be smaller than 35 * the L2 line size 36 */ 37 #define L1_CACHE_SHIFT L2_CACHE_SHIFT 38 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 39 40 #define L2_CACHE_ALIGN_LOW(x) \ 41 (((x) & ~(L2_CACHE_BYTES - 1))) 42 #define L2_CACHE_ALIGN_UP(x) \ 43 (((x) + (L2_CACHE_BYTES - 1)) & ~(L2_CACHE_BYTES - 1)) 44 #define L2_CACHE_ALIGN_CNT(x) \ 45 (((x) + (sizeof(int) - 1)) & ~(sizeof(int) - 1)) 46 47 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES 48 #define ARCH_SLAB_MINALIGN L1_CACHE_BYTES 49 50 /* 51 * This is the granularity of hardware cacheability control. 52 */ 53 #define CACHEABILITY_ALIGN 0x01000000 54 55 /* 56 * Align a physical address to MAR regions 57 */ 58 #define CACHE_REGION_START(v) \ 59 (((u32) (v)) & ~(CACHEABILITY_ALIGN - 1)) 60 #define CACHE_REGION_END(v) \ 61 (((u32) (v) + (CACHEABILITY_ALIGN - 1)) & ~(CACHEABILITY_ALIGN - 1)) 62 63 extern void __init c6x_cache_init(void); 64 65 extern void enable_caching(unsigned long start, unsigned long end); 66 extern void disable_caching(unsigned long start, unsigned long end); 67 68 extern void L1_cache_off(void); 69 extern void L1_cache_on(void); 70 71 extern void L1P_cache_global_invalidate(void); 72 extern void L1D_cache_global_invalidate(void); 73 extern void L1D_cache_global_writeback(void); 74 extern void L1D_cache_global_writeback_invalidate(void); 75 extern void L2_cache_set_mode(unsigned int mode); 76 extern void L2_cache_global_writeback_invalidate(void); 77 extern void L2_cache_global_writeback(void); 78 79 extern void L1P_cache_block_invalidate(unsigned int start, unsigned int end); 80 extern void L1D_cache_block_invalidate(unsigned int start, unsigned int end); 81 extern void L1D_cache_block_writeback_invalidate(unsigned int start, 82 unsigned int end); 83 extern void L1D_cache_block_writeback(unsigned int start, unsigned int end); 84 extern void L2_cache_block_invalidate(unsigned int start, unsigned int end); 85 extern void L2_cache_block_writeback(unsigned int start, unsigned int end); 86 extern void L2_cache_block_writeback_invalidate(unsigned int start, 87 unsigned int end); 88 extern void L2_cache_block_invalidate_nowait(unsigned int start, 89 unsigned int end); 90 extern void L2_cache_block_writeback_nowait(unsigned int start, 91 unsigned int end); 92 93 extern void L2_cache_block_writeback_invalidate_nowait(unsigned int start, 94 unsigned int end); 95 96 #endif /* _ASM_C6X_CACHE_H */ 97