1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995 Waldorf GmbH
7 * Copyright (C) 1994 - 2000, 06 Ralf Baechle
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
10 * Author: Maciej W. Rozycki <macro@mips.com>
11 */
12 #ifndef _ASM_IO_H
13 #define _ASM_IO_H
14
15 #include <linux/compiler.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/irqflags.h>
19
20 #include <asm/addrspace.h>
21 #include <asm/bug.h>
22 #include <asm/byteorder.h>
23 #include <asm/cpu.h>
24 #include <asm/cpu-features.h>
25 #include <asm-generic/iomap.h>
26 #include <asm/page.h>
27 #include <asm/pgtable-bits.h>
28 #include <asm/processor.h>
29 #include <asm/string.h>
30
31 #include <ioremap.h>
32 #include <mangle-port.h>
33
34 /*
35 * Slowdown I/O port space accesses for antique hardware.
36 */
37 #undef CONF_SLOWDOWN_IO
38
39 /*
40 * Raw operations are never swapped in software. OTOH values that raw
41 * operations are working on may or may not have been swapped by the bus
42 * hardware. An example use would be for flash memory that's used for
43 * execute in place.
44 */
45 # define __raw_ioswabb(a, x) (x)
46 # define __raw_ioswabw(a, x) (x)
47 # define __raw_ioswabl(a, x) (x)
48 # define __raw_ioswabq(a, x) (x)
49 # define ____raw_ioswabq(a, x) (x)
50
51 /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
52
53 #define IO_SPACE_LIMIT 0xffff
54
55 /*
56 * On MIPS I/O ports are memory mapped, so we access them using normal
57 * load/store instructions. mips_io_port_base is the virtual address to
58 * which all ports are being mapped. For sake of efficiency some code
59 * assumes that this is an address that can be loaded with a single lui
60 * instruction, so the lower 16 bits must be zero. Should be true on
61 * on any sane architecture; generic code does not use this assumption.
62 */
63 extern const unsigned long mips_io_port_base;
64
65 /*
66 * Gcc will generate code to load the value of mips_io_port_base after each
67 * function call which may be fairly wasteful in some cases. So we don't
68 * play quite by the book. We tell gcc mips_io_port_base is a long variable
69 * which solves the code generation issue. Now we need to violate the
70 * aliasing rules a little to make initialization possible and finally we
71 * will need the barrier() to fight side effects of the aliasing chat.
72 * This trickery will eventually collapse under gcc's optimizer. Oh well.
73 */
set_io_port_base(unsigned long base)74 static inline void set_io_port_base(unsigned long base)
75 {
76 * (unsigned long *) &mips_io_port_base = base;
77 barrier();
78 }
79
80 /*
81 * Thanks to James van Artsdalen for a better timing-fix than
82 * the two short jumps: using outb's to a nonexistent port seems
83 * to guarantee better timings even on fast machines.
84 *
85 * On the other hand, I'd like to be sure of a non-existent port:
86 * I feel a bit unsafe about using 0x80 (should be safe, though)
87 *
88 * Linus
89 *
90 */
91
92 #define __SLOW_DOWN_IO \
93 __asm__ __volatile__( \
94 "sb\t$0,0x80(%0)" \
95 : : "r" (mips_io_port_base));
96
97 #ifdef CONF_SLOWDOWN_IO
98 #ifdef REALLY_SLOW_IO
99 #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
100 #else
101 #define SLOW_DOWN_IO __SLOW_DOWN_IO
102 #endif
103 #else
104 #define SLOW_DOWN_IO
105 #endif
106
107 /*
108 * virt_to_phys - map virtual addresses to physical
109 * @address: address to remap
110 *
111 * The returned physical address is the physical (CPU) mapping for
112 * the memory address given. It is only valid to use this function on
113 * addresses directly mapped or allocated via kmalloc.
114 *
115 * This function does not give bus mappings for DMA transfers. In
116 * almost all conceivable cases a device driver should not be using
117 * this function
118 */
virt_to_phys(volatile const void * address)119 static inline unsigned long virt_to_phys(volatile const void *address)
120 {
121 return __pa(address);
122 }
123
124 /*
125 * phys_to_virt - map physical address to virtual
126 * @address: address to remap
127 *
128 * The returned virtual address is a current CPU mapping for
129 * the memory address given. It is only valid to use this function on
130 * addresses that have a kernel mapping
131 *
132 * This function does not handle bus mappings for DMA transfers. In
133 * almost all conceivable cases a device driver should not be using
134 * this function
135 */
phys_to_virt(unsigned long address)136 static inline void * phys_to_virt(unsigned long address)
137 {
138 return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
139 }
140
141 /*
142 * ISA I/O bus memory addresses are 1:1 with the physical address.
143 */
isa_virt_to_bus(volatile void * address)144 static inline unsigned long isa_virt_to_bus(volatile void * address)
145 {
146 return (unsigned long)address - PAGE_OFFSET;
147 }
148
isa_bus_to_virt(unsigned long address)149 static inline void * isa_bus_to_virt(unsigned long address)
150 {
151 return (void *)(address + PAGE_OFFSET);
152 }
153
154 #define isa_page_to_bus page_to_phys
155
156 /*
157 * However PCI ones are not necessarily 1:1 and therefore these interfaces
158 * are forbidden in portable PCI drivers.
159 *
160 * Allow them for x86 for legacy drivers, though.
161 */
162 #define virt_to_bus virt_to_phys
163 #define bus_to_virt phys_to_virt
164
165 #define phys_to_bus(x) ((dma_addr_t)(x))
166 #define bus_to_phys(x) ((phys_t)(x))
167
168 /*
169 * Change "struct page" to physical address.
170 */
171 #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
172
173 extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags);
174 extern void __iounmap(const volatile void __iomem *addr);
175
176 #ifndef CONFIG_PCI
177 struct pci_dev;
pci_iounmap(struct pci_dev * dev,void __iomem * addr)178 static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
179 #endif
180
__ioremap_mode(phys_t offset,unsigned long size,unsigned long flags)181 static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
182 unsigned long flags)
183 {
184 void __iomem *addr = plat_ioremap(offset, size, flags);
185
186 if (addr)
187 return addr;
188
189 #define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))
190
191 if (cpu_has_64bit_addresses) {
192 u64 base = UNCAC_BASE;
193
194 /*
195 * R10000 supports a 2 bit uncached attribute therefore
196 * UNCAC_BASE may not equal IO_BASE.
197 */
198 if (flags == _CACHE_UNCACHED)
199 base = (u64) IO_BASE;
200 return (void __iomem *) (unsigned long) (base + offset);
201 } else if (__builtin_constant_p(offset) &&
202 __builtin_constant_p(size) && __builtin_constant_p(flags)) {
203 phys_t phys_addr, last_addr;
204
205 phys_addr = fixup_bigphys_addr(offset, size);
206
207 /* Don't allow wraparound or zero size. */
208 last_addr = phys_addr + size - 1;
209 if (!size || last_addr < phys_addr)
210 return NULL;
211
212 /*
213 * Map uncached objects in the low 512MB of address
214 * space using KSEG1.
215 */
216 if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
217 flags == _CACHE_UNCACHED)
218 return (void __iomem *)
219 (unsigned long)CKSEG1ADDR(phys_addr);
220 }
221
222 return __ioremap(offset, size, flags);
223
224 #undef __IS_LOW512
225 }
226
227 /*
228 * ioremap - map bus memory into CPU space
229 * @offset: bus address of the memory
230 * @size: size of the resource to map
231 *
232 * ioremap performs a platform specific sequence of operations to
233 * make bus memory CPU accessible via the readb/readw/readl/writeb/
234 * writew/writel functions and the other mmio helpers. The returned
235 * address is not guaranteed to be usable directly as a virtual
236 * address.
237 */
238 #define ioremap(offset, size) \
239 __ioremap_mode((offset), (size), _CACHE_UNCACHED)
240
241 /*
242 * ioremap_nocache - map bus memory into CPU space
243 * @offset: bus address of the memory
244 * @size: size of the resource to map
245 *
246 * ioremap_nocache performs a platform specific sequence of operations to
247 * make bus memory CPU accessible via the readb/readw/readl/writeb/
248 * writew/writel functions and the other mmio helpers. The returned
249 * address is not guaranteed to be usable directly as a virtual
250 * address.
251 *
252 * This version of ioremap ensures that the memory is marked uncachable
253 * on the CPU as well as honouring existing caching rules from things like
254 * the PCI bus. Note that there are other caches and buffers on many
255 * busses. In particular driver authors should read up on PCI writes
256 *
257 * It's useful if some control registers are in such an area and
258 * write combining or read caching is not desirable:
259 */
260 #define ioremap_nocache(offset, size) \
261 __ioremap_mode((offset), (size), _CACHE_UNCACHED)
262
263 /*
264 * ioremap_cachable - map bus memory into CPU space
265 * @offset: bus address of the memory
266 * @size: size of the resource to map
267 *
268 * ioremap_nocache performs a platform specific sequence of operations to
269 * make bus memory CPU accessible via the readb/readw/readl/writeb/
270 * writew/writel functions and the other mmio helpers. The returned
271 * address is not guaranteed to be usable directly as a virtual
272 * address.
273 *
274 * This version of ioremap ensures that the memory is marked cachable by
275 * the CPU. Also enables full write-combining. Useful for some
276 * memory-like regions on I/O busses.
277 */
278 #define ioremap_cachable(offset, size) \
279 __ioremap_mode((offset), (size), _page_cachable_default)
280
281 /*
282 * These two are MIPS specific ioremap variant. ioremap_cacheable_cow
283 * requests a cachable mapping, ioremap_uncached_accelerated requests a
284 * mapping using the uncached accelerated mode which isn't supported on
285 * all processors.
286 */
287 #define ioremap_cacheable_cow(offset, size) \
288 __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
289 #define ioremap_uncached_accelerated(offset, size) \
290 __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
291
iounmap(const volatile void __iomem * addr)292 static inline void iounmap(const volatile void __iomem *addr)
293 {
294 if (plat_iounmap(addr))
295 return;
296
297 #define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
298
299 if (cpu_has_64bit_addresses ||
300 (__builtin_constant_p(addr) && __IS_KSEG1(addr)))
301 return;
302
303 __iounmap(addr);
304
305 #undef __IS_KSEG1
306 }
307
308 #ifdef CONFIG_CPU_CAVIUM_OCTEON
309 #define war_octeon_io_reorder_wmb() wmb()
310 #else
311 #define war_octeon_io_reorder_wmb() do { } while (0)
312 #endif
313
314 #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
315 \
316 static inline void pfx##write##bwlq(type val, \
317 volatile void __iomem *mem) \
318 { \
319 volatile type *__mem; \
320 type __val; \
321 \
322 war_octeon_io_reorder_wmb(); \
323 \
324 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
325 \
326 __val = pfx##ioswab##bwlq(__mem, val); \
327 \
328 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
329 *__mem = __val; \
330 else if (cpu_has_64bits) { \
331 unsigned long __flags; \
332 type __tmp; \
333 \
334 if (irq) \
335 local_irq_save(__flags); \
336 __asm__ __volatile__( \
337 ".set mips3" "\t\t# __writeq""\n\t" \
338 "dsll32 %L0, %L0, 0" "\n\t" \
339 "dsrl32 %L0, %L0, 0" "\n\t" \
340 "dsll32 %M0, %M0, 0" "\n\t" \
341 "or %L0, %L0, %M0" "\n\t" \
342 "sd %L0, %2" "\n\t" \
343 ".set mips0" "\n" \
344 : "=r" (__tmp) \
345 : "0" (__val), "m" (*__mem)); \
346 if (irq) \
347 local_irq_restore(__flags); \
348 } else \
349 BUG(); \
350 } \
351 \
352 static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
353 { \
354 volatile type *__mem; \
355 type __val; \
356 \
357 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
358 \
359 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
360 __val = *__mem; \
361 else if (cpu_has_64bits) { \
362 unsigned long __flags; \
363 \
364 if (irq) \
365 local_irq_save(__flags); \
366 __asm__ __volatile__( \
367 ".set mips3" "\t\t# __readq" "\n\t" \
368 "ld %L0, %1" "\n\t" \
369 "dsra32 %M0, %L0, 0" "\n\t" \
370 "sll %L0, %L0, 0" "\n\t" \
371 ".set mips0" "\n" \
372 : "=r" (__val) \
373 : "m" (*__mem)); \
374 if (irq) \
375 local_irq_restore(__flags); \
376 } else { \
377 __val = 0; \
378 BUG(); \
379 } \
380 \
381 return pfx##ioswab##bwlq(__mem, __val); \
382 }
383
384 #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
385 \
386 static inline void pfx##out##bwlq##p(type val, unsigned long port) \
387 { \
388 volatile type *__addr; \
389 type __val; \
390 \
391 war_octeon_io_reorder_wmb(); \
392 \
393 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
394 \
395 __val = pfx##ioswab##bwlq(__addr, val); \
396 \
397 /* Really, we want this to be atomic */ \
398 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
399 \
400 *__addr = __val; \
401 slow; \
402 } \
403 \
404 static inline type pfx##in##bwlq##p(unsigned long port) \
405 { \
406 volatile type *__addr; \
407 type __val; \
408 \
409 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
410 \
411 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
412 \
413 __val = *__addr; \
414 slow; \
415 \
416 return pfx##ioswab##bwlq(__addr, __val); \
417 }
418
419 #define __BUILD_MEMORY_PFX(bus, bwlq, type) \
420 \
421 __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
422
423 #define BUILDIO_MEM(bwlq, type) \
424 \
425 __BUILD_MEMORY_PFX(__raw_, bwlq, type) \
426 __BUILD_MEMORY_PFX(, bwlq, type) \
427 __BUILD_MEMORY_PFX(__mem_, bwlq, type) \
428
BUILDIO_MEM(b,u8)429 BUILDIO_MEM(b, u8)
430 BUILDIO_MEM(w, u16)
431 BUILDIO_MEM(l, u32)
432 BUILDIO_MEM(q, u64)
433
434 #define __BUILD_IOPORT_PFX(bus, bwlq, type) \
435 __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
436 __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
437
438 #define BUILDIO_IOPORT(bwlq, type) \
439 __BUILD_IOPORT_PFX(, bwlq, type) \
440 __BUILD_IOPORT_PFX(__mem_, bwlq, type)
441
442 BUILDIO_IOPORT(b, u8)
443 BUILDIO_IOPORT(w, u16)
444 BUILDIO_IOPORT(l, u32)
445 #ifdef CONFIG_64BIT
446 BUILDIO_IOPORT(q, u64)
447 #endif
448
449 #define __BUILDIO(bwlq, type) \
450 \
451 __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
452
453 __BUILDIO(q, u64)
454
455 #define readb_relaxed readb
456 #define readw_relaxed readw
457 #define readl_relaxed readl
458 #define readq_relaxed readq
459
460 #define readb_be(addr) \
461 __raw_readb((__force unsigned *)(addr))
462 #define readw_be(addr) \
463 be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
464 #define readl_be(addr) \
465 be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
466 #define readq_be(addr) \
467 be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
468
469 #define writeb_be(val, addr) \
470 __raw_writeb((val), (__force unsigned *)(addr))
471 #define writew_be(val, addr) \
472 __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
473 #define writel_be(val, addr) \
474 __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
475 #define writeq_be(val, addr) \
476 __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
477
478 /*
479 * Some code tests for these symbols
480 */
481 #define readq readq
482 #define writeq writeq
483
484 #define __BUILD_MEMORY_STRING(bwlq, type) \
485 \
486 static inline void writes##bwlq(volatile void __iomem *mem, \
487 const void *addr, unsigned int count) \
488 { \
489 const volatile type *__addr = addr; \
490 \
491 while (count--) { \
492 __mem_write##bwlq(*__addr, mem); \
493 __addr++; \
494 } \
495 } \
496 \
497 static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
498 unsigned int count) \
499 { \
500 volatile type *__addr = addr; \
501 \
502 while (count--) { \
503 *__addr = __mem_read##bwlq(mem); \
504 __addr++; \
505 } \
506 }
507
508 #define __BUILD_IOPORT_STRING(bwlq, type) \
509 \
510 static inline void outs##bwlq(unsigned long port, const void *addr, \
511 unsigned int count) \
512 { \
513 const volatile type *__addr = addr; \
514 \
515 while (count--) { \
516 __mem_out##bwlq(*__addr, port); \
517 __addr++; \
518 } \
519 } \
520 \
521 static inline void ins##bwlq(unsigned long port, void *addr, \
522 unsigned int count) \
523 { \
524 volatile type *__addr = addr; \
525 \
526 while (count--) { \
527 *__addr = __mem_in##bwlq(port); \
528 __addr++; \
529 } \
530 }
531
532 #define BUILDSTRING(bwlq, type) \
533 \
534 __BUILD_MEMORY_STRING(bwlq, type) \
535 __BUILD_IOPORT_STRING(bwlq, type)
536
537 BUILDSTRING(b, u8)
538 BUILDSTRING(w, u16)
539 BUILDSTRING(l, u32)
540 #ifdef CONFIG_64BIT
541 BUILDSTRING(q, u64)
542 #endif
543
544
545 #ifdef CONFIG_CPU_CAVIUM_OCTEON
546 #define mmiowb() wmb()
547 #else
548 /* Depends on MIPS II instruction set */
549 #define mmiowb() asm volatile ("sync" ::: "memory")
550 #endif
551
552 static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
553 {
554 memset((void __force *) addr, val, count);
555 }
memcpy_fromio(void * dst,const volatile void __iomem * src,int count)556 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
557 {
558 memcpy(dst, (void __force *) src, count);
559 }
memcpy_toio(volatile void __iomem * dst,const void * src,int count)560 static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
561 {
562 memcpy((void __force *) dst, src, count);
563 }
564
565 /*
566 * The caches on some architectures aren't dma-coherent and have need to
567 * handle this in software. There are three types of operations that
568 * can be applied to dma buffers.
569 *
570 * - dma_cache_wback_inv(start, size) makes caches and coherent by
571 * writing the content of the caches back to memory, if necessary.
572 * The function also invalidates the affected part of the caches as
573 * necessary before DMA transfers from outside to memory.
574 * - dma_cache_wback(start, size) makes caches and coherent by
575 * writing the content of the caches back to memory, if necessary.
576 * The function also invalidates the affected part of the caches as
577 * necessary before DMA transfers from outside to memory.
578 * - dma_cache_inv(start, size) invalidates the affected parts of the
579 * caches. Dirty lines of the caches may be written back or simply
580 * be discarded. This operation is necessary before dma operations
581 * to the memory.
582 *
583 * This API used to be exported; it now is for arch code internal use only.
584 */
585 #ifdef CONFIG_DMA_NONCOHERENT
586
587 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
588 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
589 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
590
591 #define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start, size)
592 #define dma_cache_wback(start, size) _dma_cache_wback(start, size)
593 #define dma_cache_inv(start, size) _dma_cache_inv(start, size)
594
595 #else /* Sane hardware */
596
597 #define dma_cache_wback_inv(start,size) \
598 do { (void) (start); (void) (size); } while (0)
599 #define dma_cache_wback(start,size) \
600 do { (void) (start); (void) (size); } while (0)
601 #define dma_cache_inv(start,size) \
602 do { (void) (start); (void) (size); } while (0)
603
604 #endif /* CONFIG_DMA_NONCOHERENT */
605
606 /*
607 * Read a 32-bit register that requires a 64-bit read cycle on the bus.
608 * Avoid interrupt mucking, just adjust the address for 4-byte access.
609 * Assume the addresses are 8-byte aligned.
610 */
611 #ifdef __MIPSEB__
612 #define __CSR_32_ADJUST 4
613 #else
614 #define __CSR_32_ADJUST 0
615 #endif
616
617 #define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
618 #define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
619
620 /*
621 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
622 * access
623 */
624 #define xlate_dev_mem_ptr(p) __va(p)
625
626 /*
627 * Convert a virtual cached pointer to an uncached pointer
628 */
629 #define xlate_dev_kmem_ptr(p) p
630
631 #endif /* _ASM_IO_H */
632