1 /*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * Copyright (C) 2001 Ralf Baechle
6 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
7 * Author: Maciej W. Rozycki <macro@mips.com>
8 *
9 * This file define the irq handler for MIPS CPU interrupts.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 */
16
17 /*
18 * Almost all MIPS CPUs define 8 interrupt sources. They are typically
19 * level triggered (i.e., cannot be cleared from CPU; must be cleared from
20 * device). The first two are software interrupts which we don't really
21 * use or support. The last one is usually the CPU timer interrupt if
22 * counter register is present or, for CPUs with an external FPU, by
23 * convention it's the FPU exception interrupt.
24 *
25 * Don't even think about using this on SMP. You have been warned.
26 *
27 * This file exports one global function:
28 * void mips_cpu_irq_init(void);
29 * and one variable:
30 * unsigned mips_smp_c0_status_mask;
31 */
32 #include <linux/init.h>
33 #include <linux/interrupt.h>
34 #include <linux/kernel.h>
35 #include <linux/irq.h>
36 #include <linux/irqdomain.h>
37
38 #include <asm/irq_cpu.h>
39 #include <asm/mipsregs.h>
40 #include <asm/mipsmtregs.h>
41
42 unsigned mips_smp_c0_status_mask;
43
unmask_mips_irq(struct irq_data * d)44 static inline void unmask_mips_irq(struct irq_data *d)
45 {
46 set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
47 irq_enable_hazard();
48 }
49
mask_mips_irq(struct irq_data * d)50 static inline void mask_mips_irq(struct irq_data *d)
51 {
52 clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
53 irq_disable_hazard();
54 }
55
56 static struct irq_chip mips_cpu_irq_controller = {
57 .name = "MIPS",
58 .irq_ack = mask_mips_irq,
59 .irq_mask = mask_mips_irq,
60 .irq_mask_ack = mask_mips_irq,
61 .irq_unmask = unmask_mips_irq,
62 .irq_eoi = unmask_mips_irq,
63 };
64
65 /*
66 * Basically the same as above but taking care of all the MT stuff
67 */
68
mips_mt_cpu_irq_startup(struct irq_data * d)69 static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
70 {
71 unsigned int vpflags = dvpe();
72
73 clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
74 evpe(vpflags);
75 unmask_mips_irq(d);
76 return 0;
77 }
78
79 /*
80 * While we ack the interrupt interrupts are disabled and thus we don't need
81 * to deal with concurrency issues. Same for mips_cpu_irq_end.
82 */
mips_mt_cpu_irq_ack(struct irq_data * d)83 static void mips_mt_cpu_irq_ack(struct irq_data *d)
84 {
85 unsigned int vpflags = dvpe();
86 clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
87 evpe(vpflags);
88 mask_mips_irq(d);
89 }
90
91 static struct irq_chip mips_mt_cpu_irq_controller = {
92 .name = "MIPS",
93 .irq_startup = mips_mt_cpu_irq_startup,
94 .irq_ack = mips_mt_cpu_irq_ack,
95 .irq_mask = mask_mips_irq,
96 .irq_mask_ack = mips_mt_cpu_irq_ack,
97 .irq_unmask = unmask_mips_irq,
98 .irq_eoi = unmask_mips_irq,
99 };
100
mips_cpu_irq_init(void)101 void __init mips_cpu_irq_init(void)
102 {
103 int irq_base = MIPS_CPU_IRQ_BASE;
104 int i;
105
106 /* Mask interrupts. */
107 clear_c0_status(ST0_IM);
108 clear_c0_cause(CAUSEF_IP);
109
110 /* Software interrupts are used for MT/CMT IPI */
111 for (i = irq_base; i < irq_base + 2; i++)
112 irq_set_chip_and_handler(i, cpu_has_mipsmt ?
113 &mips_mt_cpu_irq_controller :
114 &mips_cpu_irq_controller,
115 handle_percpu_irq);
116
117 for (i = irq_base + 2; i < irq_base + 8; i++)
118 irq_set_chip_and_handler(i, &mips_cpu_irq_controller,
119 handle_percpu_irq);
120 }
121
122 #ifdef CONFIG_IRQ_DOMAIN
mips_cpu_intc_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw)123 static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq,
124 irq_hw_number_t hw)
125 {
126 static struct irq_chip *chip;
127
128 if (hw < 2 && cpu_has_mipsmt) {
129 /* Software interrupts are used for MT/CMT IPI */
130 chip = &mips_mt_cpu_irq_controller;
131 } else {
132 chip = &mips_cpu_irq_controller;
133 }
134
135 irq_set_chip_and_handler(irq, chip, handle_percpu_irq);
136
137 return 0;
138 }
139
140 static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = {
141 .map = mips_cpu_intc_map,
142 .xlate = irq_domain_xlate_onecell,
143 };
144
mips_cpu_intc_init(struct device_node * of_node,struct device_node * parent)145 int __init mips_cpu_intc_init(struct device_node *of_node,
146 struct device_node *parent)
147 {
148 struct irq_domain *domain;
149
150 /* Mask interrupts. */
151 clear_c0_status(ST0_IM);
152 clear_c0_cause(CAUSEF_IP);
153
154 domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
155 &mips_cpu_intc_irq_domain_ops, NULL);
156 if (!domain)
157 panic("Failed to add irqdomain for MIPS CPU\n");
158
159 return 0;
160 }
161 #endif /* CONFIG_IRQ_DOMAIN */
162