1 /*
2 * Copyright (C) 1995, 1996, 2001 Ralf Baechle
3 * Copyright (C) 2001, 2004 MIPS Technologies, Inc.
4 * Copyright (C) 2004 Maciej W. Rozycki
5 */
6 #include <linux/delay.h>
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
9 #include <linux/seq_file.h>
10 #include <asm/bootinfo.h>
11 #include <asm/cpu.h>
12 #include <asm/cpu-features.h>
13 #include <asm/idle.h>
14 #include <asm/mipsregs.h>
15 #include <asm/processor.h>
16 #include <asm/prom.h>
17
18 unsigned int vced_count, vcei_count;
19
show_cpuinfo(struct seq_file * m,void * v)20 static int show_cpuinfo(struct seq_file *m, void *v)
21 {
22 unsigned long n = (unsigned long) v - 1;
23 unsigned int version = cpu_data[n].processor_id;
24 unsigned int fp_vers = cpu_data[n].fpu_id;
25 char fmt [64];
26 int i;
27
28 #ifdef CONFIG_SMP
29 if (!cpu_online(n))
30 return 0;
31 #endif
32
33 /*
34 * For the first processor also print the system type
35 */
36 if (n == 0) {
37 seq_printf(m, "system type\t\t: %s\n", get_system_type());
38 #ifndef CONFIG_GOLDFISH
39 if (mips_get_machine_name())
40 seq_printf(m, "machine\t\t\t: %s\n",
41 mips_get_machine_name());
42 #else
43 /*
44 * This is needed by the Android init process to run
45 * target specific startup code
46 */
47 seq_printf(m, "Hardware\t\t: %s\n", mips_get_machine_name());
48 seq_printf(m, "Revison\t\t\t: %d\n", 1);
49 #endif
50
51 }
52
53 seq_printf(m, "processor\t\t: %ld\n", n);
54 sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
55 cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : "");
56 seq_printf(m, fmt, __cpu_name[n],
57 (version >> 4) & 0x0f, version & 0x0f,
58 (fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
59 seq_printf(m, "BogoMIPS\t\t: %u.%02u\n",
60 cpu_data[n].udelay_val / (500000/HZ),
61 (cpu_data[n].udelay_val / (5000/HZ)) % 100);
62 seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
63 seq_printf(m, "microsecond timers\t: %s\n",
64 cpu_has_counter ? "yes" : "no");
65 seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize);
66 seq_printf(m, "extra interrupt vector\t: %s\n",
67 cpu_has_divec ? "yes" : "no");
68 seq_printf(m, "hardware watchpoint\t: %s",
69 cpu_has_watch ? "yes, " : "no\n");
70 if (cpu_has_watch) {
71 seq_printf(m, "count: %d, address/irw mask: [",
72 cpu_data[n].watch_reg_count);
73 for (i = 0; i < cpu_data[n].watch_reg_count; i++)
74 seq_printf(m, "%s0x%04x", i ? ", " : "" ,
75 cpu_data[n].watch_reg_masks[i]);
76 seq_printf(m, "]\n");
77 }
78 if (cpu_has_mips_r) {
79 seq_printf(m, "isa\t\t\t:");
80 if (cpu_has_mips_1)
81 seq_printf(m, "%s", " mips1");
82 if (cpu_has_mips_2)
83 seq_printf(m, "%s", " mips2");
84 if (cpu_has_mips_3)
85 seq_printf(m, "%s", " mips3");
86 if (cpu_has_mips_4)
87 seq_printf(m, "%s", " mips4");
88 if (cpu_has_mips_5)
89 seq_printf(m, "%s", " mips5");
90 if (cpu_has_mips32r1)
91 seq_printf(m, "%s", " mips32r1");
92 if (cpu_has_mips32r2)
93 seq_printf(m, "%s", " mips32r2");
94 if (cpu_has_mips32r6)
95 seq_printf(m, "%s", " mips32r6");
96 if (cpu_has_mips64r1)
97 seq_printf(m, "%s", " mips64r1");
98 if (cpu_has_mips64r2)
99 seq_printf(m, "%s", " mips64r2");
100 if (cpu_has_mips64r6)
101 seq_printf(m, "%s", " mips64r6");
102 seq_printf(m, "\n");
103 }
104
105 seq_printf(m, "ASEs implemented\t:");
106 if (cpu_has_mips16) seq_printf(m, "%s", " mips16");
107 if (cpu_has_mdmx) seq_printf(m, "%s", " mdmx");
108 if (cpu_has_mips3d) seq_printf(m, "%s", " mips3d");
109 if (cpu_has_smartmips) seq_printf(m, "%s", " smartmips");
110 if (cpu_has_dsp) seq_printf(m, "%s", " dsp");
111 if (cpu_has_dsp2) seq_printf(m, "%s", " dsp2");
112 if (cpu_has_mipsmt) seq_printf(m, "%s", " mt");
113 if (cpu_has_mmips) seq_printf(m, "%s", " micromips");
114 if (cpu_has_vz) seq_printf(m, "%s", " vz");
115 if (cpu_has_eva) seq_printf(m, "%s", " eva");
116 if (cpu_has_htw) seq_printf(m, "%s", " htw");
117 if (cpu_has_msa) seq_printf(m, "%s", " msa");
118 seq_printf(m, "\n");
119
120
121 seq_printf(m, "shadow register sets\t: %d\n",
122 cpu_data[n].srsets);
123 seq_printf(m, "kscratch registers\t: %d\n",
124 hweight8(cpu_data[n].kscratch_mask));
125 seq_printf(m, "core\t\t\t: %d\n", cpu_data[n].core);
126 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
127 if (cpu_has_mipsmt) {
128 seq_printf(m, "VPE\t\t\t: %d\n", cpu_data[n].vpe_id);
129 #if defined(CONFIG_MIPS_MT_SMTC)
130 seq_printf(m, "TC\t\t\t: %d\n", cpu_data[n].tc_id);
131 #endif
132 }
133 #endif
134
135 sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
136 cpu_has_vce ? "%u" : "not available");
137 seq_printf(m, fmt, 'D', vced_count);
138 seq_printf(m, fmt, 'I', vcei_count);
139
140 seq_printf(m, "kernel modes\t\t:");
141 #ifdef CONFIG_64BIT
142 seq_printf(m, " 64bit");
143 #else
144 seq_printf(m, " 32bit");
145 #endif
146 #ifdef CONFIG_64BIT_PHYS_ADDR
147 seq_printf(m, " 64bit-address");
148 #endif
149 #ifdef CONFIG_EVA
150 seq_printf(m, " eva");
151 #endif
152 #ifdef CONFIG_HIGHMEM
153 seq_printf(m, " highmem");
154 #endif
155 if (cpu_has_mmips && (read_c0_config3() & MIPS_CONF3_ISA_OE))
156 seq_printf(m, " micromips");
157 #ifdef CONFIG_SMP
158 seq_printf(m, " smp");
159 #endif
160 seq_printf(m, "\n");
161
162 seq_printf(m, "\n");
163
164 return 0;
165 }
166
c_start(struct seq_file * m,loff_t * pos)167 static void *c_start(struct seq_file *m, loff_t *pos)
168 {
169 unsigned long i = *pos;
170
171 return i < NR_CPUS ? (void *) (i + 1) : NULL;
172 }
173
c_next(struct seq_file * m,void * v,loff_t * pos)174 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
175 {
176 ++*pos;
177 return c_start(m, pos);
178 }
179
c_stop(struct seq_file * m,void * v)180 static void c_stop(struct seq_file *m, void *v)
181 {
182 }
183
184 const struct seq_operations cpuinfo_op = {
185 .start = c_start,
186 .next = c_next,
187 .stop = c_stop,
188 .show = show_cpuinfo,
189 };
190