1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * PROM library initialisation code.
7 *
8 * Copyright (C) 1999,2000,2004,2005,2012 MIPS Technologies, Inc.
9 * All rights reserved.
10 * Authors: Carsten Langgaard <carstenl@mips.com>
11 * Maciej W. Rozycki <macro@mips.com>
12 * Steven J. Hill <sjhill@mips.com>
13 */
14 #include <linux/init.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17
18 #include <asm/cacheflush.h>
19 #include <asm/smp-ops.h>
20 #include <asm/traps.h>
21 #include <asm/fw/fw.h>
22 #include <asm/gcmpregs.h>
23 #include <asm/cpcregs.h>
24 #include <asm/mips-boards/generic.h>
25 #include <asm/mips-boards/malta.h>
26
27 static int mips_revision_corid;
28 int mips_revision_sconid;
29
30 /* Bonito64 system controller register base. */
31 unsigned long _pcictrl_bonito;
32 unsigned long _pcictrl_bonito_pcicfg;
33
34 /* GT64120 system controller register base */
35 unsigned long _pcictrl_gt64120;
36
37 /* MIPS System controller register base */
38 unsigned long _pcictrl_msc;
39
40 #ifdef CONFIG_SERIAL_8250_CONSOLE
console_config(void)41 static void __init console_config(void)
42 {
43 char console_string[40];
44 int baud = 0;
45 char parity = '\0', bits = '\0', flow = '\0';
46 char *s;
47
48 if ((strstr(fw_getcmdline(), "console=")) == NULL) {
49 s = fw_getenv("modetty0");
50 if (s) {
51 while (*s >= '0' && *s <= '9')
52 baud = baud*10 + *s++ - '0';
53 if (*s == ',')
54 s++;
55 if (*s)
56 parity = *s++;
57 if (*s == ',')
58 s++;
59 if (*s)
60 bits = *s++;
61 if (*s == ',')
62 s++;
63 if (*s == 'h')
64 flow = 'r';
65 }
66 if (baud == 0)
67 baud = 38400;
68 if (parity != 'n' && parity != 'o' && parity != 'e')
69 parity = 'n';
70 if (bits != '7' && bits != '8')
71 bits = '8';
72 if (flow == '\0')
73 flow = 'r';
74 sprintf(console_string, " console=ttyS0,%d%c%c%c", baud,
75 parity, bits, flow);
76 strcat(fw_getcmdline(), console_string);
77 pr_info("Config serial console:%s\n", console_string);
78 }
79 }
80 #endif
81
mips_nmi_setup(void)82 static void __init mips_nmi_setup(void)
83 {
84 void *base;
85 extern char except_vec_nmi;
86
87 base = cpu_has_veic ?
88 #ifndef CONFIG_EVA
89 (void *)(CAC_BASE + 0xa80) :
90 (void *)(CAC_BASE + 0x380);
91 #else
92 (void *)(YAMON_BASE + 0xa80) :
93 (void *)(YAMON_BASE + 0x380);
94 #endif
95 memcpy(base, &except_vec_nmi, 0x80);
96 local_flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
97 }
98
mips_ejtag_setup(void)99 static void __init mips_ejtag_setup(void)
100 {
101 void *base;
102 extern char except_vec_ejtag_debug;
103
104 base = cpu_has_veic ?
105 #ifndef CONFIG_EVA
106 (void *)(CAC_BASE + 0xa00) :
107 (void *)(CAC_BASE + 0x300);
108 #else
109 (void *)(YAMON_BASE + 0xa00) :
110 (void *)(YAMON_BASE + 0x300);
111 #endif
112 memcpy(base, &except_vec_ejtag_debug, 0x80);
113 local_flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
114 }
115
116 void __init prom_mem_check(int niocu);
117 extern struct plat_smp_ops msmtc_smp_ops;
118
prom_init(void)119 void __init prom_init(void)
120 {
121 mips_display_message("LINUX");
122
123 /*
124 * early setup of _pcictrl_bonito so that we can determine
125 * the system controller on a CORE_EMUL board
126 */
127 _pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE);
128
129 mips_revision_corid = MIPS_REVISION_CORID;
130
131 if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) {
132 if (BONITO_PCIDID == 0x0001df53 ||
133 BONITO_PCIDID == 0x0003df53)
134 mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON;
135 else
136 mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC;
137 }
138
139 mips_revision_sconid = MIPS_REVISION_SCONID;
140 if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) {
141 switch (mips_revision_corid) {
142 case MIPS_REVISION_CORID_QED_RM5261:
143 case MIPS_REVISION_CORID_CORE_LV:
144 case MIPS_REVISION_CORID_CORE_FPGA:
145 case MIPS_REVISION_CORID_CORE_FPGAR2:
146 mips_revision_sconid = MIPS_REVISION_SCON_GT64120;
147 break;
148 case MIPS_REVISION_CORID_CORE_EMUL_BON:
149 case MIPS_REVISION_CORID_BONITO64:
150 case MIPS_REVISION_CORID_CORE_20K:
151 mips_revision_sconid = MIPS_REVISION_SCON_BONITO;
152 break;
153 case MIPS_REVISION_CORID_CORE_MSC:
154 case MIPS_REVISION_CORID_CORE_FPGA2:
155 case MIPS_REVISION_CORID_CORE_24K:
156 /*
157 * SOCit/ROCit support is essentially identical
158 * but make an attempt to distinguish them
159 */
160 mips_revision_sconid = MIPS_REVISION_SCON_SOCIT;
161 break;
162 case MIPS_REVISION_CORID_CORE_FPGA3:
163 case MIPS_REVISION_CORID_CORE_FPGA4:
164 case MIPS_REVISION_CORID_CORE_FPGA5:
165 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
166 default:
167 /* See above */
168 mips_revision_sconid = MIPS_REVISION_SCON_ROCIT;
169 break;
170 }
171 }
172
173 switch (mips_revision_sconid) {
174 u32 start, map, mask, data;
175
176 case MIPS_REVISION_SCON_GT64120:
177 /*
178 * Setup the North bridge to do Master byte-lane swapping
179 * when running in bigendian.
180 */
181 _pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000);
182
183 #ifdef CONFIG_CPU_LITTLE_ENDIAN
184 GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT |
185 GT_PCI0_CMD_SBYTESWAP_BIT);
186 #else
187 GT_WRITE(GT_PCI0_CMD_OFS, 0);
188 #endif
189 /* Fix up PCI I/O mapping if necessary (for Atlas). */
190 start = GT_READ(GT_PCI0IOLD_OFS);
191 map = GT_READ(GT_PCI0IOREMAP_OFS);
192 if ((start & map) != 0) {
193 map &= ~start;
194 GT_WRITE(GT_PCI0IOREMAP_OFS, map);
195 }
196
197 set_io_port_base(MALTA_GT_PORT_BASE);
198 break;
199
200 case MIPS_REVISION_SCON_BONITO:
201 _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE);
202
203 /*
204 * Disable Bonito IOBC.
205 */
206 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
207 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
208 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
209
210 /*
211 * Setup the North bridge to do Master byte-lane swapping
212 * when running in bigendian.
213 */
214 #ifdef CONFIG_CPU_LITTLE_ENDIAN
215 BONITO_BONGENCFG = BONITO_BONGENCFG &
216 ~(BONITO_BONGENCFG_MSTRBYTESWAP |
217 BONITO_BONGENCFG_BYTESWAP);
218 #else
219 BONITO_BONGENCFG = BONITO_BONGENCFG |
220 BONITO_BONGENCFG_MSTRBYTESWAP |
221 BONITO_BONGENCFG_BYTESWAP;
222 #endif
223
224 set_io_port_base(MALTA_BONITO_PORT_BASE);
225 break;
226
227 case MIPS_REVISION_SCON_SOCIT:
228 case MIPS_REVISION_SCON_ROCIT:
229 _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000);
230 mips_pci_controller:
231 mb();
232 MSC_READ(MSC01_PCI_CFG, data);
233 MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT);
234 wmb();
235
236 /* Fix up lane swapping. */
237 #ifdef CONFIG_CPU_LITTLE_ENDIAN
238 MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP);
239 #else
240 MSC_WRITE(MSC01_PCI_SWAP,
241 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF |
242 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF |
243 MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF);
244 #endif
245 /* Fix up target memory mapping. */
246 #ifndef CONFIG_EVA
247 MSC_READ(MSC01_PCI_BAR0, mask);
248 MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK);
249 #else
250 #ifdef CONFIG_EVA_OLD_MALTA_MAP
251 /* Classic (old) Malta memory map:
252 Setup the Malta max (2GB) memory for PCI DMA in host bridge
253 in transparent addressing mode, starting from 80000000.
254 Don't believe in registers content */
255 mask = 0x80000008;
256 MSC_WRITE(MSC01_PCI_BAR0, mask);
257
258 mask = 0x80000000;
259 MSC_WRITE(MSC01_PCI_HEAD4, mask);
260 MSC_WRITE(MSC01_PCI_P2SCMSKL, mask);
261 MSC_WRITE(MSC01_PCI_P2SCMAPL, mask);
262 #else
263 /* New Malta memory map:
264 Setup the Malta max memory (2G) for PCI DMA in host bridge
265 in transparent addressing mode, starting from 00000000.
266 Don't believe in registers content */
267 mask = 0x80000008;
268 MSC_WRITE(MSC01_PCI_BAR0, mask);
269
270 mask = 0x00000000;
271 MSC_WRITE(MSC01_PCI_HEAD4, mask);
272 mask = 0x80000000;
273 MSC_WRITE(MSC01_PCI_P2SCMSKL, mask);
274 mask = 0x00000000;
275 MSC_WRITE(MSC01_PCI_P2SCMAPL, mask);
276 #endif
277 #endif
278
279 /* Don't handle target retries indefinitely. */
280 if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) ==
281 MSC01_PCI_CFG_MAXRTRY_MSK)
282 data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK <<
283 MSC01_PCI_CFG_MAXRTRY_SHF)) |
284 ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) <<
285 MSC01_PCI_CFG_MAXRTRY_SHF);
286
287 wmb();
288 MSC_WRITE(MSC01_PCI_CFG, data);
289 mb();
290
291 set_io_port_base(MALTA_MSC_PORT_BASE);
292 break;
293
294 case MIPS_REVISION_SCON_SOCITSC:
295 case MIPS_REVISION_SCON_SOCITSCP:
296 _pcictrl_msc = (unsigned long)ioremap(MIPS_SOCITSC_PCI_REG_BASE, 0x2000);
297 goto mips_pci_controller;
298
299 default:
300 /* Unknown system controller */
301 mips_display_message("SC Error");
302 while (1); /* We die here... */
303 }
304 board_nmi_handler_setup = mips_nmi_setup;
305 board_ejtag_handler_setup = mips_ejtag_setup;
306
307 fw_init_cmdline();
308 fw_meminit();
309 #ifdef CONFIG_SERIAL_8250_CONSOLE
310 console_config();
311 #endif
312 #ifdef CONFIG_MIPS_CMP
313 /* Early detection of CMP support */
314 if ((mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) &&
315 (mips_revision_sconid != MIPS_REVISION_SCON_GT64120)) {
316 gcmp_present = 0;
317 printk("GCMP NOT present\n");
318 } else if (gcmp_probe(GCMP_BASE_ADDR_MALTA, GCMP_ADDRSPACE_SZ_MALTA)) {
319 cpc_probe(CPC_BASE_ADDR_MALTA, CPC_ADDRSPACE_SZ_MALTA);
320 #if defined(CONFIG_EVA) && !defined(CONFIG_EVA_OLD_MALTA_MAP)
321 prom_mem_check(gcmp_niocu());
322 #endif
323 if (!register_cmp_smp_ops())
324 return;
325 }
326 #endif
327
328 if (!register_vsmp_smp_ops())
329 return;
330
331 #ifdef CONFIG_MIPS_MT_SMTC
332 register_smp_ops(&msmtc_smp_ops);
333 #endif
334 }
335