1/* 2 * B4420 Silicon/SoC Device Tree Source (pre include) 3 * 4 * Copyright 2012 Freescale Semiconductor, Inc. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * * Neither the name of Freescale Semiconductor nor the 14 * names of its contributors may be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * 18 * ALTERNATIVELY, this software may be distributed under the terms of the 19 * GNU General Public License ("GPL") as published by the Free Software 20 * Foundation, either version 2 of that License or (at your option) any 21 * later version. 22 * 23 * This software is provided by Freescale Semiconductor "as is" and any 24 * express or implied warranties, including, but not limited to, the implied 25 * warranties of merchantability and fitness for a particular purpose are 26 * disclaimed. In no event shall Freescale Semiconductor be liable for any 27 * direct, indirect, incidental, special, exemplary, or consequential damages 28 * (including, but not limited to, procurement of substitute goods or services; 29 * loss of use, data, or profits; or business interruption) however caused and 30 * on any theory of liability, whether in contract, strict liability, or tort 31 * (including negligence or otherwise) arising in any way out of the use of 32 * this software, even if advised of the possibility of such damage. 33 */ 34 35/dts-v1/; 36 37/ { 38 compatible = "fsl,B4420"; 39 #address-cells = <2>; 40 #size-cells = <2>; 41 interrupt-parent = <&mpic>; 42 43 aliases { 44 ccsr = &soc; 45 dcsr = &dcsr; 46 47 serial0 = &serial0; 48 serial1 = &serial1; 49 serial2 = &serial2; 50 serial3 = &serial3; 51 pci0 = &pci0; 52 dma0 = &dma0; 53 dma1 = &dma1; 54 sdhc = &sdhc; 55 }; 56 57 58 cpus { 59 #address-cells = <1>; 60 #size-cells = <0>; 61 62 cpu0: PowerPC,e6500@0 { 63 device_type = "cpu"; 64 reg = <0 1>; 65 next-level-cache = <&L2>; 66 }; 67 cpu1: PowerPC,e6500@2 { 68 device_type = "cpu"; 69 reg = <2 3>; 70 next-level-cache = <&L2>; 71 }; 72 }; 73}; 74