1/* 2 * MPC8541 CDS Device Tree Source 3 * 4 * Copyright 2006, 2008 Freescale Semiconductor Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 */ 11 12/dts-v1/; 13 14/include/ "fsl/e500v2_power_isa.dtsi" 15 16/ { 17 model = "MPC8541CDS"; 18 compatible = "MPC8541CDS", "MPC85xxCDS"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 22 aliases { 23 ethernet0 = &enet0; 24 ethernet1 = &enet1; 25 serial0 = &serial0; 26 serial1 = &serial1; 27 pci0 = &pci0; 28 pci1 = &pci1; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 PowerPC,8541@0 { 36 device_type = "cpu"; 37 reg = <0x0>; 38 d-cache-line-size = <32>; // 32 bytes 39 i-cache-line-size = <32>; // 32 bytes 40 d-cache-size = <0x8000>; // L1, 32K 41 i-cache-size = <0x8000>; // L1, 32K 42 timebase-frequency = <0>; // 33 MHz, from uboot 43 bus-frequency = <0>; // 166 MHz 44 clock-frequency = <0>; // 825 MHz, from uboot 45 next-level-cache = <&L2>; 46 }; 47 }; 48 49 memory { 50 device_type = "memory"; 51 reg = <0x0 0x8000000>; // 128M at 0x0 52 }; 53 54 soc8541@e0000000 { 55 #address-cells = <1>; 56 #size-cells = <1>; 57 device_type = "soc"; 58 compatible = "simple-bus"; 59 ranges = <0x0 0xe0000000 0x100000>; 60 bus-frequency = <0>; 61 62 ecm-law@0 { 63 compatible = "fsl,ecm-law"; 64 reg = <0x0 0x1000>; 65 fsl,num-laws = <8>; 66 }; 67 68 ecm@1000 { 69 compatible = "fsl,mpc8541-ecm", "fsl,ecm"; 70 reg = <0x1000 0x1000>; 71 interrupts = <17 2>; 72 interrupt-parent = <&mpic>; 73 }; 74 75 memory-controller@2000 { 76 compatible = "fsl,mpc8541-memory-controller"; 77 reg = <0x2000 0x1000>; 78 interrupt-parent = <&mpic>; 79 interrupts = <18 2>; 80 }; 81 82 L2: l2-cache-controller@20000 { 83 compatible = "fsl,mpc8541-l2-cache-controller"; 84 reg = <0x20000 0x1000>; 85 cache-line-size = <32>; // 32 bytes 86 cache-size = <0x40000>; // L2, 256K 87 interrupt-parent = <&mpic>; 88 interrupts = <16 2>; 89 }; 90 91 i2c@3000 { 92 #address-cells = <1>; 93 #size-cells = <0>; 94 cell-index = <0>; 95 compatible = "fsl-i2c"; 96 reg = <0x3000 0x100>; 97 interrupts = <43 2>; 98 interrupt-parent = <&mpic>; 99 dfsrr; 100 }; 101 102 dma@21300 { 103 #address-cells = <1>; 104 #size-cells = <1>; 105 compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma"; 106 reg = <0x21300 0x4>; 107 ranges = <0x0 0x21100 0x200>; 108 cell-index = <0>; 109 dma-channel@0 { 110 compatible = "fsl,mpc8541-dma-channel", 111 "fsl,eloplus-dma-channel"; 112 reg = <0x0 0x80>; 113 cell-index = <0>; 114 interrupt-parent = <&mpic>; 115 interrupts = <20 2>; 116 }; 117 dma-channel@80 { 118 compatible = "fsl,mpc8541-dma-channel", 119 "fsl,eloplus-dma-channel"; 120 reg = <0x80 0x80>; 121 cell-index = <1>; 122 interrupt-parent = <&mpic>; 123 interrupts = <21 2>; 124 }; 125 dma-channel@100 { 126 compatible = "fsl,mpc8541-dma-channel", 127 "fsl,eloplus-dma-channel"; 128 reg = <0x100 0x80>; 129 cell-index = <2>; 130 interrupt-parent = <&mpic>; 131 interrupts = <22 2>; 132 }; 133 dma-channel@180 { 134 compatible = "fsl,mpc8541-dma-channel", 135 "fsl,eloplus-dma-channel"; 136 reg = <0x180 0x80>; 137 cell-index = <3>; 138 interrupt-parent = <&mpic>; 139 interrupts = <23 2>; 140 }; 141 }; 142 143 enet0: ethernet@24000 { 144 #address-cells = <1>; 145 #size-cells = <1>; 146 cell-index = <0>; 147 device_type = "network"; 148 model = "TSEC"; 149 compatible = "gianfar"; 150 reg = <0x24000 0x1000>; 151 ranges = <0x0 0x24000 0x1000>; 152 local-mac-address = [ 00 00 00 00 00 00 ]; 153 interrupts = <29 2 30 2 34 2>; 154 interrupt-parent = <&mpic>; 155 tbi-handle = <&tbi0>; 156 phy-handle = <&phy0>; 157 158 mdio@520 { 159 #address-cells = <1>; 160 #size-cells = <0>; 161 compatible = "fsl,gianfar-mdio"; 162 reg = <0x520 0x20>; 163 164 phy0: ethernet-phy@0 { 165 interrupt-parent = <&mpic>; 166 interrupts = <5 1>; 167 reg = <0x0>; 168 device_type = "ethernet-phy"; 169 }; 170 phy1: ethernet-phy@1 { 171 interrupt-parent = <&mpic>; 172 interrupts = <5 1>; 173 reg = <0x1>; 174 device_type = "ethernet-phy"; 175 }; 176 tbi0: tbi-phy@11 { 177 reg = <0x11>; 178 device_type = "tbi-phy"; 179 }; 180 }; 181 }; 182 183 enet1: ethernet@25000 { 184 #address-cells = <1>; 185 #size-cells = <1>; 186 cell-index = <1>; 187 device_type = "network"; 188 model = "TSEC"; 189 compatible = "gianfar"; 190 reg = <0x25000 0x1000>; 191 ranges = <0x0 0x25000 0x1000>; 192 local-mac-address = [ 00 00 00 00 00 00 ]; 193 interrupts = <35 2 36 2 40 2>; 194 interrupt-parent = <&mpic>; 195 tbi-handle = <&tbi1>; 196 phy-handle = <&phy1>; 197 198 mdio@520 { 199 #address-cells = <1>; 200 #size-cells = <0>; 201 compatible = "fsl,gianfar-tbi"; 202 reg = <0x520 0x20>; 203 204 tbi1: tbi-phy@11 { 205 reg = <0x11>; 206 device_type = "tbi-phy"; 207 }; 208 }; 209 }; 210 211 serial0: serial@4500 { 212 cell-index = <0>; 213 device_type = "serial"; 214 compatible = "fsl,ns16550", "ns16550"; 215 reg = <0x4500 0x100>; // reg base, size 216 clock-frequency = <0>; // should we fill in in uboot? 217 interrupts = <42 2>; 218 interrupt-parent = <&mpic>; 219 }; 220 221 serial1: serial@4600 { 222 cell-index = <1>; 223 device_type = "serial"; 224 compatible = "fsl,ns16550", "ns16550"; 225 reg = <0x4600 0x100>; // reg base, size 226 clock-frequency = <0>; // should we fill in in uboot? 227 interrupts = <42 2>; 228 interrupt-parent = <&mpic>; 229 }; 230 231 crypto@30000 { 232 compatible = "fsl,sec2.0"; 233 reg = <0x30000 0x10000>; 234 interrupts = <45 2>; 235 interrupt-parent = <&mpic>; 236 fsl,num-channels = <4>; 237 fsl,channel-fifo-len = <24>; 238 fsl,exec-units-mask = <0x7e>; 239 fsl,descriptor-types-mask = <0x01010ebf>; 240 }; 241 242 mpic: pic@40000 { 243 interrupt-controller; 244 #address-cells = <0>; 245 #interrupt-cells = <2>; 246 reg = <0x40000 0x40000>; 247 compatible = "chrp,open-pic"; 248 device_type = "open-pic"; 249 }; 250 251 cpm@919c0 { 252 #address-cells = <1>; 253 #size-cells = <1>; 254 compatible = "fsl,mpc8541-cpm", "fsl,cpm2"; 255 reg = <0x919c0 0x30>; 256 ranges; 257 258 muram@80000 { 259 #address-cells = <1>; 260 #size-cells = <1>; 261 ranges = <0x0 0x80000 0x10000>; 262 263 data@0 { 264 compatible = "fsl,cpm-muram-data"; 265 reg = <0x0 0x2000 0x9000 0x1000>; 266 }; 267 }; 268 269 brg@919f0 { 270 compatible = "fsl,mpc8541-brg", 271 "fsl,cpm2-brg", 272 "fsl,cpm-brg"; 273 reg = <0x919f0 0x10 0x915f0 0x10>; 274 }; 275 276 cpmpic: pic@90c00 { 277 interrupt-controller; 278 #address-cells = <0>; 279 #interrupt-cells = <2>; 280 interrupts = <46 2>; 281 interrupt-parent = <&mpic>; 282 reg = <0x90c00 0x80>; 283 compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic"; 284 }; 285 }; 286 }; 287 288 pci0: pci@e0008000 { 289 interrupt-map-mask = <0x1f800 0x0 0x0 0x7>; 290 interrupt-map = < 291 292 /* IDSEL 0x10 */ 293 0x8000 0x0 0x0 0x1 &mpic 0x0 0x1 294 0x8000 0x0 0x0 0x2 &mpic 0x1 0x1 295 0x8000 0x0 0x0 0x3 &mpic 0x2 0x1 296 0x8000 0x0 0x0 0x4 &mpic 0x3 0x1 297 298 /* IDSEL 0x11 */ 299 0x8800 0x0 0x0 0x1 &mpic 0x0 0x1 300 0x8800 0x0 0x0 0x2 &mpic 0x1 0x1 301 0x8800 0x0 0x0 0x3 &mpic 0x2 0x1 302 0x8800 0x0 0x0 0x4 &mpic 0x3 0x1 303 304 /* IDSEL 0x12 (Slot 1) */ 305 0x9000 0x0 0x0 0x1 &mpic 0x0 0x1 306 0x9000 0x0 0x0 0x2 &mpic 0x1 0x1 307 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1 308 0x9000 0x0 0x0 0x4 &mpic 0x3 0x1 309 310 /* IDSEL 0x13 (Slot 2) */ 311 0x9800 0x0 0x0 0x1 &mpic 0x1 0x1 312 0x9800 0x0 0x0 0x2 &mpic 0x2 0x1 313 0x9800 0x0 0x0 0x3 &mpic 0x3 0x1 314 0x9800 0x0 0x0 0x4 &mpic 0x0 0x1 315 316 /* IDSEL 0x14 (Slot 3) */ 317 0xa000 0x0 0x0 0x1 &mpic 0x2 0x1 318 0xa000 0x0 0x0 0x2 &mpic 0x3 0x1 319 0xa000 0x0 0x0 0x3 &mpic 0x0 0x1 320 0xa000 0x0 0x0 0x4 &mpic 0x1 0x1 321 322 /* IDSEL 0x15 (Slot 4) */ 323 0xa800 0x0 0x0 0x1 &mpic 0x3 0x1 324 0xa800 0x0 0x0 0x2 &mpic 0x0 0x1 325 0xa800 0x0 0x0 0x3 &mpic 0x1 0x1 326 0xa800 0x0 0x0 0x4 &mpic 0x2 0x1 327 328 /* Bus 1 (Tundra Bridge) */ 329 /* IDSEL 0x12 (ISA bridge) */ 330 0x19000 0x0 0x0 0x1 &mpic 0x0 0x1 331 0x19000 0x0 0x0 0x2 &mpic 0x1 0x1 332 0x19000 0x0 0x0 0x3 &mpic 0x2 0x1 333 0x19000 0x0 0x0 0x4 &mpic 0x3 0x1>; 334 interrupt-parent = <&mpic>; 335 interrupts = <24 2>; 336 bus-range = <0 0>; 337 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 338 0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>; 339 clock-frequency = <66666666>; 340 #interrupt-cells = <1>; 341 #size-cells = <2>; 342 #address-cells = <3>; 343 reg = <0xe0008000 0x1000>; 344 compatible = "fsl,mpc8540-pci"; 345 device_type = "pci"; 346 347 i8259@19000 { 348 interrupt-controller; 349 device_type = "interrupt-controller"; 350 reg = <0x19000 0x0 0x0 0x0 0x1>; 351 #address-cells = <0>; 352 #interrupt-cells = <2>; 353 compatible = "chrp,iic"; 354 interrupts = <1>; 355 interrupt-parent = <&pci0>; 356 }; 357 }; 358 359 pci1: pci@e0009000 { 360 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 361 interrupt-map = < 362 363 /* IDSEL 0x15 */ 364 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 365 0xa800 0x0 0x0 0x2 &mpic 0xb 0x1 366 0xa800 0x0 0x0 0x3 &mpic 0xb 0x1 367 0xa800 0x0 0x0 0x4 &mpic 0xb 0x1>; 368 interrupt-parent = <&mpic>; 369 interrupts = <25 2>; 370 bus-range = <0 0>; 371 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000 372 0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>; 373 clock-frequency = <66666666>; 374 #interrupt-cells = <1>; 375 #size-cells = <2>; 376 #address-cells = <3>; 377 reg = <0xe0009000 0x1000>; 378 compatible = "fsl,mpc8540-pci"; 379 device_type = "pci"; 380 }; 381}; 382