1/* 2 * This file contains low level CPU setup functions. 3 * Kumar Gala <galak@kernel.crashing.org> 4 * Copyright 2009 Freescale Semiconductor, Inc. 5 * 6 * Based on cpu_setup_6xx code by 7 * Benjamin Herrenschmidt <benh@kernel.crashing.org> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 * 14 */ 15 16#include <asm/processor.h> 17#include <asm/cputable.h> 18#include <asm/ppc_asm.h> 19#include <asm/mmu-book3e.h> 20#include <asm/asm-offsets.h> 21 22_GLOBAL(__e500_icache_setup) 23 mfspr r0, SPRN_L1CSR1 24 andi. r3, r0, L1CSR1_ICE 25 bnelr /* Already enabled */ 26 oris r0, r0, L1CSR1_CPE@h 27 ori r0, r0, (L1CSR1_ICFI | L1CSR1_ICLFR | L1CSR1_ICE) 28 mtspr SPRN_L1CSR1, r0 /* Enable I-Cache */ 29 isync 30 blr 31 32_GLOBAL(__e500_dcache_setup) 33 mfspr r0, SPRN_L1CSR0 34 andi. r3, r0, L1CSR0_DCE 35 bnelr /* Already enabled */ 36 msync 37 isync 38 li r0, 0 39 mtspr SPRN_L1CSR0, r0 /* Disable */ 40 msync 41 isync 42 li r0, (L1CSR0_DCFI | L1CSR0_CLFC) 43 mtspr SPRN_L1CSR0, r0 /* Invalidate */ 44 isync 451: mfspr r0, SPRN_L1CSR0 46 andi. r3, r0, L1CSR0_CLFC 47 bne+ 1b /* Wait for lock bits reset */ 48 oris r0, r0, L1CSR0_CPE@h 49 ori r0, r0, L1CSR0_DCE 50 msync 51 isync 52 mtspr SPRN_L1CSR0, r0 /* Enable */ 53 isync 54 blr 55 56_GLOBAL(__setup_cpu_e6500) 57 mflr r6 58#ifdef CONFIG_PPC64 59 bl .setup_altivec_ivors 60#endif 61 bl __setup_cpu_e5500 62 mtlr r6 63 blr 64 65#ifdef CONFIG_PPC32 66_GLOBAL(__setup_cpu_e200) 67 /* enable dedicated debug exception handling resources (Debug APU) */ 68 mfspr r3,SPRN_HID0 69 ori r3,r3,HID0_DAPUEN@l 70 mtspr SPRN_HID0,r3 71 b __setup_e200_ivors 72_GLOBAL(__setup_cpu_e500v1) 73_GLOBAL(__setup_cpu_e500v2) 74 mflr r4 75 bl __e500_icache_setup 76 bl __e500_dcache_setup 77 bl __setup_e500_ivors 78#ifdef CONFIG_FSL_RIO 79 /* Ensure that RFXE is set */ 80 mfspr r3,SPRN_HID1 81 oris r3,r3,HID1_RFXE@h 82 mtspr SPRN_HID1,r3 83#endif 84 mtlr r4 85 blr 86_GLOBAL(__setup_cpu_e500mc) 87_GLOBAL(__setup_cpu_e5500) 88 mflr r5 89 bl __e500_icache_setup 90 bl __e500_dcache_setup 91 bl __setup_e500mc_ivors 92 /* 93 * We only want to touch IVOR38-41 if we're running on hardware 94 * that supports category E.HV. The architectural way to determine 95 * this is MMUCFG[LPIDSIZE]. 96 */ 97 mfspr r3, SPRN_MMUCFG 98 rlwinm. r3, r3, 0, MMUCFG_LPIDSIZE 99 beq 1f 100 bl __setup_ehv_ivors 101 b 2f 1021: 103 lwz r3, CPU_SPEC_FEATURES(r4) 104 /* We need this check as cpu_setup is also called for 105 * the secondary cores. So, if we have already cleared 106 * the feature on the primary core, avoid doing it on the 107 * secondary core. 108 */ 109 andis. r6, r3, CPU_FTR_EMB_HV@h 110 beq 2f 111 rlwinm r3, r3, 0, ~CPU_FTR_EMB_HV 112 stw r3, CPU_SPEC_FEATURES(r4) 1132: 114 mtlr r5 115 blr 116#endif 117 118#ifdef CONFIG_PPC_BOOK3E_64 119_GLOBAL(__restore_cpu_e6500) 120 mflr r5 121 bl .setup_altivec_ivors 122 bl __restore_cpu_e5500 123 mtlr r5 124 blr 125 126_GLOBAL(__restore_cpu_e5500) 127 mflr r4 128 bl __e500_icache_setup 129 bl __e500_dcache_setup 130 bl .__setup_base_ivors 131 bl .setup_perfmon_ivor 132 bl .setup_doorbell_ivors 133 /* 134 * We only want to touch IVOR38-41 if we're running on hardware 135 * that supports category E.HV. The architectural way to determine 136 * this is MMUCFG[LPIDSIZE]. 137 */ 138 mfspr r10,SPRN_MMUCFG 139 rlwinm. r10,r10,0,MMUCFG_LPIDSIZE 140 beq 1f 141 bl .setup_ehv_ivors 1421: 143 mtlr r4 144 blr 145 146_GLOBAL(__setup_cpu_e5500) 147 mflr r5 148 bl __e500_icache_setup 149 bl __e500_dcache_setup 150 bl .__setup_base_ivors 151 bl .setup_perfmon_ivor 152 bl .setup_doorbell_ivors 153 /* 154 * We only want to touch IVOR38-41 if we're running on hardware 155 * that supports category E.HV. The architectural way to determine 156 * this is MMUCFG[LPIDSIZE]. 157 */ 158 mfspr r10,SPRN_MMUCFG 159 rlwinm. r10,r10,0,MMUCFG_LPIDSIZE 160 beq 1f 161 bl .setup_ehv_ivors 162 b 2f 1631: 164 ld r10,CPU_SPEC_FEATURES(r4) 165 LOAD_REG_IMMEDIATE(r9,CPU_FTR_EMB_HV) 166 andc r10,r10,r9 167 std r10,CPU_SPEC_FEATURES(r4) 1682: 169 mtlr r5 170 blr 171#endif 172