1 /*
2 * SH7366 Setup
3 *
4 * Copyright (C) 2008 Renesas Solutions
5 *
6 * Based on linux/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12 #include <linux/platform_device.h>
13 #include <linux/init.h>
14 #include <linux/serial.h>
15 #include <linux/serial_sci.h>
16 #include <linux/uio_driver.h>
17 #include <linux/sh_timer.h>
18 #include <linux/sh_intc.h>
19 #include <linux/usb/r8a66597.h>
20 #include <asm/clock.h>
21
22 static struct plat_sci_port scif0_platform_data = {
23 .mapbase = 0xffe00000,
24 .port_reg = 0xa405013e,
25 .flags = UPF_BOOT_AUTOCONF,
26 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
27 .scbrr_algo_id = SCBRR_ALGO_2,
28 .type = PORT_SCIF,
29 .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)),
30 };
31
32 static struct platform_device scif0_device = {
33 .name = "sh-sci",
34 .id = 0,
35 .dev = {
36 .platform_data = &scif0_platform_data,
37 },
38 };
39
40 static struct resource iic_resources[] = {
41 [0] = {
42 .name = "IIC",
43 .start = 0x04470000,
44 .end = 0x04470017,
45 .flags = IORESOURCE_MEM,
46 },
47 [1] = {
48 .start = evt2irq(0xe00),
49 .end = evt2irq(0xe60),
50 .flags = IORESOURCE_IRQ,
51 },
52 };
53
54 static struct platform_device iic_device = {
55 .name = "i2c-sh_mobile",
56 .id = 0, /* "i2c0" clock */
57 .num_resources = ARRAY_SIZE(iic_resources),
58 .resource = iic_resources,
59 };
60
61 static struct r8a66597_platdata r8a66597_data = {
62 .on_chip = 1,
63 };
64
65 static struct resource usb_host_resources[] = {
66 [0] = {
67 .start = 0xa4d80000,
68 .end = 0xa4d800ff,
69 .flags = IORESOURCE_MEM,
70 },
71 [1] = {
72 .start = evt2irq(0xa20),
73 .end = evt2irq(0xa20),
74 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
75 },
76 };
77
78 static struct platform_device usb_host_device = {
79 .name = "r8a66597_hcd",
80 .id = -1,
81 .dev = {
82 .dma_mask = NULL,
83 .coherent_dma_mask = 0xffffffff,
84 .platform_data = &r8a66597_data,
85 },
86 .num_resources = ARRAY_SIZE(usb_host_resources),
87 .resource = usb_host_resources,
88 };
89
90 static struct uio_info vpu_platform_data = {
91 .name = "VPU5",
92 .version = "0",
93 .irq = evt2irq(0x980),
94 };
95
96 static struct resource vpu_resources[] = {
97 [0] = {
98 .name = "VPU",
99 .start = 0xfe900000,
100 .end = 0xfe902807,
101 .flags = IORESOURCE_MEM,
102 },
103 [1] = {
104 /* place holder for contiguous memory */
105 },
106 };
107
108 static struct platform_device vpu_device = {
109 .name = "uio_pdrv_genirq",
110 .id = 0,
111 .dev = {
112 .platform_data = &vpu_platform_data,
113 },
114 .resource = vpu_resources,
115 .num_resources = ARRAY_SIZE(vpu_resources),
116 };
117
118 static struct uio_info veu0_platform_data = {
119 .name = "VEU",
120 .version = "0",
121 .irq = evt2irq(0x8c0),
122 };
123
124 static struct resource veu0_resources[] = {
125 [0] = {
126 .name = "VEU(1)",
127 .start = 0xfe920000,
128 .end = 0xfe9200b7,
129 .flags = IORESOURCE_MEM,
130 },
131 [1] = {
132 /* place holder for contiguous memory */
133 },
134 };
135
136 static struct platform_device veu0_device = {
137 .name = "uio_pdrv_genirq",
138 .id = 1,
139 .dev = {
140 .platform_data = &veu0_platform_data,
141 },
142 .resource = veu0_resources,
143 .num_resources = ARRAY_SIZE(veu0_resources),
144 };
145
146 static struct uio_info veu1_platform_data = {
147 .name = "VEU",
148 .version = "0",
149 .irq = evt2irq(0x560),
150 };
151
152 static struct resource veu1_resources[] = {
153 [0] = {
154 .name = "VEU(2)",
155 .start = 0xfe924000,
156 .end = 0xfe9240b7,
157 .flags = IORESOURCE_MEM,
158 },
159 [1] = {
160 /* place holder for contiguous memory */
161 },
162 };
163
164 static struct platform_device veu1_device = {
165 .name = "uio_pdrv_genirq",
166 .id = 2,
167 .dev = {
168 .platform_data = &veu1_platform_data,
169 },
170 .resource = veu1_resources,
171 .num_resources = ARRAY_SIZE(veu1_resources),
172 };
173
174 static struct sh_timer_config cmt_platform_data = {
175 .channel_offset = 0x60,
176 .timer_bit = 5,
177 .clockevent_rating = 125,
178 .clocksource_rating = 200,
179 };
180
181 static struct resource cmt_resources[] = {
182 [0] = {
183 .start = 0x044a0060,
184 .end = 0x044a006b,
185 .flags = IORESOURCE_MEM,
186 },
187 [1] = {
188 .start = evt2irq(0xf00),
189 .flags = IORESOURCE_IRQ,
190 },
191 };
192
193 static struct platform_device cmt_device = {
194 .name = "sh_cmt",
195 .id = 0,
196 .dev = {
197 .platform_data = &cmt_platform_data,
198 },
199 .resource = cmt_resources,
200 .num_resources = ARRAY_SIZE(cmt_resources),
201 };
202
203 static struct sh_timer_config tmu0_platform_data = {
204 .channel_offset = 0x04,
205 .timer_bit = 0,
206 .clockevent_rating = 200,
207 };
208
209 static struct resource tmu0_resources[] = {
210 [0] = {
211 .start = 0xffd80008,
212 .end = 0xffd80013,
213 .flags = IORESOURCE_MEM,
214 },
215 [1] = {
216 .start = 16,
217 .flags = IORESOURCE_IRQ,
218 },
219 };
220
221 static struct platform_device tmu0_device = {
222 .name = "sh_tmu",
223 .id = 0,
224 .dev = {
225 .platform_data = &tmu0_platform_data,
226 },
227 .resource = tmu0_resources,
228 .num_resources = ARRAY_SIZE(tmu0_resources),
229 };
230
231 static struct sh_timer_config tmu1_platform_data = {
232 .channel_offset = 0x10,
233 .timer_bit = 1,
234 .clocksource_rating = 200,
235 };
236
237 static struct resource tmu1_resources[] = {
238 [0] = {
239 .start = 0xffd80014,
240 .end = 0xffd8001f,
241 .flags = IORESOURCE_MEM,
242 },
243 [1] = {
244 .start = evt2irq(0x420),
245 .flags = IORESOURCE_IRQ,
246 },
247 };
248
249 static struct platform_device tmu1_device = {
250 .name = "sh_tmu",
251 .id = 1,
252 .dev = {
253 .platform_data = &tmu1_platform_data,
254 },
255 .resource = tmu1_resources,
256 .num_resources = ARRAY_SIZE(tmu1_resources),
257 };
258
259 static struct sh_timer_config tmu2_platform_data = {
260 .channel_offset = 0x1c,
261 .timer_bit = 2,
262 };
263
264 static struct resource tmu2_resources[] = {
265 [0] = {
266 .start = 0xffd80020,
267 .end = 0xffd8002b,
268 .flags = IORESOURCE_MEM,
269 },
270 [1] = {
271 .start = evt2irq(0x440),
272 .flags = IORESOURCE_IRQ,
273 },
274 };
275
276 static struct platform_device tmu2_device = {
277 .name = "sh_tmu",
278 .id = 2,
279 .dev = {
280 .platform_data = &tmu2_platform_data,
281 },
282 .resource = tmu2_resources,
283 .num_resources = ARRAY_SIZE(tmu2_resources),
284 };
285
286 static struct platform_device *sh7366_devices[] __initdata = {
287 &scif0_device,
288 &cmt_device,
289 &tmu0_device,
290 &tmu1_device,
291 &tmu2_device,
292 &iic_device,
293 &usb_host_device,
294 &vpu_device,
295 &veu0_device,
296 &veu1_device,
297 };
298
sh7366_devices_setup(void)299 static int __init sh7366_devices_setup(void)
300 {
301 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
302 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
303 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
304
305 return platform_add_devices(sh7366_devices,
306 ARRAY_SIZE(sh7366_devices));
307 }
308 arch_initcall(sh7366_devices_setup);
309
310 static struct platform_device *sh7366_early_devices[] __initdata = {
311 &scif0_device,
312 &cmt_device,
313 &tmu0_device,
314 &tmu1_device,
315 &tmu2_device,
316 };
317
plat_early_device_setup(void)318 void __init plat_early_device_setup(void)
319 {
320 early_platform_add_devices(sh7366_early_devices,
321 ARRAY_SIZE(sh7366_early_devices));
322 }
323
324 enum {
325 UNUSED=0,
326 ENABLED,
327 DISABLED,
328
329 /* interrupt sources */
330 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
331 ICB,
332 DMAC0, DMAC1, DMAC2, DMAC3,
333 VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
334 MFI, VPU, USB,
335 MMC_MMC1I, MMC_MMC2I, MMC_MMC3I,
336 DMAC4, DMAC5, DMAC_DADERR,
337 SCIF, SCIFA1, SCIFA2,
338 DENC, MSIOF,
339 FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
340 I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
341 SDHI, CMT, TSIF, SIU,
342 TMU0, TMU1, TMU2,
343 VEU2, LCDC,
344
345 /* interrupt groups */
346
347 DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C,
348 };
349
350 static struct intc_vect vectors[] __initdata = {
351 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
352 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
353 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
354 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
355 INTC_VECT(ICB, 0x700),
356 INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
357 INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
358 INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
359 INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
360 INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980), INTC_VECT(USB, 0xa20),
361 INTC_VECT(MMC_MMC1I, 0xb00), INTC_VECT(MMC_MMC2I, 0xb20),
362 INTC_VECT(MMC_MMC3I, 0xb40),
363 INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
364 INTC_VECT(DMAC_DADERR, 0xbc0),
365 INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIFA1, 0xc20),
366 INTC_VECT(SCIFA2, 0xc40),
367 INTC_VECT(DENC, 0xc60), INTC_VECT(MSIOF, 0xc80),
368 INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
369 INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
370 INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
371 INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
372 INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
373 INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
374 INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
375 INTC_VECT(SIU, 0xf80),
376 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
377 INTC_VECT(TMU2, 0x440),
378 INTC_VECT(VEU2, 0x560), INTC_VECT(LCDC, 0x580),
379 };
380
381 static struct intc_group groups[] __initdata = {
382 INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
383 INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
384 INTC_GROUP(MMC, MMC_MMC1I, MMC_MMC2I, MMC_MMC3I),
385 INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
386 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
387 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
388 INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
389 };
390
391 static struct intc_mask_reg mask_registers[] __initdata = {
392 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
393 { } },
394 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
395 { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
396 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
397 { 0, 0, 0, VPU, 0, 0, 0, MFI } },
398 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
399 { 0, 0, 0, ICB } },
400 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
401 { 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } },
402 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
403 { 0, DMAC_DADERR, DMAC5, DMAC4, DENC, SCIFA2, SCIFA1, SCIF } },
404 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
405 { 0, 0, 0, 0, 0, 0, 0, MSIOF } },
406 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
407 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
408 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
409 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
410 { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } },
411 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
412 { 0, 0, 0, CMT, 0, USB, } },
413 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
414 { 0, MMC_MMC3I, MMC_MMC2I, MMC_MMC1I } },
415 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
416 { 0, 0, 0, 0, 0, 0, 0, TSIF } },
417 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
418 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
419 };
420
421 static struct intc_prio_reg prio_registers[] __initdata = {
422 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
423 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2, LCDC, ICB } },
424 { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
425 { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
426 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
427 { 0xa4080014, 0, 16, 4, /* IPRF */ { 0, DMAC45, USB, CMT } },
428 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIFA1, SCIFA2, DENC } },
429 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF, 0, FLCTL, I2C } },
430 { 0xa4080020, 0, 16, 4, /* IPRI */ { 0, 0, TSIF, } },
431 { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
432 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
433 { 0xa408002c, 0, 16, 4, /* IPRL */ { } },
434 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
435 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
436 };
437
438 static struct intc_sense_reg sense_registers[] __initdata = {
439 { 0xa414001c, 16, 2, /* ICR1 */
440 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
441 };
442
443 static struct intc_mask_reg ack_registers[] __initdata = {
444 { 0xa4140024, 0, 8, /* INTREQ00 */
445 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
446 };
447
448 static struct intc_desc intc_desc __initdata = {
449 .name = "sh7366",
450 .force_enable = ENABLED,
451 .force_disable = DISABLED,
452 .hw = INTC_HW_DESC(vectors, groups, mask_registers,
453 prio_registers, sense_registers, ack_registers),
454 };
455
plat_irq_setup(void)456 void __init plat_irq_setup(void)
457 {
458 register_intc_controller(&intc_desc);
459 }
460
plat_mem_setup(void)461 void __init plat_mem_setup(void)
462 {
463 /* TODO: Register Node 1 */
464 }
465