1 /*
2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
12 * more details.
13 */
14
15 #ifndef _ASM_TILE_TOPOLOGY_H
16 #define _ASM_TILE_TOPOLOGY_H
17
18 #ifdef CONFIG_NUMA
19
20 #include <linux/cpumask.h>
21
22 /* Mappings between logical cpu number and node number. */
23 extern struct cpumask node_2_cpu_mask[];
24 extern char cpu_2_node[];
25
26 /* Returns the number of the node containing CPU 'cpu'. */
cpu_to_node(int cpu)27 static inline int cpu_to_node(int cpu)
28 {
29 return cpu_2_node[cpu];
30 }
31
32 /*
33 * Returns the number of the node containing Node 'node'.
34 * This architecture is flat, so it is a pretty simple function!
35 */
36 #define parent_node(node) (node)
37
38 /* Returns a bitmask of CPUs on Node 'node'. */
cpumask_of_node(int node)39 static inline const struct cpumask *cpumask_of_node(int node)
40 {
41 return &node_2_cpu_mask[node];
42 }
43
44 /* For now, use numa node -1 for global allocation. */
45 #define pcibus_to_node(bus) ((void)(bus), -1)
46
47 /*
48 * TILE architecture has many cores integrated in one processor, so we need
49 * setup bigger balance_interval for both CPU/NODE scheduling domains to
50 * reduce process scheduling costs.
51 */
52
53 /* sched_domains SD_CPU_INIT for TILE architecture */
54 #define SD_CPU_INIT (struct sched_domain) { \
55 .min_interval = 4, \
56 .max_interval = 128, \
57 .busy_factor = 64, \
58 .imbalance_pct = 125, \
59 .cache_nice_tries = 1, \
60 .busy_idx = 2, \
61 .idle_idx = 1, \
62 .newidle_idx = 0, \
63 .wake_idx = 0, \
64 .forkexec_idx = 0, \
65 \
66 .flags = 1*SD_LOAD_BALANCE \
67 | 1*SD_BALANCE_NEWIDLE \
68 | 1*SD_BALANCE_EXEC \
69 | 1*SD_BALANCE_FORK \
70 | 0*SD_BALANCE_WAKE \
71 | 0*SD_WAKE_AFFINE \
72 | 0*SD_SHARE_CPUPOWER \
73 | 0*SD_SHARE_PKG_RESOURCES \
74 | 0*SD_SERIALIZE \
75 , \
76 .last_balance = jiffies, \
77 .balance_interval = 32, \
78 }
79
80 /* By definition, we create nodes based on online memory. */
81 #define node_has_online_mem(nid) 1
82
83 #endif /* CONFIG_NUMA */
84
85 #include <asm-generic/topology.h>
86
87 #ifdef CONFIG_SMP
88 #define topology_physical_package_id(cpu) ((void)(cpu), 0)
89 #define topology_core_id(cpu) (cpu)
90 #define topology_core_cpumask(cpu) ((void)(cpu), cpu_online_mask)
91 #define topology_thread_cpumask(cpu) cpumask_of(cpu)
92
93 /* indicates that pointers to the topology struct cpumask maps are valid */
94 #define arch_provides_topology_pointers yes
95 #endif
96
97 #endif /* _ASM_TILE_TOPOLOGY_H */
98