1 /*
2 * Disk Array driver for Compaq SMART2 Controllers
3 * Copyright 1998 Compaq Computer Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
20 *
21 */
22 #include <linux/module.h>
23 #include <linux/types.h>
24 #include <linux/pci.h>
25 #include <linux/bio.h>
26 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
28 #include <linux/slab.h>
29 #include <linux/delay.h>
30 #include <linux/major.h>
31 #include <linux/fs.h>
32 #include <linux/blkpg.h>
33 #include <linux/timer.h>
34 #include <linux/proc_fs.h>
35 #include <linux/seq_file.h>
36 #include <linux/init.h>
37 #include <linux/hdreg.h>
38 #include <linux/mutex.h>
39 #include <linux/spinlock.h>
40 #include <linux/blkdev.h>
41 #include <linux/genhd.h>
42 #include <linux/scatterlist.h>
43 #include <asm/uaccess.h>
44 #include <asm/io.h>
45
46
47 #define SMART2_DRIVER_VERSION(maj,min,submin) ((maj<<16)|(min<<8)|(submin))
48
49 #define DRIVER_NAME "Compaq SMART2 Driver (v 2.6.0)"
50 #define DRIVER_VERSION SMART2_DRIVER_VERSION(2,6,0)
51
52 /* Embedded module documentation macros - see modules.h */
53 /* Original author Chris Frantz - Compaq Computer Corporation */
54 MODULE_AUTHOR("Compaq Computer Corporation");
55 MODULE_DESCRIPTION("Driver for Compaq Smart2 Array Controllers version 2.6.0");
56 MODULE_LICENSE("GPL");
57
58 #include "cpqarray.h"
59 #include "ida_cmd.h"
60 #include "smart1,2.h"
61 #include "ida_ioctl.h"
62
63 #define READ_AHEAD 128
64 #define NR_CMDS 128 /* This could probably go as high as ~400 */
65
66 #define MAX_CTLR 8
67 #define CTLR_SHIFT 8
68
69 #define CPQARRAY_DMA_MASK 0xFFFFFFFF /* 32 bit DMA */
70
71 static DEFINE_MUTEX(cpqarray_mutex);
72 static int nr_ctlr;
73 static ctlr_info_t *hba[MAX_CTLR];
74
75 static int eisa[8];
76
77 #define NR_PRODUCTS ARRAY_SIZE(products)
78
79 /* board_id = Subsystem Device ID & Vendor ID
80 * product = Marketing Name for the board
81 * access = Address of the struct of function pointers
82 */
83 static struct board_type products[] = {
84 { 0x0040110E, "IDA", &smart1_access },
85 { 0x0140110E, "IDA-2", &smart1_access },
86 { 0x1040110E, "IAES", &smart1_access },
87 { 0x2040110E, "SMART", &smart1_access },
88 { 0x3040110E, "SMART-2/E", &smart2e_access },
89 { 0x40300E11, "SMART-2/P", &smart2_access },
90 { 0x40310E11, "SMART-2SL", &smart2_access },
91 { 0x40320E11, "Smart Array 3200", &smart2_access },
92 { 0x40330E11, "Smart Array 3100ES", &smart2_access },
93 { 0x40340E11, "Smart Array 221", &smart2_access },
94 { 0x40400E11, "Integrated Array", &smart4_access },
95 { 0x40480E11, "Compaq Raid LC2", &smart4_access },
96 { 0x40500E11, "Smart Array 4200", &smart4_access },
97 { 0x40510E11, "Smart Array 4250ES", &smart4_access },
98 { 0x40580E11, "Smart Array 431", &smart4_access },
99 };
100
101 /* define the PCI info for the PCI cards this driver can control */
102 static const struct pci_device_id cpqarray_pci_device_id[] =
103 {
104 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_COMPAQ_42XX,
105 0x0E11, 0x4058, 0, 0, 0}, /* SA431 */
106 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_COMPAQ_42XX,
107 0x0E11, 0x4051, 0, 0, 0}, /* SA4250ES */
108 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_COMPAQ_42XX,
109 0x0E11, 0x4050, 0, 0, 0}, /* SA4200 */
110 { PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C1510,
111 0x0E11, 0x4048, 0, 0, 0}, /* LC2 */
112 { PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C1510,
113 0x0E11, 0x4040, 0, 0, 0}, /* Integrated Array */
114 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
115 0x0E11, 0x4034, 0, 0, 0}, /* SA 221 */
116 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
117 0x0E11, 0x4033, 0, 0, 0}, /* SA 3100ES*/
118 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
119 0x0E11, 0x4032, 0, 0, 0}, /* SA 3200*/
120 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
121 0x0E11, 0x4031, 0, 0, 0}, /* SA 2SL*/
122 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_SMART2P,
123 0x0E11, 0x4030, 0, 0, 0}, /* SA 2P */
124 { 0 }
125 };
126
127 MODULE_DEVICE_TABLE(pci, cpqarray_pci_device_id);
128
129 static struct gendisk *ida_gendisk[MAX_CTLR][NWD];
130
131 /* Debug... */
132 #define DBG(s) do { s } while(0)
133 /* Debug (general info)... */
134 #define DBGINFO(s) do { } while(0)
135 /* Debug Paranoid... */
136 #define DBGP(s) do { } while(0)
137 /* Debug Extra Paranoid... */
138 #define DBGPX(s) do { } while(0)
139
140 static int cpqarray_pci_init(ctlr_info_t *c, struct pci_dev *pdev);
141 static void __iomem *remap_pci_mem(ulong base, ulong size);
142 static int cpqarray_eisa_detect(void);
143 static int pollcomplete(int ctlr);
144 static void getgeometry(int ctlr);
145 static void start_fwbk(int ctlr);
146
147 static cmdlist_t * cmd_alloc(ctlr_info_t *h, int get_from_pool);
148 static void cmd_free(ctlr_info_t *h, cmdlist_t *c, int got_from_pool);
149
150 static void free_hba(int i);
151 static int alloc_cpqarray_hba(void);
152
153 static int sendcmd(
154 __u8 cmd,
155 int ctlr,
156 void *buff,
157 size_t size,
158 unsigned int blk,
159 unsigned int blkcnt,
160 unsigned int log_unit );
161
162 static int ida_unlocked_open(struct block_device *bdev, fmode_t mode);
163 static void ida_release(struct gendisk *disk, fmode_t mode);
164 static int ida_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, unsigned long arg);
165 static int ida_getgeo(struct block_device *bdev, struct hd_geometry *geo);
166 static int ida_ctlr_ioctl(ctlr_info_t *h, int dsk, ida_ioctl_t *io);
167
168 static void do_ida_request(struct request_queue *q);
169 static void start_io(ctlr_info_t *h);
170
171 static inline void addQ(cmdlist_t **Qptr, cmdlist_t *c);
172 static inline cmdlist_t *removeQ(cmdlist_t **Qptr, cmdlist_t *c);
173 static inline void complete_command(cmdlist_t *cmd, int timeout);
174
175 static irqreturn_t do_ida_intr(int irq, void *dev_id);
176 static void ida_timer(unsigned long tdata);
177 static int ida_revalidate(struct gendisk *disk);
178 static int revalidate_allvol(ctlr_info_t *host);
179 static int cpqarray_register_ctlr(int ctlr, struct pci_dev *pdev);
180
181 #ifdef CONFIG_PROC_FS
182 static void ida_procinit(int i);
183 #else
ida_procinit(int i)184 static void ida_procinit(int i) {}
185 #endif
186
get_drv(struct gendisk * disk)187 static inline drv_info_t *get_drv(struct gendisk *disk)
188 {
189 return disk->private_data;
190 }
191
get_host(struct gendisk * disk)192 static inline ctlr_info_t *get_host(struct gendisk *disk)
193 {
194 return disk->queue->queuedata;
195 }
196
197
198 static const struct block_device_operations ida_fops = {
199 .owner = THIS_MODULE,
200 .open = ida_unlocked_open,
201 .release = ida_release,
202 .ioctl = ida_ioctl,
203 .getgeo = ida_getgeo,
204 .revalidate_disk= ida_revalidate,
205 };
206
207
208 #ifdef CONFIG_PROC_FS
209
210 static struct proc_dir_entry *proc_array;
211 static const struct file_operations ida_proc_fops;
212
213 /*
214 * Get us a file in /proc/array that says something about each controller.
215 * Create /proc/array if it doesn't exist yet.
216 */
ida_procinit(int i)217 static void __init ida_procinit(int i)
218 {
219 if (proc_array == NULL) {
220 proc_array = proc_mkdir("driver/cpqarray", NULL);
221 if (!proc_array) return;
222 }
223
224 proc_create_data(hba[i]->devname, 0, proc_array, &ida_proc_fops, hba[i]);
225 }
226
227 /*
228 * Report information about this controller.
229 */
ida_proc_show(struct seq_file * m,void * v)230 static int ida_proc_show(struct seq_file *m, void *v)
231 {
232 int i, ctlr;
233 ctlr_info_t *h = (ctlr_info_t*)m->private;
234 drv_info_t *drv;
235 #ifdef CPQ_PROC_PRINT_QUEUES
236 cmdlist_t *c;
237 unsigned long flags;
238 #endif
239
240 ctlr = h->ctlr;
241 seq_printf(m, "%s: Compaq %s Controller\n"
242 " Board ID: 0x%08lx\n"
243 " Firmware Revision: %c%c%c%c\n"
244 " Controller Sig: 0x%08lx\n"
245 " Memory Address: 0x%08lx\n"
246 " I/O Port: 0x%04x\n"
247 " IRQ: %d\n"
248 " Logical drives: %d\n"
249 " Physical drives: %d\n\n"
250 " Current Q depth: %d\n"
251 " Max Q depth since init: %d\n\n",
252 h->devname,
253 h->product_name,
254 (unsigned long)h->board_id,
255 h->firm_rev[0], h->firm_rev[1], h->firm_rev[2], h->firm_rev[3],
256 (unsigned long)h->ctlr_sig, (unsigned long)h->vaddr,
257 (unsigned int) h->io_mem_addr, (unsigned int)h->intr,
258 h->log_drives, h->phys_drives,
259 h->Qdepth, h->maxQsinceinit);
260
261 seq_puts(m, "Logical Drive Info:\n");
262
263 for(i=0; i<h->log_drives; i++) {
264 drv = &h->drv[i];
265 seq_printf(m, "ida/c%dd%d: blksz=%d nr_blks=%d\n",
266 ctlr, i, drv->blk_size, drv->nr_blks);
267 }
268
269 #ifdef CPQ_PROC_PRINT_QUEUES
270 spin_lock_irqsave(IDA_LOCK(h->ctlr), flags);
271 seq_puts(m, "\nCurrent Queues:\n");
272
273 c = h->reqQ;
274 seq_printf(m, "reqQ = %p", c);
275 if (c) c=c->next;
276 while(c && c != h->reqQ) {
277 seq_printf(m, "->%p", c);
278 c=c->next;
279 }
280
281 c = h->cmpQ;
282 seq_printf(m, "\ncmpQ = %p", c);
283 if (c) c=c->next;
284 while(c && c != h->cmpQ) {
285 seq_printf(m, "->%p", c);
286 c=c->next;
287 }
288
289 seq_putc(m, '\n');
290 spin_unlock_irqrestore(IDA_LOCK(h->ctlr), flags);
291 #endif
292 seq_printf(m, "nr_allocs = %d\nnr_frees = %d\n",
293 h->nr_allocs, h->nr_frees);
294 return 0;
295 }
296
ida_proc_open(struct inode * inode,struct file * file)297 static int ida_proc_open(struct inode *inode, struct file *file)
298 {
299 return single_open(file, ida_proc_show, PDE_DATA(inode));
300 }
301
302 static const struct file_operations ida_proc_fops = {
303 .owner = THIS_MODULE,
304 .open = ida_proc_open,
305 .read = seq_read,
306 .llseek = seq_lseek,
307 .release = single_release,
308 };
309 #endif /* CONFIG_PROC_FS */
310
311 module_param_array(eisa, int, NULL, 0);
312
release_io_mem(ctlr_info_t * c)313 static void release_io_mem(ctlr_info_t *c)
314 {
315 /* if IO mem was not protected do nothing */
316 if( c->io_mem_addr == 0)
317 return;
318 release_region(c->io_mem_addr, c->io_mem_length);
319 c->io_mem_addr = 0;
320 c->io_mem_length = 0;
321 }
322
cpqarray_remove_one(int i)323 static void cpqarray_remove_one(int i)
324 {
325 int j;
326 char buff[4];
327
328 /* sendcmd will turn off interrupt, and send the flush...
329 * To write all data in the battery backed cache to disks
330 * no data returned, but don't want to send NULL to sendcmd */
331 if( sendcmd(FLUSH_CACHE, i, buff, 4, 0, 0, 0))
332 {
333 printk(KERN_WARNING "Unable to flush cache on controller %d\n",
334 i);
335 }
336 free_irq(hba[i]->intr, hba[i]);
337 iounmap(hba[i]->vaddr);
338 unregister_blkdev(COMPAQ_SMART2_MAJOR+i, hba[i]->devname);
339 del_timer(&hba[i]->timer);
340 remove_proc_entry(hba[i]->devname, proc_array);
341 pci_free_consistent(hba[i]->pci_dev,
342 NR_CMDS * sizeof(cmdlist_t), (hba[i]->cmd_pool),
343 hba[i]->cmd_pool_dhandle);
344 kfree(hba[i]->cmd_pool_bits);
345 for(j = 0; j < NWD; j++) {
346 if (ida_gendisk[i][j]->flags & GENHD_FL_UP)
347 del_gendisk(ida_gendisk[i][j]);
348 put_disk(ida_gendisk[i][j]);
349 }
350 blk_cleanup_queue(hba[i]->queue);
351 release_io_mem(hba[i]);
352 free_hba(i);
353 }
354
cpqarray_remove_one_pci(struct pci_dev * pdev)355 static void cpqarray_remove_one_pci(struct pci_dev *pdev)
356 {
357 int i;
358 ctlr_info_t *tmp_ptr;
359
360 if (pci_get_drvdata(pdev) == NULL) {
361 printk( KERN_ERR "cpqarray: Unable to remove device \n");
362 return;
363 }
364
365 tmp_ptr = pci_get_drvdata(pdev);
366 i = tmp_ptr->ctlr;
367 if (hba[i] == NULL) {
368 printk(KERN_ERR "cpqarray: controller %d appears to have"
369 "already been removed \n", i);
370 return;
371 }
372 pci_set_drvdata(pdev, NULL);
373
374 cpqarray_remove_one(i);
375 }
376
377 /* removing an instance that was not removed automatically..
378 * must be an eisa card.
379 */
cpqarray_remove_one_eisa(int i)380 static void cpqarray_remove_one_eisa(int i)
381 {
382 if (hba[i] == NULL) {
383 printk(KERN_ERR "cpqarray: controller %d appears to have"
384 "already been removed \n", i);
385 return;
386 }
387 cpqarray_remove_one(i);
388 }
389
390 /* pdev is NULL for eisa */
cpqarray_register_ctlr(int i,struct pci_dev * pdev)391 static int cpqarray_register_ctlr(int i, struct pci_dev *pdev)
392 {
393 struct request_queue *q;
394 int j;
395
396 /*
397 * register block devices
398 * Find disks and fill in structs
399 * Get an interrupt, set the Q depth and get into /proc
400 */
401
402 /* If this successful it should insure that we are the only */
403 /* instance of the driver */
404 if (register_blkdev(COMPAQ_SMART2_MAJOR+i, hba[i]->devname)) {
405 goto Enomem4;
406 }
407 hba[i]->access.set_intr_mask(hba[i], 0);
408 if (request_irq(hba[i]->intr, do_ida_intr,
409 IRQF_DISABLED|IRQF_SHARED, hba[i]->devname, hba[i]))
410 {
411 printk(KERN_ERR "cpqarray: Unable to get irq %d for %s\n",
412 hba[i]->intr, hba[i]->devname);
413 goto Enomem3;
414 }
415
416 for (j=0; j<NWD; j++) {
417 ida_gendisk[i][j] = alloc_disk(1 << NWD_SHIFT);
418 if (!ida_gendisk[i][j])
419 goto Enomem2;
420 }
421
422 hba[i]->cmd_pool = pci_alloc_consistent(
423 hba[i]->pci_dev, NR_CMDS * sizeof(cmdlist_t),
424 &(hba[i]->cmd_pool_dhandle));
425 hba[i]->cmd_pool_bits = kcalloc(
426 DIV_ROUND_UP(NR_CMDS, BITS_PER_LONG), sizeof(unsigned long),
427 GFP_KERNEL);
428
429 if (!hba[i]->cmd_pool_bits || !hba[i]->cmd_pool)
430 goto Enomem1;
431
432 memset(hba[i]->cmd_pool, 0, NR_CMDS * sizeof(cmdlist_t));
433 printk(KERN_INFO "cpqarray: Finding drives on %s",
434 hba[i]->devname);
435
436 spin_lock_init(&hba[i]->lock);
437 q = blk_init_queue(do_ida_request, &hba[i]->lock);
438 if (!q)
439 goto Enomem1;
440
441 hba[i]->queue = q;
442 q->queuedata = hba[i];
443
444 getgeometry(i);
445 start_fwbk(i);
446
447 ida_procinit(i);
448
449 if (pdev)
450 blk_queue_bounce_limit(q, hba[i]->pci_dev->dma_mask);
451
452 /* This is a hardware imposed limit. */
453 blk_queue_max_segments(q, SG_MAX);
454
455 init_timer(&hba[i]->timer);
456 hba[i]->timer.expires = jiffies + IDA_TIMER;
457 hba[i]->timer.data = (unsigned long)hba[i];
458 hba[i]->timer.function = ida_timer;
459 add_timer(&hba[i]->timer);
460
461 /* Enable IRQ now that spinlock and rate limit timer are set up */
462 hba[i]->access.set_intr_mask(hba[i], FIFO_NOT_EMPTY);
463
464 for(j=0; j<NWD; j++) {
465 struct gendisk *disk = ida_gendisk[i][j];
466 drv_info_t *drv = &hba[i]->drv[j];
467 sprintf(disk->disk_name, "ida/c%dd%d", i, j);
468 disk->major = COMPAQ_SMART2_MAJOR + i;
469 disk->first_minor = j<<NWD_SHIFT;
470 disk->fops = &ida_fops;
471 if (j && !drv->nr_blks)
472 continue;
473 blk_queue_logical_block_size(hba[i]->queue, drv->blk_size);
474 set_capacity(disk, drv->nr_blks);
475 disk->queue = hba[i]->queue;
476 disk->private_data = drv;
477 add_disk(disk);
478 }
479
480 /* done ! */
481 return(i);
482
483 Enomem1:
484 nr_ctlr = i;
485 kfree(hba[i]->cmd_pool_bits);
486 if (hba[i]->cmd_pool)
487 pci_free_consistent(hba[i]->pci_dev, NR_CMDS*sizeof(cmdlist_t),
488 hba[i]->cmd_pool, hba[i]->cmd_pool_dhandle);
489 Enomem2:
490 while (j--) {
491 put_disk(ida_gendisk[i][j]);
492 ida_gendisk[i][j] = NULL;
493 }
494 free_irq(hba[i]->intr, hba[i]);
495 Enomem3:
496 unregister_blkdev(COMPAQ_SMART2_MAJOR+i, hba[i]->devname);
497 Enomem4:
498 if (pdev)
499 pci_set_drvdata(pdev, NULL);
500 release_io_mem(hba[i]);
501 free_hba(i);
502
503 printk( KERN_ERR "cpqarray: out of memory");
504
505 return -1;
506 }
507
cpqarray_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)508 static int cpqarray_init_one(struct pci_dev *pdev,
509 const struct pci_device_id *ent)
510 {
511 int i;
512
513 printk(KERN_DEBUG "cpqarray: Device 0x%x has been found at"
514 " bus %d dev %d func %d\n",
515 pdev->device, pdev->bus->number, PCI_SLOT(pdev->devfn),
516 PCI_FUNC(pdev->devfn));
517 i = alloc_cpqarray_hba();
518 if( i < 0 )
519 return (-1);
520 memset(hba[i], 0, sizeof(ctlr_info_t));
521 sprintf(hba[i]->devname, "ida%d", i);
522 hba[i]->ctlr = i;
523 /* Initialize the pdev driver private data */
524 pci_set_drvdata(pdev, hba[i]);
525
526 if (cpqarray_pci_init(hba[i], pdev) != 0) {
527 pci_set_drvdata(pdev, NULL);
528 release_io_mem(hba[i]);
529 free_hba(i);
530 return -1;
531 }
532
533 return (cpqarray_register_ctlr(i, pdev));
534 }
535
536 static struct pci_driver cpqarray_pci_driver = {
537 .name = "cpqarray",
538 .probe = cpqarray_init_one,
539 .remove = cpqarray_remove_one_pci,
540 .id_table = cpqarray_pci_device_id,
541 };
542
543 /*
544 * This is it. Find all the controllers and register them.
545 * returns the number of block devices registered.
546 */
cpqarray_init(void)547 static int __init cpqarray_init(void)
548 {
549 int num_cntlrs_reg = 0;
550 int i;
551 int rc = 0;
552
553 /* detect controllers */
554 printk(DRIVER_NAME "\n");
555
556 rc = pci_register_driver(&cpqarray_pci_driver);
557 if (rc)
558 return rc;
559 cpqarray_eisa_detect();
560
561 for (i=0; i < MAX_CTLR; i++) {
562 if (hba[i] != NULL)
563 num_cntlrs_reg++;
564 }
565
566 if (num_cntlrs_reg)
567 return 0;
568 else {
569 pci_unregister_driver(&cpqarray_pci_driver);
570 return -ENODEV;
571 }
572 }
573
574 /* Function to find the first free pointer into our hba[] array */
575 /* Returns -1 if no free entries are left. */
alloc_cpqarray_hba(void)576 static int alloc_cpqarray_hba(void)
577 {
578 int i;
579
580 for(i=0; i< MAX_CTLR; i++) {
581 if (hba[i] == NULL) {
582 hba[i] = kmalloc(sizeof(ctlr_info_t), GFP_KERNEL);
583 if(hba[i]==NULL) {
584 printk(KERN_ERR "cpqarray: out of memory.\n");
585 return (-1);
586 }
587 return (i);
588 }
589 }
590 printk(KERN_WARNING "cpqarray: This driver supports a maximum"
591 " of 8 controllers.\n");
592 return(-1);
593 }
594
free_hba(int i)595 static void free_hba(int i)
596 {
597 kfree(hba[i]);
598 hba[i]=NULL;
599 }
600
601 /*
602 * Find the IO address of the controller, its IRQ and so forth. Fill
603 * in some basic stuff into the ctlr_info_t structure.
604 */
cpqarray_pci_init(ctlr_info_t * c,struct pci_dev * pdev)605 static int cpqarray_pci_init(ctlr_info_t *c, struct pci_dev *pdev)
606 {
607 ushort vendor_id, device_id, command;
608 unchar cache_line_size, latency_timer;
609 unchar irq, revision;
610 unsigned long addr[6];
611 __u32 board_id;
612
613 int i;
614
615 c->pci_dev = pdev;
616 pci_set_master(pdev);
617 if (pci_enable_device(pdev)) {
618 printk(KERN_ERR "cpqarray: Unable to Enable PCI device\n");
619 return -1;
620 }
621 vendor_id = pdev->vendor;
622 device_id = pdev->device;
623 revision = pdev->revision;
624 irq = pdev->irq;
625
626 for(i=0; i<6; i++)
627 addr[i] = pci_resource_start(pdev, i);
628
629 if (pci_set_dma_mask(pdev, CPQARRAY_DMA_MASK) != 0)
630 {
631 printk(KERN_ERR "cpqarray: Unable to set DMA mask\n");
632 return -1;
633 }
634
635 pci_read_config_word(pdev, PCI_COMMAND, &command);
636 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line_size);
637 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency_timer);
638
639 pci_read_config_dword(pdev, 0x2c, &board_id);
640
641 /* check to see if controller has been disabled */
642 if(!(command & 0x02)) {
643 printk(KERN_WARNING
644 "cpqarray: controller appears to be disabled\n");
645 return(-1);
646 }
647
648 DBGINFO(
649 printk("vendor_id = %x\n", vendor_id);
650 printk("device_id = %x\n", device_id);
651 printk("command = %x\n", command);
652 for(i=0; i<6; i++)
653 printk("addr[%d] = %lx\n", i, addr[i]);
654 printk("revision = %x\n", revision);
655 printk("irq = %x\n", irq);
656 printk("cache_line_size = %x\n", cache_line_size);
657 printk("latency_timer = %x\n", latency_timer);
658 printk("board_id = %x\n", board_id);
659 );
660
661 c->intr = irq;
662
663 for(i=0; i<6; i++) {
664 if (pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE_IO)
665 { /* IO space */
666 c->io_mem_addr = addr[i];
667 c->io_mem_length = pci_resource_end(pdev, i)
668 - pci_resource_start(pdev, i) + 1;
669 if(!request_region( c->io_mem_addr, c->io_mem_length,
670 "cpqarray"))
671 {
672 printk( KERN_WARNING "cpqarray I/O memory range already in use addr %lx length = %ld\n", c->io_mem_addr, c->io_mem_length);
673 c->io_mem_addr = 0;
674 c->io_mem_length = 0;
675 }
676 break;
677 }
678 }
679
680 c->paddr = 0;
681 for(i=0; i<6; i++)
682 if (!(pci_resource_flags(pdev, i) &
683 PCI_BASE_ADDRESS_SPACE_IO)) {
684 c->paddr = pci_resource_start (pdev, i);
685 break;
686 }
687 if (!c->paddr)
688 return -1;
689 c->vaddr = remap_pci_mem(c->paddr, 128);
690 if (!c->vaddr)
691 return -1;
692 c->board_id = board_id;
693
694 for(i=0; i<NR_PRODUCTS; i++) {
695 if (board_id == products[i].board_id) {
696 c->product_name = products[i].product_name;
697 c->access = *(products[i].access);
698 break;
699 }
700 }
701 if (i == NR_PRODUCTS) {
702 printk(KERN_WARNING "cpqarray: Sorry, I don't know how"
703 " to access the SMART Array controller %08lx\n",
704 (unsigned long)board_id);
705 return -1;
706 }
707
708 return 0;
709 }
710
711 /*
712 * Map (physical) PCI mem into (virtual) kernel space
713 */
remap_pci_mem(ulong base,ulong size)714 static void __iomem *remap_pci_mem(ulong base, ulong size)
715 {
716 ulong page_base = ((ulong) base) & PAGE_MASK;
717 ulong page_offs = ((ulong) base) - page_base;
718 void __iomem *page_remapped = ioremap(page_base, page_offs+size);
719
720 return (page_remapped ? (page_remapped + page_offs) : NULL);
721 }
722
723 #ifndef MODULE
724 /*
725 * Config string is a comma separated set of i/o addresses of EISA cards.
726 */
cpqarray_setup(char * str)727 static int cpqarray_setup(char *str)
728 {
729 int i, ints[9];
730
731 (void)get_options(str, ARRAY_SIZE(ints), ints);
732
733 for(i=0; i<ints[0] && i<8; i++)
734 eisa[i] = ints[i+1];
735 return 1;
736 }
737
738 __setup("smart2=", cpqarray_setup);
739
740 #endif
741
742 /*
743 * Find an EISA controller's signature. Set up an hba if we find it.
744 */
cpqarray_eisa_detect(void)745 static int cpqarray_eisa_detect(void)
746 {
747 int i=0, j;
748 __u32 board_id;
749 int intr;
750 int ctlr;
751 int num_ctlr = 0;
752
753 while(i<8 && eisa[i]) {
754 ctlr = alloc_cpqarray_hba();
755 if(ctlr == -1)
756 break;
757 board_id = inl(eisa[i]+0xC80);
758 for(j=0; j < NR_PRODUCTS; j++)
759 if (board_id == products[j].board_id)
760 break;
761
762 if (j == NR_PRODUCTS) {
763 printk(KERN_WARNING "cpqarray: Sorry, I don't know how"
764 " to access the SMART Array controller %08lx\n", (unsigned long)board_id);
765 continue;
766 }
767
768 memset(hba[ctlr], 0, sizeof(ctlr_info_t));
769 hba[ctlr]->io_mem_addr = eisa[i];
770 hba[ctlr]->io_mem_length = 0x7FF;
771 if(!request_region(hba[ctlr]->io_mem_addr,
772 hba[ctlr]->io_mem_length,
773 "cpqarray"))
774 {
775 printk(KERN_WARNING "cpqarray: I/O range already in "
776 "use addr = %lx length = %ld\n",
777 hba[ctlr]->io_mem_addr,
778 hba[ctlr]->io_mem_length);
779 free_hba(ctlr);
780 continue;
781 }
782
783 /*
784 * Read the config register to find our interrupt
785 */
786 intr = inb(eisa[i]+0xCC0) >> 4;
787 if (intr & 1) intr = 11;
788 else if (intr & 2) intr = 10;
789 else if (intr & 4) intr = 14;
790 else if (intr & 8) intr = 15;
791
792 hba[ctlr]->intr = intr;
793 sprintf(hba[ctlr]->devname, "ida%d", nr_ctlr);
794 hba[ctlr]->product_name = products[j].product_name;
795 hba[ctlr]->access = *(products[j].access);
796 hba[ctlr]->ctlr = ctlr;
797 hba[ctlr]->board_id = board_id;
798 hba[ctlr]->pci_dev = NULL; /* not PCI */
799
800 DBGINFO(
801 printk("i = %d, j = %d\n", i, j);
802 printk("irq = %x\n", intr);
803 printk("product name = %s\n", products[j].product_name);
804 printk("board_id = %x\n", board_id);
805 );
806
807 num_ctlr++;
808 i++;
809
810 if (cpqarray_register_ctlr(ctlr, NULL) == -1)
811 printk(KERN_WARNING
812 "cpqarray: Can't register EISA controller %d\n",
813 ctlr);
814
815 }
816
817 return num_ctlr;
818 }
819
820 /*
821 * Open. Make sure the device is really there.
822 */
ida_open(struct block_device * bdev,fmode_t mode)823 static int ida_open(struct block_device *bdev, fmode_t mode)
824 {
825 drv_info_t *drv = get_drv(bdev->bd_disk);
826 ctlr_info_t *host = get_host(bdev->bd_disk);
827
828 DBGINFO(printk("ida_open %s\n", bdev->bd_disk->disk_name));
829 /*
830 * Root is allowed to open raw volume zero even if it's not configured
831 * so array config can still work. I don't think I really like this,
832 * but I'm already using way to many device nodes to claim another one
833 * for "raw controller".
834 */
835 if (!drv->nr_blks) {
836 if (!capable(CAP_SYS_RAWIO))
837 return -ENXIO;
838 if (!capable(CAP_SYS_ADMIN) && drv != host->drv)
839 return -ENXIO;
840 }
841 host->usage_count++;
842 return 0;
843 }
844
ida_unlocked_open(struct block_device * bdev,fmode_t mode)845 static int ida_unlocked_open(struct block_device *bdev, fmode_t mode)
846 {
847 int ret;
848
849 mutex_lock(&cpqarray_mutex);
850 ret = ida_open(bdev, mode);
851 mutex_unlock(&cpqarray_mutex);
852
853 return ret;
854 }
855
856 /*
857 * Close. Sync first.
858 */
ida_release(struct gendisk * disk,fmode_t mode)859 static void ida_release(struct gendisk *disk, fmode_t mode)
860 {
861 ctlr_info_t *host;
862
863 mutex_lock(&cpqarray_mutex);
864 host = get_host(disk);
865 host->usage_count--;
866 mutex_unlock(&cpqarray_mutex);
867 }
868
869 /*
870 * Enqueuing and dequeuing functions for cmdlists.
871 */
addQ(cmdlist_t ** Qptr,cmdlist_t * c)872 static inline void addQ(cmdlist_t **Qptr, cmdlist_t *c)
873 {
874 if (*Qptr == NULL) {
875 *Qptr = c;
876 c->next = c->prev = c;
877 } else {
878 c->prev = (*Qptr)->prev;
879 c->next = (*Qptr);
880 (*Qptr)->prev->next = c;
881 (*Qptr)->prev = c;
882 }
883 }
884
removeQ(cmdlist_t ** Qptr,cmdlist_t * c)885 static inline cmdlist_t *removeQ(cmdlist_t **Qptr, cmdlist_t *c)
886 {
887 if (c && c->next != c) {
888 if (*Qptr == c) *Qptr = c->next;
889 c->prev->next = c->next;
890 c->next->prev = c->prev;
891 } else {
892 *Qptr = NULL;
893 }
894 return c;
895 }
896
897 /*
898 * Get a request and submit it to the controller.
899 * This routine needs to grab all the requests it possibly can from the
900 * req Q and submit them. Interrupts are off (and need to be off) when you
901 * are in here (either via the dummy do_ida_request functions or by being
902 * called from the interrupt handler
903 */
do_ida_request(struct request_queue * q)904 static void do_ida_request(struct request_queue *q)
905 {
906 ctlr_info_t *h = q->queuedata;
907 cmdlist_t *c;
908 struct request *creq;
909 struct scatterlist tmp_sg[SG_MAX];
910 int i, dir, seg;
911
912 queue_next:
913 creq = blk_peek_request(q);
914 if (!creq)
915 goto startio;
916
917 BUG_ON(creq->nr_phys_segments > SG_MAX);
918
919 if ((c = cmd_alloc(h,1)) == NULL)
920 goto startio;
921
922 blk_start_request(creq);
923
924 c->ctlr = h->ctlr;
925 c->hdr.unit = (drv_info_t *)(creq->rq_disk->private_data) - h->drv;
926 c->hdr.size = sizeof(rblk_t) >> 2;
927 c->size += sizeof(rblk_t);
928
929 c->req.hdr.blk = blk_rq_pos(creq);
930 c->rq = creq;
931 DBGPX(
932 printk("sector=%d, nr_sectors=%u\n",
933 blk_rq_pos(creq), blk_rq_sectors(creq));
934 );
935 sg_init_table(tmp_sg, SG_MAX);
936 seg = blk_rq_map_sg(q, creq, tmp_sg);
937
938 /* Now do all the DMA Mappings */
939 if (rq_data_dir(creq) == READ)
940 dir = PCI_DMA_FROMDEVICE;
941 else
942 dir = PCI_DMA_TODEVICE;
943 for( i=0; i < seg; i++)
944 {
945 c->req.sg[i].size = tmp_sg[i].length;
946 c->req.sg[i].addr = (__u32) pci_map_page(h->pci_dev,
947 sg_page(&tmp_sg[i]),
948 tmp_sg[i].offset,
949 tmp_sg[i].length, dir);
950 }
951 DBGPX( printk("Submitting %u sectors in %d segments\n", blk_rq_sectors(creq), seg); );
952 c->req.hdr.sg_cnt = seg;
953 c->req.hdr.blk_cnt = blk_rq_sectors(creq);
954 c->req.hdr.cmd = (rq_data_dir(creq) == READ) ? IDA_READ : IDA_WRITE;
955 c->type = CMD_RWREQ;
956
957 /* Put the request on the tail of the request queue */
958 addQ(&h->reqQ, c);
959 h->Qdepth++;
960 if (h->Qdepth > h->maxQsinceinit)
961 h->maxQsinceinit = h->Qdepth;
962
963 goto queue_next;
964
965 startio:
966 start_io(h);
967 }
968
969 /*
970 * start_io submits everything on a controller's request queue
971 * and moves it to the completion queue.
972 *
973 * Interrupts had better be off if you're in here
974 */
start_io(ctlr_info_t * h)975 static void start_io(ctlr_info_t *h)
976 {
977 cmdlist_t *c;
978
979 while((c = h->reqQ) != NULL) {
980 /* Can't do anything if we're busy */
981 if (h->access.fifo_full(h) == 0)
982 return;
983
984 /* Get the first entry from the request Q */
985 removeQ(&h->reqQ, c);
986 h->Qdepth--;
987
988 /* Tell the controller to do our bidding */
989 h->access.submit_command(h, c);
990
991 /* Get onto the completion Q */
992 addQ(&h->cmpQ, c);
993 }
994 }
995
996 /*
997 * Mark all buffers that cmd was responsible for
998 */
complete_command(cmdlist_t * cmd,int timeout)999 static inline void complete_command(cmdlist_t *cmd, int timeout)
1000 {
1001 struct request *rq = cmd->rq;
1002 int error = 0;
1003 int i, ddir;
1004
1005 if (cmd->req.hdr.rcode & RCODE_NONFATAL &&
1006 (hba[cmd->ctlr]->misc_tflags & MISC_NONFATAL_WARN) == 0) {
1007 printk(KERN_NOTICE "Non Fatal error on ida/c%dd%d\n",
1008 cmd->ctlr, cmd->hdr.unit);
1009 hba[cmd->ctlr]->misc_tflags |= MISC_NONFATAL_WARN;
1010 }
1011 if (cmd->req.hdr.rcode & RCODE_FATAL) {
1012 printk(KERN_WARNING "Fatal error on ida/c%dd%d\n",
1013 cmd->ctlr, cmd->hdr.unit);
1014 error = -EIO;
1015 }
1016 if (cmd->req.hdr.rcode & RCODE_INVREQ) {
1017 printk(KERN_WARNING "Invalid request on ida/c%dd%d = (cmd=%x sect=%d cnt=%d sg=%d ret=%x)\n",
1018 cmd->ctlr, cmd->hdr.unit, cmd->req.hdr.cmd,
1019 cmd->req.hdr.blk, cmd->req.hdr.blk_cnt,
1020 cmd->req.hdr.sg_cnt, cmd->req.hdr.rcode);
1021 error = -EIO;
1022 }
1023 if (timeout)
1024 error = -EIO;
1025 /* unmap the DMA mapping for all the scatter gather elements */
1026 if (cmd->req.hdr.cmd == IDA_READ)
1027 ddir = PCI_DMA_FROMDEVICE;
1028 else
1029 ddir = PCI_DMA_TODEVICE;
1030 for(i=0; i<cmd->req.hdr.sg_cnt; i++)
1031 pci_unmap_page(hba[cmd->ctlr]->pci_dev, cmd->req.sg[i].addr,
1032 cmd->req.sg[i].size, ddir);
1033
1034 DBGPX(printk("Done with %p\n", rq););
1035 __blk_end_request_all(rq, error);
1036 }
1037
1038 /*
1039 * The controller will interrupt us upon completion of commands.
1040 * Find the command on the completion queue, remove it, tell the OS and
1041 * try to queue up more IO
1042 */
do_ida_intr(int irq,void * dev_id)1043 static irqreturn_t do_ida_intr(int irq, void *dev_id)
1044 {
1045 ctlr_info_t *h = dev_id;
1046 cmdlist_t *c;
1047 unsigned long istat;
1048 unsigned long flags;
1049 __u32 a,a1;
1050
1051 istat = h->access.intr_pending(h);
1052 /* Is this interrupt for us? */
1053 if (istat == 0)
1054 return IRQ_NONE;
1055
1056 /*
1057 * If there are completed commands in the completion queue,
1058 * we had better do something about it.
1059 */
1060 spin_lock_irqsave(IDA_LOCK(h->ctlr), flags);
1061 if (istat & FIFO_NOT_EMPTY) {
1062 while((a = h->access.command_completed(h))) {
1063 a1 = a; a &= ~3;
1064 if ((c = h->cmpQ) == NULL)
1065 {
1066 printk(KERN_WARNING "cpqarray: Completion of %08lx ignored\n", (unsigned long)a1);
1067 continue;
1068 }
1069 while(c->busaddr != a) {
1070 c = c->next;
1071 if (c == h->cmpQ)
1072 break;
1073 }
1074 /*
1075 * If we've found the command, take it off the
1076 * completion Q and free it
1077 */
1078 if (c->busaddr == a) {
1079 removeQ(&h->cmpQ, c);
1080 /* Check for invalid command.
1081 * Controller returns command error,
1082 * But rcode = 0.
1083 */
1084
1085 if((a1 & 0x03) && (c->req.hdr.rcode == 0))
1086 {
1087 c->req.hdr.rcode = RCODE_INVREQ;
1088 }
1089 if (c->type == CMD_RWREQ) {
1090 complete_command(c, 0);
1091 cmd_free(h, c, 1);
1092 } else if (c->type == CMD_IOCTL_PEND) {
1093 c->type = CMD_IOCTL_DONE;
1094 }
1095 continue;
1096 }
1097 }
1098 }
1099
1100 /*
1101 * See if we can queue up some more IO
1102 */
1103 do_ida_request(h->queue);
1104 spin_unlock_irqrestore(IDA_LOCK(h->ctlr), flags);
1105 return IRQ_HANDLED;
1106 }
1107
1108 /*
1109 * This timer was for timing out requests that haven't happened after
1110 * IDA_TIMEOUT. That wasn't such a good idea. This timer is used to
1111 * reset a flags structure so we don't flood the user with
1112 * "Non-Fatal error" messages.
1113 */
ida_timer(unsigned long tdata)1114 static void ida_timer(unsigned long tdata)
1115 {
1116 ctlr_info_t *h = (ctlr_info_t*)tdata;
1117
1118 h->timer.expires = jiffies + IDA_TIMER;
1119 add_timer(&h->timer);
1120 h->misc_tflags = 0;
1121 }
1122
ida_getgeo(struct block_device * bdev,struct hd_geometry * geo)1123 static int ida_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1124 {
1125 drv_info_t *drv = get_drv(bdev->bd_disk);
1126
1127 if (drv->cylinders) {
1128 geo->heads = drv->heads;
1129 geo->sectors = drv->sectors;
1130 geo->cylinders = drv->cylinders;
1131 } else {
1132 geo->heads = 0xff;
1133 geo->sectors = 0x3f;
1134 geo->cylinders = drv->nr_blks / (0xff*0x3f);
1135 }
1136
1137 return 0;
1138 }
1139
1140 /*
1141 * ida_ioctl does some miscellaneous stuff like reporting drive geometry,
1142 * setting readahead and submitting commands from userspace to the controller.
1143 */
ida_locked_ioctl(struct block_device * bdev,fmode_t mode,unsigned int cmd,unsigned long arg)1144 static int ida_locked_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd, unsigned long arg)
1145 {
1146 drv_info_t *drv = get_drv(bdev->bd_disk);
1147 ctlr_info_t *host = get_host(bdev->bd_disk);
1148 int error;
1149 ida_ioctl_t __user *io = (ida_ioctl_t __user *)arg;
1150 ida_ioctl_t *my_io;
1151
1152 switch(cmd) {
1153 case IDAGETDRVINFO:
1154 if (copy_to_user(&io->c.drv, drv, sizeof(drv_info_t)))
1155 return -EFAULT;
1156 return 0;
1157 case IDAPASSTHRU:
1158 if (!capable(CAP_SYS_RAWIO))
1159 return -EPERM;
1160 my_io = kmalloc(sizeof(ida_ioctl_t), GFP_KERNEL);
1161 if (!my_io)
1162 return -ENOMEM;
1163 error = -EFAULT;
1164 if (copy_from_user(my_io, io, sizeof(*my_io)))
1165 goto out_passthru;
1166 error = ida_ctlr_ioctl(host, drv - host->drv, my_io);
1167 if (error)
1168 goto out_passthru;
1169 error = -EFAULT;
1170 if (copy_to_user(io, my_io, sizeof(*my_io)))
1171 goto out_passthru;
1172 error = 0;
1173 out_passthru:
1174 kfree(my_io);
1175 return error;
1176 case IDAGETCTLRSIG:
1177 if (!arg) return -EINVAL;
1178 if (put_user(host->ctlr_sig, (int __user *)arg))
1179 return -EFAULT;
1180 return 0;
1181 case IDAREVALIDATEVOLS:
1182 if (MINOR(bdev->bd_dev) != 0)
1183 return -ENXIO;
1184 return revalidate_allvol(host);
1185 case IDADRIVERVERSION:
1186 if (!arg) return -EINVAL;
1187 if (put_user(DRIVER_VERSION, (unsigned long __user *)arg))
1188 return -EFAULT;
1189 return 0;
1190 case IDAGETPCIINFO:
1191 {
1192
1193 ida_pci_info_struct pciinfo;
1194
1195 if (!arg) return -EINVAL;
1196 pciinfo.bus = host->pci_dev->bus->number;
1197 pciinfo.dev_fn = host->pci_dev->devfn;
1198 pciinfo.board_id = host->board_id;
1199 if(copy_to_user((void __user *) arg, &pciinfo,
1200 sizeof( ida_pci_info_struct)))
1201 return -EFAULT;
1202 return(0);
1203 }
1204
1205 default:
1206 return -EINVAL;
1207 }
1208
1209 }
1210
ida_ioctl(struct block_device * bdev,fmode_t mode,unsigned int cmd,unsigned long param)1211 static int ida_ioctl(struct block_device *bdev, fmode_t mode,
1212 unsigned int cmd, unsigned long param)
1213 {
1214 int ret;
1215
1216 mutex_lock(&cpqarray_mutex);
1217 ret = ida_locked_ioctl(bdev, mode, cmd, param);
1218 mutex_unlock(&cpqarray_mutex);
1219
1220 return ret;
1221 }
1222
1223 /*
1224 * ida_ctlr_ioctl is for passing commands to the controller from userspace.
1225 * The command block (io) has already been copied to kernel space for us,
1226 * however, any elements in the sglist need to be copied to kernel space
1227 * or copied back to userspace.
1228 *
1229 * Only root may perform a controller passthru command, however I'm not doing
1230 * any serious sanity checking on the arguments. Doing an IDA_WRITE_MEDIA and
1231 * putting a 64M buffer in the sglist is probably a *bad* idea.
1232 */
ida_ctlr_ioctl(ctlr_info_t * h,int dsk,ida_ioctl_t * io)1233 static int ida_ctlr_ioctl(ctlr_info_t *h, int dsk, ida_ioctl_t *io)
1234 {
1235 int ctlr = h->ctlr;
1236 cmdlist_t *c;
1237 void *p = NULL;
1238 unsigned long flags;
1239 int error;
1240
1241 if ((c = cmd_alloc(h, 0)) == NULL)
1242 return -ENOMEM;
1243 c->ctlr = ctlr;
1244 c->hdr.unit = (io->unit & UNITVALID) ? (io->unit & ~UNITVALID) : dsk;
1245 c->hdr.size = sizeof(rblk_t) >> 2;
1246 c->size += sizeof(rblk_t);
1247
1248 c->req.hdr.cmd = io->cmd;
1249 c->req.hdr.blk = io->blk;
1250 c->req.hdr.blk_cnt = io->blk_cnt;
1251 c->type = CMD_IOCTL_PEND;
1252
1253 /* Pre submit processing */
1254 switch(io->cmd) {
1255 case PASSTHRU_A:
1256 p = memdup_user(io->sg[0].addr, io->sg[0].size);
1257 if (IS_ERR(p)) {
1258 error = PTR_ERR(p);
1259 cmd_free(h, c, 0);
1260 return error;
1261 }
1262 c->req.hdr.blk = pci_map_single(h->pci_dev, &(io->c),
1263 sizeof(ida_ioctl_t),
1264 PCI_DMA_BIDIRECTIONAL);
1265 c->req.sg[0].size = io->sg[0].size;
1266 c->req.sg[0].addr = pci_map_single(h->pci_dev, p,
1267 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1268 c->req.hdr.sg_cnt = 1;
1269 break;
1270 case IDA_READ:
1271 case READ_FLASH_ROM:
1272 case SENSE_CONTROLLER_PERFORMANCE:
1273 p = kmalloc(io->sg[0].size, GFP_KERNEL);
1274 if (!p)
1275 {
1276 error = -ENOMEM;
1277 cmd_free(h, c, 0);
1278 return(error);
1279 }
1280
1281 c->req.sg[0].size = io->sg[0].size;
1282 c->req.sg[0].addr = pci_map_single(h->pci_dev, p,
1283 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1284 c->req.hdr.sg_cnt = 1;
1285 break;
1286 case IDA_WRITE:
1287 case IDA_WRITE_MEDIA:
1288 case DIAG_PASS_THRU:
1289 case COLLECT_BUFFER:
1290 case WRITE_FLASH_ROM:
1291 p = memdup_user(io->sg[0].addr, io->sg[0].size);
1292 if (IS_ERR(p)) {
1293 error = PTR_ERR(p);
1294 cmd_free(h, c, 0);
1295 return error;
1296 }
1297 c->req.sg[0].size = io->sg[0].size;
1298 c->req.sg[0].addr = pci_map_single(h->pci_dev, p,
1299 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1300 c->req.hdr.sg_cnt = 1;
1301 break;
1302 default:
1303 c->req.sg[0].size = sizeof(io->c);
1304 c->req.sg[0].addr = pci_map_single(h->pci_dev,&io->c,
1305 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1306 c->req.hdr.sg_cnt = 1;
1307 }
1308
1309 /* Put the request on the tail of the request queue */
1310 spin_lock_irqsave(IDA_LOCK(ctlr), flags);
1311 addQ(&h->reqQ, c);
1312 h->Qdepth++;
1313 start_io(h);
1314 spin_unlock_irqrestore(IDA_LOCK(ctlr), flags);
1315
1316 /* Wait for completion */
1317 while(c->type != CMD_IOCTL_DONE)
1318 schedule();
1319
1320 /* Unmap the DMA */
1321 pci_unmap_single(h->pci_dev, c->req.sg[0].addr, c->req.sg[0].size,
1322 PCI_DMA_BIDIRECTIONAL);
1323 /* Post submit processing */
1324 switch(io->cmd) {
1325 case PASSTHRU_A:
1326 pci_unmap_single(h->pci_dev, c->req.hdr.blk,
1327 sizeof(ida_ioctl_t),
1328 PCI_DMA_BIDIRECTIONAL);
1329 case IDA_READ:
1330 case DIAG_PASS_THRU:
1331 case SENSE_CONTROLLER_PERFORMANCE:
1332 case READ_FLASH_ROM:
1333 if (copy_to_user(io->sg[0].addr, p, io->sg[0].size)) {
1334 kfree(p);
1335 return -EFAULT;
1336 }
1337 /* fall through and free p */
1338 case IDA_WRITE:
1339 case IDA_WRITE_MEDIA:
1340 case COLLECT_BUFFER:
1341 case WRITE_FLASH_ROM:
1342 kfree(p);
1343 break;
1344 default:;
1345 /* Nothing to do */
1346 }
1347
1348 io->rcode = c->req.hdr.rcode;
1349 cmd_free(h, c, 0);
1350 return(0);
1351 }
1352
1353 /*
1354 * Commands are pre-allocated in a large block. Here we use a simple bitmap
1355 * scheme to suballocte them to the driver. Operations that are not time
1356 * critical (and can wait for kmalloc and possibly sleep) can pass in NULL
1357 * as the first argument to get a new command.
1358 */
cmd_alloc(ctlr_info_t * h,int get_from_pool)1359 static cmdlist_t * cmd_alloc(ctlr_info_t *h, int get_from_pool)
1360 {
1361 cmdlist_t * c;
1362 int i;
1363 dma_addr_t cmd_dhandle;
1364
1365 if (!get_from_pool) {
1366 c = (cmdlist_t*)pci_alloc_consistent(h->pci_dev,
1367 sizeof(cmdlist_t), &cmd_dhandle);
1368 if(c==NULL)
1369 return NULL;
1370 } else {
1371 do {
1372 i = find_first_zero_bit(h->cmd_pool_bits, NR_CMDS);
1373 if (i == NR_CMDS)
1374 return NULL;
1375 } while(test_and_set_bit(i&(BITS_PER_LONG-1), h->cmd_pool_bits+(i/BITS_PER_LONG)) != 0);
1376 c = h->cmd_pool + i;
1377 cmd_dhandle = h->cmd_pool_dhandle + i*sizeof(cmdlist_t);
1378 h->nr_allocs++;
1379 }
1380
1381 memset(c, 0, sizeof(cmdlist_t));
1382 c->busaddr = cmd_dhandle;
1383 return c;
1384 }
1385
cmd_free(ctlr_info_t * h,cmdlist_t * c,int got_from_pool)1386 static void cmd_free(ctlr_info_t *h, cmdlist_t *c, int got_from_pool)
1387 {
1388 int i;
1389
1390 if (!got_from_pool) {
1391 pci_free_consistent(h->pci_dev, sizeof(cmdlist_t), c,
1392 c->busaddr);
1393 } else {
1394 i = c - h->cmd_pool;
1395 clear_bit(i&(BITS_PER_LONG-1), h->cmd_pool_bits+(i/BITS_PER_LONG));
1396 h->nr_frees++;
1397 }
1398 }
1399
1400 /***********************************************************************
1401 name: sendcmd
1402 Send a command to an IDA using the memory mapped FIFO interface
1403 and wait for it to complete.
1404 This routine should only be called at init time.
1405 ***********************************************************************/
sendcmd(__u8 cmd,int ctlr,void * buff,size_t size,unsigned int blk,unsigned int blkcnt,unsigned int log_unit)1406 static int sendcmd(
1407 __u8 cmd,
1408 int ctlr,
1409 void *buff,
1410 size_t size,
1411 unsigned int blk,
1412 unsigned int blkcnt,
1413 unsigned int log_unit )
1414 {
1415 cmdlist_t *c;
1416 int complete;
1417 unsigned long temp;
1418 unsigned long i;
1419 ctlr_info_t *info_p = hba[ctlr];
1420
1421 c = cmd_alloc(info_p, 1);
1422 if(!c)
1423 return IO_ERROR;
1424 c->ctlr = ctlr;
1425 c->hdr.unit = log_unit;
1426 c->hdr.prio = 0;
1427 c->hdr.size = sizeof(rblk_t) >> 2;
1428 c->size += sizeof(rblk_t);
1429
1430 /* The request information. */
1431 c->req.hdr.next = 0;
1432 c->req.hdr.rcode = 0;
1433 c->req.bp = 0;
1434 c->req.hdr.sg_cnt = 1;
1435 c->req.hdr.reserved = 0;
1436
1437 if (size == 0)
1438 c->req.sg[0].size = 512;
1439 else
1440 c->req.sg[0].size = size;
1441
1442 c->req.hdr.blk = blk;
1443 c->req.hdr.blk_cnt = blkcnt;
1444 c->req.hdr.cmd = (unsigned char) cmd;
1445 c->req.sg[0].addr = (__u32) pci_map_single(info_p->pci_dev,
1446 buff, c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1447 /*
1448 * Disable interrupt
1449 */
1450 info_p->access.set_intr_mask(info_p, 0);
1451 /* Make sure there is room in the command FIFO */
1452 /* Actually it should be completely empty at this time. */
1453 for (i = 200000; i > 0; i--) {
1454 temp = info_p->access.fifo_full(info_p);
1455 if (temp != 0) {
1456 break;
1457 }
1458 udelay(10);
1459 DBG(
1460 printk(KERN_WARNING "cpqarray ida%d: idaSendPciCmd FIFO full,"
1461 " waiting!\n", ctlr);
1462 );
1463 }
1464 /*
1465 * Send the cmd
1466 */
1467 info_p->access.submit_command(info_p, c);
1468 complete = pollcomplete(ctlr);
1469
1470 pci_unmap_single(info_p->pci_dev, (dma_addr_t) c->req.sg[0].addr,
1471 c->req.sg[0].size, PCI_DMA_BIDIRECTIONAL);
1472 if (complete != 1) {
1473 if (complete != c->busaddr) {
1474 printk( KERN_WARNING
1475 "cpqarray ida%d: idaSendPciCmd "
1476 "Invalid command list address returned! (%08lx)\n",
1477 ctlr, (unsigned long)complete);
1478 cmd_free(info_p, c, 1);
1479 return (IO_ERROR);
1480 }
1481 } else {
1482 printk( KERN_WARNING
1483 "cpqarray ida%d: idaSendPciCmd Timeout out, "
1484 "No command list address returned!\n",
1485 ctlr);
1486 cmd_free(info_p, c, 1);
1487 return (IO_ERROR);
1488 }
1489
1490 if (c->req.hdr.rcode & 0x00FE) {
1491 if (!(c->req.hdr.rcode & BIG_PROBLEM)) {
1492 printk( KERN_WARNING
1493 "cpqarray ida%d: idaSendPciCmd, error: "
1494 "Controller failed at init time "
1495 "cmd: 0x%x, return code = 0x%x\n",
1496 ctlr, c->req.hdr.cmd, c->req.hdr.rcode);
1497
1498 cmd_free(info_p, c, 1);
1499 return (IO_ERROR);
1500 }
1501 }
1502 cmd_free(info_p, c, 1);
1503 return (IO_OK);
1504 }
1505
1506 /*
1507 * revalidate_allvol is for online array config utilities. After a
1508 * utility reconfigures the drives in the array, it can use this function
1509 * (through an ioctl) to make the driver zap any previous disk structs for
1510 * that controller and get new ones.
1511 *
1512 * Right now I'm using the getgeometry() function to do this, but this
1513 * function should probably be finer grained and allow you to revalidate one
1514 * particualar logical volume (instead of all of them on a particular
1515 * controller).
1516 */
revalidate_allvol(ctlr_info_t * host)1517 static int revalidate_allvol(ctlr_info_t *host)
1518 {
1519 int ctlr = host->ctlr;
1520 int i;
1521 unsigned long flags;
1522
1523 spin_lock_irqsave(IDA_LOCK(ctlr), flags);
1524 if (host->usage_count > 1) {
1525 spin_unlock_irqrestore(IDA_LOCK(ctlr), flags);
1526 printk(KERN_WARNING "cpqarray: Device busy for volume"
1527 " revalidation (usage=%d)\n", host->usage_count);
1528 return -EBUSY;
1529 }
1530 host->usage_count++;
1531 spin_unlock_irqrestore(IDA_LOCK(ctlr), flags);
1532
1533 /*
1534 * Set the partition and block size structures for all volumes
1535 * on this controller to zero. We will reread all of this data
1536 */
1537 set_capacity(ida_gendisk[ctlr][0], 0);
1538 for (i = 1; i < NWD; i++) {
1539 struct gendisk *disk = ida_gendisk[ctlr][i];
1540 if (disk->flags & GENHD_FL_UP)
1541 del_gendisk(disk);
1542 }
1543 memset(host->drv, 0, sizeof(drv_info_t)*NWD);
1544
1545 /*
1546 * Tell the array controller not to give us any interrupts while
1547 * we check the new geometry. Then turn interrupts back on when
1548 * we're done.
1549 */
1550 host->access.set_intr_mask(host, 0);
1551 getgeometry(ctlr);
1552 host->access.set_intr_mask(host, FIFO_NOT_EMPTY);
1553
1554 for(i=0; i<NWD; i++) {
1555 struct gendisk *disk = ida_gendisk[ctlr][i];
1556 drv_info_t *drv = &host->drv[i];
1557 if (i && !drv->nr_blks)
1558 continue;
1559 blk_queue_logical_block_size(host->queue, drv->blk_size);
1560 set_capacity(disk, drv->nr_blks);
1561 disk->queue = host->queue;
1562 disk->private_data = drv;
1563 if (i)
1564 add_disk(disk);
1565 }
1566
1567 host->usage_count--;
1568 return 0;
1569 }
1570
ida_revalidate(struct gendisk * disk)1571 static int ida_revalidate(struct gendisk *disk)
1572 {
1573 drv_info_t *drv = disk->private_data;
1574 set_capacity(disk, drv->nr_blks);
1575 return 0;
1576 }
1577
1578 /********************************************************************
1579 name: pollcomplete
1580 Wait polling for a command to complete.
1581 The memory mapped FIFO is polled for the completion.
1582 Used only at init time, interrupts disabled.
1583 ********************************************************************/
pollcomplete(int ctlr)1584 static int pollcomplete(int ctlr)
1585 {
1586 int done;
1587 int i;
1588
1589 /* Wait (up to 2 seconds) for a command to complete */
1590
1591 for (i = 200000; i > 0; i--) {
1592 done = hba[ctlr]->access.command_completed(hba[ctlr]);
1593 if (done == 0) {
1594 udelay(10); /* a short fixed delay */
1595 } else
1596 return (done);
1597 }
1598 /* Invalid address to tell caller we ran out of time */
1599 return 1;
1600 }
1601 /*****************************************************************
1602 start_fwbk
1603 Starts controller firmwares background processing.
1604 Currently only the Integrated Raid controller needs this done.
1605 If the PCI mem address registers are written to after this,
1606 data corruption may occur
1607 *****************************************************************/
start_fwbk(int ctlr)1608 static void start_fwbk(int ctlr)
1609 {
1610 id_ctlr_t *id_ctlr_buf;
1611 int ret_code;
1612
1613 if( (hba[ctlr]->board_id != 0x40400E11)
1614 && (hba[ctlr]->board_id != 0x40480E11) )
1615
1616 /* Not a Integrated Raid, so there is nothing for us to do */
1617 return;
1618 printk(KERN_DEBUG "cpqarray: Starting firmware's background"
1619 " processing\n");
1620 /* Command does not return anything, but idasend command needs a
1621 buffer */
1622 id_ctlr_buf = kmalloc(sizeof(id_ctlr_t), GFP_KERNEL);
1623 if(id_ctlr_buf==NULL)
1624 {
1625 printk(KERN_WARNING "cpqarray: Out of memory. "
1626 "Unable to start background processing.\n");
1627 return;
1628 }
1629 ret_code = sendcmd(RESUME_BACKGROUND_ACTIVITY, ctlr,
1630 id_ctlr_buf, 0, 0, 0, 0);
1631 if(ret_code != IO_OK)
1632 printk(KERN_WARNING "cpqarray: Unable to start"
1633 " background processing\n");
1634
1635 kfree(id_ctlr_buf);
1636 }
1637 /*****************************************************************
1638 getgeometry
1639 Get ida logical volume geometry from the controller
1640 This is a large bit of code which once existed in two flavors,
1641 It is used only at init time.
1642 *****************************************************************/
getgeometry(int ctlr)1643 static void getgeometry(int ctlr)
1644 {
1645 id_log_drv_t *id_ldrive;
1646 id_ctlr_t *id_ctlr_buf;
1647 sense_log_drv_stat_t *id_lstatus_buf;
1648 config_t *sense_config_buf;
1649 unsigned int log_unit, log_index;
1650 int ret_code, size;
1651 drv_info_t *drv;
1652 ctlr_info_t *info_p = hba[ctlr];
1653 int i;
1654
1655 info_p->log_drv_map = 0;
1656
1657 id_ldrive = kzalloc(sizeof(id_log_drv_t), GFP_KERNEL);
1658 if (!id_ldrive) {
1659 printk( KERN_ERR "cpqarray: out of memory.\n");
1660 goto err_0;
1661 }
1662
1663 id_ctlr_buf = kzalloc(sizeof(id_ctlr_t), GFP_KERNEL);
1664 if (!id_ctlr_buf) {
1665 printk( KERN_ERR "cpqarray: out of memory.\n");
1666 goto err_1;
1667 }
1668
1669 id_lstatus_buf = kzalloc(sizeof(sense_log_drv_stat_t), GFP_KERNEL);
1670 if (!id_lstatus_buf) {
1671 printk( KERN_ERR "cpqarray: out of memory.\n");
1672 goto err_2;
1673 }
1674
1675 sense_config_buf = kzalloc(sizeof(config_t), GFP_KERNEL);
1676 if (!sense_config_buf) {
1677 printk( KERN_ERR "cpqarray: out of memory.\n");
1678 goto err_3;
1679 }
1680
1681 info_p->phys_drives = 0;
1682 info_p->log_drv_map = 0;
1683 info_p->drv_assign_map = 0;
1684 info_p->drv_spare_map = 0;
1685 info_p->mp_failed_drv_map = 0; /* only initialized here */
1686 /* Get controllers info for this logical drive */
1687 ret_code = sendcmd(ID_CTLR, ctlr, id_ctlr_buf, 0, 0, 0, 0);
1688 if (ret_code == IO_ERROR) {
1689 /*
1690 * If can't get controller info, set the logical drive map to 0,
1691 * so the idastubopen will fail on all logical drives
1692 * on the controller.
1693 */
1694 printk(KERN_ERR "cpqarray: error sending ID controller\n");
1695 goto err_4;
1696 }
1697
1698 info_p->log_drives = id_ctlr_buf->nr_drvs;
1699 for(i=0;i<4;i++)
1700 info_p->firm_rev[i] = id_ctlr_buf->firm_rev[i];
1701 info_p->ctlr_sig = id_ctlr_buf->cfg_sig;
1702
1703 printk(" (%s)\n", info_p->product_name);
1704 /*
1705 * Initialize logical drive map to zero
1706 */
1707 log_index = 0;
1708 /*
1709 * Get drive geometry for all logical drives
1710 */
1711 if (id_ctlr_buf->nr_drvs > 16)
1712 printk(KERN_WARNING "cpqarray ida%d: This driver supports "
1713 "16 logical drives per controller.\n. "
1714 " Additional drives will not be "
1715 "detected\n", ctlr);
1716
1717 for (log_unit = 0;
1718 (log_index < id_ctlr_buf->nr_drvs)
1719 && (log_unit < NWD);
1720 log_unit++) {
1721 size = sizeof(sense_log_drv_stat_t);
1722
1723 /*
1724 Send "Identify logical drive status" cmd
1725 */
1726 ret_code = sendcmd(SENSE_LOG_DRV_STAT,
1727 ctlr, id_lstatus_buf, size, 0, 0, log_unit);
1728 if (ret_code == IO_ERROR) {
1729 /*
1730 If can't get logical drive status, set
1731 the logical drive map to 0, so the
1732 idastubopen will fail for all logical drives
1733 on the controller.
1734 */
1735 info_p->log_drv_map = 0;
1736 printk( KERN_WARNING
1737 "cpqarray ida%d: idaGetGeometry - Controller"
1738 " failed to report status of logical drive %d\n"
1739 "Access to this controller has been disabled\n",
1740 ctlr, log_unit);
1741 goto err_4;
1742 }
1743 /*
1744 Make sure the logical drive is configured
1745 */
1746 if (id_lstatus_buf->status != LOG_NOT_CONF) {
1747 ret_code = sendcmd(ID_LOG_DRV, ctlr, id_ldrive,
1748 sizeof(id_log_drv_t), 0, 0, log_unit);
1749 /*
1750 If error, the bit for this
1751 logical drive won't be set and
1752 idastubopen will return error.
1753 */
1754 if (ret_code != IO_ERROR) {
1755 drv = &info_p->drv[log_unit];
1756 drv->blk_size = id_ldrive->blk_size;
1757 drv->nr_blks = id_ldrive->nr_blks;
1758 drv->cylinders = id_ldrive->drv.cyl;
1759 drv->heads = id_ldrive->drv.heads;
1760 drv->sectors = id_ldrive->drv.sect_per_track;
1761 info_p->log_drv_map |= (1 << log_unit);
1762
1763 printk(KERN_INFO "cpqarray ida/c%dd%d: blksz=%d nr_blks=%d\n",
1764 ctlr, log_unit, drv->blk_size, drv->nr_blks);
1765 ret_code = sendcmd(SENSE_CONFIG,
1766 ctlr, sense_config_buf,
1767 sizeof(config_t), 0, 0, log_unit);
1768 if (ret_code == IO_ERROR) {
1769 info_p->log_drv_map = 0;
1770 printk(KERN_ERR "cpqarray: error sending sense config\n");
1771 goto err_4;
1772 }
1773
1774 info_p->phys_drives =
1775 sense_config_buf->ctlr_phys_drv;
1776 info_p->drv_assign_map
1777 |= sense_config_buf->drv_asgn_map;
1778 info_p->drv_assign_map
1779 |= sense_config_buf->spare_asgn_map;
1780 info_p->drv_spare_map
1781 |= sense_config_buf->spare_asgn_map;
1782 } /* end of if no error on id_ldrive */
1783 log_index = log_index + 1;
1784 } /* end of if logical drive configured */
1785 } /* end of for log_unit */
1786
1787 /* Free all the buffers and return */
1788 err_4:
1789 kfree(sense_config_buf);
1790 err_3:
1791 kfree(id_lstatus_buf);
1792 err_2:
1793 kfree(id_ctlr_buf);
1794 err_1:
1795 kfree(id_ldrive);
1796 err_0:
1797 return;
1798 }
1799
cpqarray_exit(void)1800 static void __exit cpqarray_exit(void)
1801 {
1802 int i;
1803
1804 pci_unregister_driver(&cpqarray_pci_driver);
1805
1806 /* Double check that all controller entries have been removed */
1807 for(i=0; i<MAX_CTLR; i++) {
1808 if (hba[i] != NULL) {
1809 printk(KERN_WARNING "cpqarray: Removing EISA "
1810 "controller %d\n", i);
1811 cpqarray_remove_one_eisa(i);
1812 }
1813 }
1814
1815 remove_proc_entry("driver/cpqarray", NULL);
1816 }
1817
1818 module_init(cpqarray_init)
1819 module_exit(cpqarray_exit)
1820