1 /*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/of.h>
20 #include <linux/clk/tegra.h>
21
22 #include "clk.h"
23
24 /* Global data of Tegra CPU CAR ops */
25 static struct tegra_cpu_car_ops dummy_car_ops;
26 struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops;
27
tegra_init_dup_clks(struct tegra_clk_duplicate * dup_list,struct clk * clks[],int clk_max)28 void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
29 struct clk *clks[], int clk_max)
30 {
31 struct clk *clk;
32
33 for (; dup_list->clk_id < clk_max; dup_list++) {
34 clk = clks[dup_list->clk_id];
35 dup_list->lookup.clk = clk;
36 clkdev_add(&dup_list->lookup);
37 }
38 }
39
tegra_init_from_table(struct tegra_clk_init_table * tbl,struct clk * clks[],int clk_max)40 void __init tegra_init_from_table(struct tegra_clk_init_table *tbl,
41 struct clk *clks[], int clk_max)
42 {
43 struct clk *clk;
44
45 for (; tbl->clk_id < clk_max; tbl++) {
46 clk = clks[tbl->clk_id];
47 if (IS_ERR_OR_NULL(clk))
48 return;
49
50 if (tbl->parent_id < clk_max) {
51 struct clk *parent = clks[tbl->parent_id];
52 if (clk_set_parent(clk, parent)) {
53 pr_err("%s: Failed to set parent %s of %s\n",
54 __func__, __clk_get_name(parent),
55 __clk_get_name(clk));
56 WARN_ON(1);
57 }
58 }
59
60 if (tbl->rate)
61 if (clk_set_rate(clk, tbl->rate)) {
62 pr_err("%s: Failed to set rate %lu of %s\n",
63 __func__, tbl->rate,
64 __clk_get_name(clk));
65 WARN_ON(1);
66 }
67
68 if (tbl->state)
69 if (clk_prepare_enable(clk)) {
70 pr_err("%s: Failed to enable %s\n", __func__,
71 __clk_get_name(clk));
72 WARN_ON(1);
73 }
74 }
75 }
76
77 static const struct of_device_id tegra_dt_clk_match[] = {
78 { .compatible = "nvidia,tegra20-car", .data = tegra20_clock_init },
79 { .compatible = "nvidia,tegra30-car", .data = tegra30_clock_init },
80 { .compatible = "nvidia,tegra114-car", .data = tegra114_clock_init },
81 { }
82 };
83
tegra_clocks_init(void)84 void __init tegra_clocks_init(void)
85 {
86 of_clk_init(tegra_dt_clk_match);
87 }
88
89 tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
90
tegra_clocks_apply_init_table(void)91 void __init tegra_clocks_apply_init_table(void)
92 {
93 if (!tegra_clk_apply_init_table)
94 return;
95
96 tegra_clk_apply_init_table();
97 }
98