1 /*
2 * Moorestown platform Langwell chip GPIO driver
3 *
4 * Copyright (c) 2008 - 2009, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20 /* Supports:
21 * Moorestown platform Langwell chip.
22 * Medfield platform Penwell chip.
23 * Whitney point.
24 */
25
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/platform_device.h>
29 #include <linux/kernel.h>
30 #include <linux/delay.h>
31 #include <linux/stddef.h>
32 #include <linux/interrupt.h>
33 #include <linux/init.h>
34 #include <linux/irq.h>
35 #include <linux/io.h>
36 #include <linux/gpio.h>
37 #include <linux/slab.h>
38 #include <linux/pm_runtime.h>
39 #include <linux/irqdomain.h>
40
41 /*
42 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
43 * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
44 * registers to control them, so we only define the order here instead of a
45 * structure, to get a bit offset for a pin (use GPDR as an example):
46 *
47 * nreg = ngpio / 32;
48 * reg = offset / 32;
49 * bit = offset % 32;
50 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
51 *
52 * so the bit of reg_addr is to control pin offset's GPDR feature
53 */
54
55 enum GPIO_REG {
56 GPLR = 0, /* pin level read-only */
57 GPDR, /* pin direction */
58 GPSR, /* pin set */
59 GPCR, /* pin clear */
60 GRER, /* rising edge detect */
61 GFER, /* falling edge detect */
62 GEDR, /* edge detect result */
63 GAFR, /* alt function */
64 };
65
66 struct lnw_gpio {
67 struct gpio_chip chip;
68 void *reg_base;
69 spinlock_t lock;
70 struct pci_dev *pdev;
71 struct irq_domain *domain;
72 };
73
74 #define to_lnw_priv(chip) container_of(chip, struct lnw_gpio, chip)
75
gpio_reg(struct gpio_chip * chip,unsigned offset,enum GPIO_REG reg_type)76 static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
77 enum GPIO_REG reg_type)
78 {
79 struct lnw_gpio *lnw = to_lnw_priv(chip);
80 unsigned nreg = chip->ngpio / 32;
81 u8 reg = offset / 32;
82 void __iomem *ptr;
83
84 ptr = (void __iomem *)(lnw->reg_base + reg_type * nreg * 4 + reg * 4);
85 return ptr;
86 }
87
gpio_reg_2bit(struct gpio_chip * chip,unsigned offset,enum GPIO_REG reg_type)88 static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
89 enum GPIO_REG reg_type)
90 {
91 struct lnw_gpio *lnw = to_lnw_priv(chip);
92 unsigned nreg = chip->ngpio / 32;
93 u8 reg = offset / 16;
94 void __iomem *ptr;
95
96 ptr = (void __iomem *)(lnw->reg_base + reg_type * nreg * 4 + reg * 4);
97 return ptr;
98 }
99
lnw_gpio_request(struct gpio_chip * chip,unsigned offset)100 static int lnw_gpio_request(struct gpio_chip *chip, unsigned offset)
101 {
102 void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
103 u32 value = readl(gafr);
104 int shift = (offset % 16) << 1, af = (value >> shift) & 3;
105
106 if (af) {
107 value &= ~(3 << shift);
108 writel(value, gafr);
109 }
110 return 0;
111 }
112
lnw_gpio_get(struct gpio_chip * chip,unsigned offset)113 static int lnw_gpio_get(struct gpio_chip *chip, unsigned offset)
114 {
115 void __iomem *gplr = gpio_reg(chip, offset, GPLR);
116
117 return readl(gplr) & BIT(offset % 32);
118 }
119
lnw_gpio_set(struct gpio_chip * chip,unsigned offset,int value)120 static void lnw_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
121 {
122 void __iomem *gpsr, *gpcr;
123
124 if (value) {
125 gpsr = gpio_reg(chip, offset, GPSR);
126 writel(BIT(offset % 32), gpsr);
127 } else {
128 gpcr = gpio_reg(chip, offset, GPCR);
129 writel(BIT(offset % 32), gpcr);
130 }
131 }
132
lnw_gpio_direction_input(struct gpio_chip * chip,unsigned offset)133 static int lnw_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
134 {
135 struct lnw_gpio *lnw = to_lnw_priv(chip);
136 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
137 u32 value;
138 unsigned long flags;
139
140 if (lnw->pdev)
141 pm_runtime_get(&lnw->pdev->dev);
142
143 spin_lock_irqsave(&lnw->lock, flags);
144 value = readl(gpdr);
145 value &= ~BIT(offset % 32);
146 writel(value, gpdr);
147 spin_unlock_irqrestore(&lnw->lock, flags);
148
149 if (lnw->pdev)
150 pm_runtime_put(&lnw->pdev->dev);
151
152 return 0;
153 }
154
lnw_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int value)155 static int lnw_gpio_direction_output(struct gpio_chip *chip,
156 unsigned offset, int value)
157 {
158 struct lnw_gpio *lnw = to_lnw_priv(chip);
159 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
160 unsigned long flags;
161
162 lnw_gpio_set(chip, offset, value);
163
164 if (lnw->pdev)
165 pm_runtime_get(&lnw->pdev->dev);
166
167 spin_lock_irqsave(&lnw->lock, flags);
168 value = readl(gpdr);
169 value |= BIT(offset % 32);
170 writel(value, gpdr);
171 spin_unlock_irqrestore(&lnw->lock, flags);
172
173 if (lnw->pdev)
174 pm_runtime_put(&lnw->pdev->dev);
175
176 return 0;
177 }
178
lnw_gpio_to_irq(struct gpio_chip * chip,unsigned offset)179 static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
180 {
181 struct lnw_gpio *lnw = to_lnw_priv(chip);
182 return irq_create_mapping(lnw->domain, offset);
183 }
184
lnw_irq_type(struct irq_data * d,unsigned type)185 static int lnw_irq_type(struct irq_data *d, unsigned type)
186 {
187 struct lnw_gpio *lnw = irq_data_get_irq_chip_data(d);
188 u32 gpio = irqd_to_hwirq(d);
189 unsigned long flags;
190 u32 value;
191 void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER);
192 void __iomem *gfer = gpio_reg(&lnw->chip, gpio, GFER);
193
194 if (gpio >= lnw->chip.ngpio)
195 return -EINVAL;
196
197 if (lnw->pdev)
198 pm_runtime_get(&lnw->pdev->dev);
199
200 spin_lock_irqsave(&lnw->lock, flags);
201 if (type & IRQ_TYPE_EDGE_RISING)
202 value = readl(grer) | BIT(gpio % 32);
203 else
204 value = readl(grer) & (~BIT(gpio % 32));
205 writel(value, grer);
206
207 if (type & IRQ_TYPE_EDGE_FALLING)
208 value = readl(gfer) | BIT(gpio % 32);
209 else
210 value = readl(gfer) & (~BIT(gpio % 32));
211 writel(value, gfer);
212 spin_unlock_irqrestore(&lnw->lock, flags);
213
214 if (lnw->pdev)
215 pm_runtime_put(&lnw->pdev->dev);
216
217 return 0;
218 }
219
lnw_irq_unmask(struct irq_data * d)220 static void lnw_irq_unmask(struct irq_data *d)
221 {
222 }
223
lnw_irq_mask(struct irq_data * d)224 static void lnw_irq_mask(struct irq_data *d)
225 {
226 }
227
228 static struct irq_chip lnw_irqchip = {
229 .name = "LNW-GPIO",
230 .irq_mask = lnw_irq_mask,
231 .irq_unmask = lnw_irq_unmask,
232 .irq_set_type = lnw_irq_type,
233 };
234
235 static DEFINE_PCI_DEVICE_TABLE(lnw_gpio_ids) = { /* pin number */
236 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f), .driver_data = 64 },
237 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f), .driver_data = 96 },
238 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a), .driver_data = 96 },
239 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb), .driver_data = 96 },
240 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7), .driver_data = 96 },
241 { 0, }
242 };
243 MODULE_DEVICE_TABLE(pci, lnw_gpio_ids);
244
lnw_irq_handler(unsigned irq,struct irq_desc * desc)245 static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
246 {
247 struct irq_data *data = irq_desc_get_irq_data(desc);
248 struct lnw_gpio *lnw = irq_data_get_irq_handler_data(data);
249 struct irq_chip *chip = irq_data_get_irq_chip(data);
250 u32 base, gpio, mask;
251 unsigned long pending;
252 void __iomem *gedr;
253
254 /* check GPIO controller to check which pin triggered the interrupt */
255 for (base = 0; base < lnw->chip.ngpio; base += 32) {
256 gedr = gpio_reg(&lnw->chip, base, GEDR);
257 while ((pending = readl(gedr))) {
258 gpio = __ffs(pending);
259 mask = BIT(gpio);
260 /* Clear before handling so we can't lose an edge */
261 writel(mask, gedr);
262 generic_handle_irq(irq_find_mapping(lnw->domain,
263 base + gpio));
264 }
265 }
266
267 chip->irq_eoi(data);
268 }
269
lnw_irq_init_hw(struct lnw_gpio * lnw)270 static void lnw_irq_init_hw(struct lnw_gpio *lnw)
271 {
272 void __iomem *reg;
273 unsigned base;
274
275 for (base = 0; base < lnw->chip.ngpio; base += 32) {
276 /* Clear the rising-edge detect register */
277 reg = gpio_reg(&lnw->chip, base, GRER);
278 writel(0, reg);
279 /* Clear the falling-edge detect register */
280 reg = gpio_reg(&lnw->chip, base, GFER);
281 writel(0, reg);
282 /* Clear the edge detect status register */
283 reg = gpio_reg(&lnw->chip, base, GEDR);
284 writel(~0, reg);
285 }
286 }
287
lnw_gpio_irq_map(struct irq_domain * d,unsigned int virq,irq_hw_number_t hw)288 static int lnw_gpio_irq_map(struct irq_domain *d, unsigned int virq,
289 irq_hw_number_t hw)
290 {
291 struct lnw_gpio *lnw = d->host_data;
292
293 irq_set_chip_and_handler_name(virq, &lnw_irqchip, handle_simple_irq,
294 "demux");
295 irq_set_chip_data(virq, lnw);
296 irq_set_irq_type(virq, IRQ_TYPE_NONE);
297
298 return 0;
299 }
300
301 static const struct irq_domain_ops lnw_gpio_irq_ops = {
302 .map = lnw_gpio_irq_map,
303 .xlate = irq_domain_xlate_twocell,
304 };
305
lnw_gpio_runtime_idle(struct device * dev)306 static int lnw_gpio_runtime_idle(struct device *dev)
307 {
308 int err = pm_schedule_suspend(dev, 500);
309
310 if (!err)
311 return 0;
312
313 return -EBUSY;
314 }
315
316 static const struct dev_pm_ops lnw_gpio_pm_ops = {
317 SET_RUNTIME_PM_OPS(NULL, NULL, lnw_gpio_runtime_idle)
318 };
319
lnw_gpio_probe(struct pci_dev * pdev,const struct pci_device_id * id)320 static int lnw_gpio_probe(struct pci_dev *pdev,
321 const struct pci_device_id *id)
322 {
323 void *base;
324 resource_size_t start, len;
325 struct lnw_gpio *lnw;
326 u32 gpio_base;
327 u32 irq_base;
328 int retval;
329 int ngpio = id->driver_data;
330
331 retval = pci_enable_device(pdev);
332 if (retval)
333 return retval;
334
335 retval = pci_request_regions(pdev, "langwell_gpio");
336 if (retval) {
337 dev_err(&pdev->dev, "error requesting resources\n");
338 goto err_pci_req_region;
339 }
340 /* get the gpio_base from bar1 */
341 start = pci_resource_start(pdev, 1);
342 len = pci_resource_len(pdev, 1);
343 base = ioremap_nocache(start, len);
344 if (!base) {
345 dev_err(&pdev->dev, "error mapping bar1\n");
346 retval = -EFAULT;
347 goto err_ioremap;
348 }
349 irq_base = *(u32 *)base;
350 gpio_base = *((u32 *)base + 1);
351 /* release the IO mapping, since we already get the info from bar1 */
352 iounmap(base);
353 /* get the register base from bar0 */
354 start = pci_resource_start(pdev, 0);
355 len = pci_resource_len(pdev, 0);
356 base = devm_ioremap_nocache(&pdev->dev, start, len);
357 if (!base) {
358 dev_err(&pdev->dev, "error mapping bar0\n");
359 retval = -EFAULT;
360 goto err_ioremap;
361 }
362
363 lnw = devm_kzalloc(&pdev->dev, sizeof(*lnw), GFP_KERNEL);
364 if (!lnw) {
365 dev_err(&pdev->dev, "can't allocate langwell_gpio chip data\n");
366 retval = -ENOMEM;
367 goto err_ioremap;
368 }
369
370 lnw->reg_base = base;
371 lnw->chip.label = dev_name(&pdev->dev);
372 lnw->chip.request = lnw_gpio_request;
373 lnw->chip.direction_input = lnw_gpio_direction_input;
374 lnw->chip.direction_output = lnw_gpio_direction_output;
375 lnw->chip.get = lnw_gpio_get;
376 lnw->chip.set = lnw_gpio_set;
377 lnw->chip.to_irq = lnw_gpio_to_irq;
378 lnw->chip.base = gpio_base;
379 lnw->chip.ngpio = ngpio;
380 lnw->chip.can_sleep = 0;
381 lnw->pdev = pdev;
382
383 lnw->domain = irq_domain_add_simple(pdev->dev.of_node, ngpio, irq_base,
384 &lnw_gpio_irq_ops, lnw);
385 if (!lnw->domain) {
386 retval = -ENOMEM;
387 goto err_ioremap;
388 }
389
390 pci_set_drvdata(pdev, lnw);
391 retval = gpiochip_add(&lnw->chip);
392 if (retval) {
393 dev_err(&pdev->dev, "langwell gpiochip_add error %d\n", retval);
394 goto err_ioremap;
395 }
396
397 lnw_irq_init_hw(lnw);
398
399 irq_set_handler_data(pdev->irq, lnw);
400 irq_set_chained_handler(pdev->irq, lnw_irq_handler);
401
402 spin_lock_init(&lnw->lock);
403
404 pm_runtime_put_noidle(&pdev->dev);
405 pm_runtime_allow(&pdev->dev);
406
407 return 0;
408
409 err_ioremap:
410 pci_release_regions(pdev);
411 err_pci_req_region:
412 pci_disable_device(pdev);
413 return retval;
414 }
415
416 static struct pci_driver lnw_gpio_driver = {
417 .name = "langwell_gpio",
418 .id_table = lnw_gpio_ids,
419 .probe = lnw_gpio_probe,
420 .driver = {
421 .pm = &lnw_gpio_pm_ops,
422 },
423 };
424
425
wp_gpio_probe(struct platform_device * pdev)426 static int wp_gpio_probe(struct platform_device *pdev)
427 {
428 struct lnw_gpio *lnw;
429 struct gpio_chip *gc;
430 struct resource *rc;
431 int retval = 0;
432
433 rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
434 if (!rc)
435 return -EINVAL;
436
437 lnw = kzalloc(sizeof(struct lnw_gpio), GFP_KERNEL);
438 if (!lnw) {
439 dev_err(&pdev->dev,
440 "can't allocate whitneypoint_gpio chip data\n");
441 return -ENOMEM;
442 }
443 lnw->reg_base = ioremap_nocache(rc->start, resource_size(rc));
444 if (lnw->reg_base == NULL) {
445 retval = -EINVAL;
446 goto err_kmalloc;
447 }
448 spin_lock_init(&lnw->lock);
449 gc = &lnw->chip;
450 gc->label = dev_name(&pdev->dev);
451 gc->owner = THIS_MODULE;
452 gc->direction_input = lnw_gpio_direction_input;
453 gc->direction_output = lnw_gpio_direction_output;
454 gc->get = lnw_gpio_get;
455 gc->set = lnw_gpio_set;
456 gc->to_irq = NULL;
457 gc->base = 0;
458 gc->ngpio = 64;
459 gc->can_sleep = 0;
460 retval = gpiochip_add(gc);
461 if (retval) {
462 dev_err(&pdev->dev, "whitneypoint gpiochip_add error %d\n",
463 retval);
464 goto err_ioremap;
465 }
466 platform_set_drvdata(pdev, lnw);
467 return 0;
468 err_ioremap:
469 iounmap(lnw->reg_base);
470 err_kmalloc:
471 kfree(lnw);
472 return retval;
473 }
474
wp_gpio_remove(struct platform_device * pdev)475 static int wp_gpio_remove(struct platform_device *pdev)
476 {
477 struct lnw_gpio *lnw = platform_get_drvdata(pdev);
478 int err;
479 err = gpiochip_remove(&lnw->chip);
480 if (err)
481 dev_err(&pdev->dev, "failed to remove gpio_chip.\n");
482 iounmap(lnw->reg_base);
483 kfree(lnw);
484 platform_set_drvdata(pdev, NULL);
485 return 0;
486 }
487
488 static struct platform_driver wp_gpio_driver = {
489 .probe = wp_gpio_probe,
490 .remove = wp_gpio_remove,
491 .driver = {
492 .name = "wp_gpio",
493 .owner = THIS_MODULE,
494 },
495 };
496
lnw_gpio_init(void)497 static int __init lnw_gpio_init(void)
498 {
499 int ret;
500 ret = pci_register_driver(&lnw_gpio_driver);
501 if (ret < 0)
502 return ret;
503 ret = platform_driver_register(&wp_gpio_driver);
504 if (ret < 0)
505 pci_unregister_driver(&lnw_gpio_driver);
506 return ret;
507 }
508
509 device_initcall(lnw_gpio_init);
510