1 /*
2 * STMicroelectronics ConneXt (STA2X11) GPIO driver
3 *
4 * Copyright 2012 ST Microelectronics (Alessandro Rubini)
5 * Based on gpio-ml-ioh.c, Copyright 2010 OKI Semiconductors Ltd.
6 * Also based on previous sta2x11 work, Copyright 2011 Wind River Systems, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
15 * See the GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/gpio.h>
27 #include <linux/interrupt.h>
28 #include <linux/irq.h>
29 #include <linux/pci.h>
30 #include <linux/platform_device.h>
31 #include <linux/mfd/sta2x11-mfd.h>
32
33 struct gsta_regs {
34 u32 dat; /* 0x00 */
35 u32 dats;
36 u32 datc;
37 u32 pdis;
38 u32 dir; /* 0x10 */
39 u32 dirs;
40 u32 dirc;
41 u32 unused_1c;
42 u32 afsela; /* 0x20 */
43 u32 unused_24[7];
44 u32 rimsc; /* 0x40 */
45 u32 fimsc;
46 u32 is;
47 u32 ic;
48 };
49
50 struct gsta_gpio {
51 spinlock_t lock;
52 struct device *dev;
53 void __iomem *reg_base;
54 struct gsta_regs __iomem *regs[GSTA_NR_BLOCKS];
55 struct gpio_chip gpio;
56 int irq_base;
57 /* FIXME: save the whole config here (AF, ...) */
58 unsigned irq_type[GSTA_NR_GPIO];
59 };
60
__regs(struct gsta_gpio * chip,int nr)61 static inline struct gsta_regs __iomem *__regs(struct gsta_gpio *chip, int nr)
62 {
63 return chip->regs[nr / GSTA_GPIO_PER_BLOCK];
64 }
65
__bit(int nr)66 static inline u32 __bit(int nr)
67 {
68 return 1U << (nr % GSTA_GPIO_PER_BLOCK);
69 }
70
71 /*
72 * gpio methods
73 */
74
gsta_gpio_set(struct gpio_chip * gpio,unsigned nr,int val)75 static void gsta_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
76 {
77 struct gsta_gpio *chip = container_of(gpio, struct gsta_gpio, gpio);
78 struct gsta_regs __iomem *regs = __regs(chip, nr);
79 u32 bit = __bit(nr);
80
81 if (val)
82 writel(bit, ®s->dats);
83 else
84 writel(bit, ®s->datc);
85 }
86
gsta_gpio_get(struct gpio_chip * gpio,unsigned nr)87 static int gsta_gpio_get(struct gpio_chip *gpio, unsigned nr)
88 {
89 struct gsta_gpio *chip = container_of(gpio, struct gsta_gpio, gpio);
90 struct gsta_regs __iomem *regs = __regs(chip, nr);
91 u32 bit = __bit(nr);
92
93 return readl(®s->dat) & bit;
94 }
95
gsta_gpio_direction_output(struct gpio_chip * gpio,unsigned nr,int val)96 static int gsta_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
97 int val)
98 {
99 struct gsta_gpio *chip = container_of(gpio, struct gsta_gpio, gpio);
100 struct gsta_regs __iomem *regs = __regs(chip, nr);
101 u32 bit = __bit(nr);
102
103 writel(bit, ®s->dirs);
104 /* Data register after direction, otherwise pullup/down is selected */
105 if (val)
106 writel(bit, ®s->dats);
107 else
108 writel(bit, ®s->datc);
109 return 0;
110 }
111
gsta_gpio_direction_input(struct gpio_chip * gpio,unsigned nr)112 static int gsta_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
113 {
114 struct gsta_gpio *chip = container_of(gpio, struct gsta_gpio, gpio);
115 struct gsta_regs __iomem *regs = __regs(chip, nr);
116 u32 bit = __bit(nr);
117
118 writel(bit, ®s->dirc);
119 return 0;
120 }
121
gsta_gpio_to_irq(struct gpio_chip * gpio,unsigned offset)122 static int gsta_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
123 {
124 struct gsta_gpio *chip = container_of(gpio, struct gsta_gpio, gpio);
125 return chip->irq_base + offset;
126 }
127
gsta_gpio_setup(struct gsta_gpio * chip)128 static void gsta_gpio_setup(struct gsta_gpio *chip) /* called from probe */
129 {
130 struct gpio_chip *gpio = &chip->gpio;
131
132 /*
133 * ARCH_NR_GPIOS is currently 256 and dynamic allocation starts
134 * from the end. However, for compatibility, we need the first
135 * ConneXt device to start from gpio 0: it's the main chipset
136 * on most boards so documents and drivers assume gpio0..gpio127
137 */
138 static int gpio_base;
139
140 gpio->label = dev_name(chip->dev);
141 gpio->owner = THIS_MODULE;
142 gpio->direction_input = gsta_gpio_direction_input;
143 gpio->get = gsta_gpio_get;
144 gpio->direction_output = gsta_gpio_direction_output;
145 gpio->set = gsta_gpio_set;
146 gpio->dbg_show = NULL;
147 gpio->base = gpio_base;
148 gpio->ngpio = GSTA_NR_GPIO;
149 gpio->can_sleep = 0;
150 gpio->to_irq = gsta_gpio_to_irq;
151
152 /*
153 * After the first device, turn to dynamic gpio numbers.
154 * For example, with ARCH_NR_GPIOS = 256 we can fit two cards
155 */
156 if (!gpio_base)
157 gpio_base = -1;
158 }
159
160 /*
161 * Special method: alternate functions and pullup/pulldown. This is only
162 * invoked on startup to configure gpio's according to platform data.
163 * FIXME : this functionality shall be managed (and exported to other drivers)
164 * via the pin control subsystem.
165 */
gsta_set_config(struct gsta_gpio * chip,int nr,unsigned cfg)166 static void gsta_set_config(struct gsta_gpio *chip, int nr, unsigned cfg)
167 {
168 struct gsta_regs __iomem *regs = __regs(chip, nr);
169 unsigned long flags;
170 u32 bit = __bit(nr);
171 u32 val;
172 int err = 0;
173
174 pr_info("%s: %p %i %i\n", __func__, chip, nr, cfg);
175
176 if (cfg == PINMUX_TYPE_NONE)
177 return;
178
179 /* Alternate function or not? */
180 spin_lock_irqsave(&chip->lock, flags);
181 val = readl(®s->afsela);
182 if (cfg == PINMUX_TYPE_FUNCTION)
183 val |= bit;
184 else
185 val &= ~bit;
186 writel(val | bit, ®s->afsela);
187 if (cfg == PINMUX_TYPE_FUNCTION) {
188 spin_unlock_irqrestore(&chip->lock, flags);
189 return;
190 }
191
192 /* not alternate function: set details */
193 switch (cfg) {
194 case PINMUX_TYPE_OUTPUT_LOW:
195 writel(bit, ®s->dirs);
196 writel(bit, ®s->datc);
197 break;
198 case PINMUX_TYPE_OUTPUT_HIGH:
199 writel(bit, ®s->dirs);
200 writel(bit, ®s->dats);
201 break;
202 case PINMUX_TYPE_INPUT:
203 writel(bit, ®s->dirc);
204 val = readl(®s->pdis) | bit;
205 writel(val, ®s->pdis);
206 break;
207 case PINMUX_TYPE_INPUT_PULLUP:
208 writel(bit, ®s->dirc);
209 val = readl(®s->pdis) & ~bit;
210 writel(val, ®s->pdis);
211 writel(bit, ®s->dats);
212 break;
213 case PINMUX_TYPE_INPUT_PULLDOWN:
214 writel(bit, ®s->dirc);
215 val = readl(®s->pdis) & ~bit;
216 writel(val, ®s->pdis);
217 writel(bit, ®s->datc);
218 break;
219 default:
220 err = 1;
221 }
222 spin_unlock_irqrestore(&chip->lock, flags);
223 if (err)
224 pr_err("%s: chip %p, pin %i, cfg %i is invalid\n",
225 __func__, chip, nr, cfg);
226 }
227
228 /*
229 * Irq methods
230 */
231
gsta_irq_disable(struct irq_data * data)232 static void gsta_irq_disable(struct irq_data *data)
233 {
234 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
235 struct gsta_gpio *chip = gc->private;
236 int nr = data->irq - chip->irq_base;
237 struct gsta_regs __iomem *regs = __regs(chip, nr);
238 u32 bit = __bit(nr);
239 u32 val;
240 unsigned long flags;
241
242 spin_lock_irqsave(&chip->lock, flags);
243 if (chip->irq_type[nr] & IRQ_TYPE_EDGE_RISING) {
244 val = readl(®s->rimsc) & ~bit;
245 writel(val, ®s->rimsc);
246 }
247 if (chip->irq_type[nr] & IRQ_TYPE_EDGE_FALLING) {
248 val = readl(®s->fimsc) & ~bit;
249 writel(val, ®s->fimsc);
250 }
251 spin_unlock_irqrestore(&chip->lock, flags);
252 return;
253 }
254
gsta_irq_enable(struct irq_data * data)255 static void gsta_irq_enable(struct irq_data *data)
256 {
257 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
258 struct gsta_gpio *chip = gc->private;
259 int nr = data->irq - chip->irq_base;
260 struct gsta_regs __iomem *regs = __regs(chip, nr);
261 u32 bit = __bit(nr);
262 u32 val;
263 int type;
264 unsigned long flags;
265
266 type = chip->irq_type[nr];
267
268 spin_lock_irqsave(&chip->lock, flags);
269 val = readl(®s->rimsc);
270 if (type & IRQ_TYPE_EDGE_RISING)
271 writel(val | bit, ®s->rimsc);
272 else
273 writel(val & ~bit, ®s->rimsc);
274 val = readl(®s->rimsc);
275 if (type & IRQ_TYPE_EDGE_FALLING)
276 writel(val | bit, ®s->fimsc);
277 else
278 writel(val & ~bit, ®s->fimsc);
279 spin_unlock_irqrestore(&chip->lock, flags);
280 return;
281 }
282
gsta_irq_type(struct irq_data * d,unsigned int type)283 static int gsta_irq_type(struct irq_data *d, unsigned int type)
284 {
285 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
286 struct gsta_gpio *chip = gc->private;
287 int nr = d->irq - chip->irq_base;
288
289 /* We only support edge interrupts */
290 if (!(type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))) {
291 pr_debug("%s: unsupported type 0x%x\n", __func__, type);
292 return -EINVAL;
293 }
294
295 chip->irq_type[nr] = type; /* used for enable/disable */
296
297 gsta_irq_enable(d);
298 return 0;
299 }
300
gsta_gpio_handler(int irq,void * dev_id)301 static irqreturn_t gsta_gpio_handler(int irq, void *dev_id)
302 {
303 struct gsta_gpio *chip = dev_id;
304 struct gsta_regs __iomem *regs;
305 u32 is;
306 int i, nr, base;
307 irqreturn_t ret = IRQ_NONE;
308
309 for (i = 0; i < GSTA_NR_BLOCKS; i++) {
310 regs = chip->regs[i];
311 base = chip->irq_base + i * GSTA_GPIO_PER_BLOCK;
312 while ((is = readl(®s->is))) {
313 nr = __ffs(is);
314 irq = base + nr;
315 generic_handle_irq(irq);
316 writel(1 << nr, ®s->ic);
317 ret = IRQ_HANDLED;
318 }
319 }
320 return ret;
321 }
322
gsta_alloc_irq_chip(struct gsta_gpio * chip)323 static void gsta_alloc_irq_chip(struct gsta_gpio *chip)
324 {
325 struct irq_chip_generic *gc;
326 struct irq_chip_type *ct;
327
328 gc = irq_alloc_generic_chip(KBUILD_MODNAME, 1, chip->irq_base,
329 chip->reg_base, handle_simple_irq);
330 gc->private = chip;
331 ct = gc->chip_types;
332
333 ct->chip.irq_set_type = gsta_irq_type;
334 ct->chip.irq_disable = gsta_irq_disable;
335 ct->chip.irq_enable = gsta_irq_enable;
336
337 /* FIXME: this makes at most 32 interrupts. Request 0 by now */
338 irq_setup_generic_chip(gc, 0 /* IRQ_MSK(GSTA_GPIO_PER_BLOCK) */, 0,
339 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
340
341 /* Set up all all 128 interrupts: code from setup_generic_chip */
342 {
343 struct irq_chip_type *ct = gc->chip_types;
344 int i, j;
345 for (j = 0; j < GSTA_NR_GPIO; j++) {
346 i = chip->irq_base + j;
347 irq_set_chip_and_handler(i, &ct->chip, ct->handler);
348 irq_set_chip_data(i, gc);
349 irq_modify_status(i, IRQ_NOREQUEST | IRQ_NOPROBE, 0);
350 }
351 gc->irq_cnt = i - gc->irq_base;
352 }
353 }
354
355 /* The platform device used here is instantiated by the MFD device */
gsta_probe(struct platform_device * dev)356 static int gsta_probe(struct platform_device *dev)
357 {
358 int i, err;
359 struct pci_dev *pdev;
360 struct sta2x11_gpio_pdata *gpio_pdata;
361 struct gsta_gpio *chip;
362 struct resource *res;
363
364 pdev = *(struct pci_dev **)(dev->dev.platform_data);
365 gpio_pdata = dev_get_platdata(&pdev->dev);
366
367 if (gpio_pdata == NULL)
368 dev_err(&dev->dev, "no gpio config\n");
369 pr_debug("gpio config: %p\n", gpio_pdata);
370
371 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
372
373 chip = devm_kzalloc(&dev->dev, sizeof(*chip), GFP_KERNEL);
374 chip->dev = &dev->dev;
375 chip->reg_base = devm_request_and_ioremap(&dev->dev, res);
376
377 for (i = 0; i < GSTA_NR_BLOCKS; i++) {
378 chip->regs[i] = chip->reg_base + i * 4096;
379 /* disable all irqs */
380 writel(0, &chip->regs[i]->rimsc);
381 writel(0, &chip->regs[i]->fimsc);
382 writel(~0, &chip->regs[i]->ic);
383 }
384 spin_lock_init(&chip->lock);
385 gsta_gpio_setup(chip);
386 if (gpio_pdata)
387 for (i = 0; i < GSTA_NR_GPIO; i++)
388 gsta_set_config(chip, i, gpio_pdata->pinconfig[i]);
389
390 /* 384 was used in previous code: be compatible for other drivers */
391 err = irq_alloc_descs(-1, 384, GSTA_NR_GPIO, NUMA_NO_NODE);
392 if (err < 0) {
393 dev_warn(&dev->dev, "sta2x11 gpio: Can't get irq base (%i)\n",
394 -err);
395 return err;
396 }
397 chip->irq_base = err;
398 gsta_alloc_irq_chip(chip);
399
400 err = request_irq(pdev->irq, gsta_gpio_handler,
401 IRQF_SHARED, KBUILD_MODNAME, chip);
402 if (err < 0) {
403 dev_err(&dev->dev, "sta2x11 gpio: Can't request irq (%i)\n",
404 -err);
405 goto err_free_descs;
406 }
407
408 err = gpiochip_add(&chip->gpio);
409 if (err < 0) {
410 dev_err(&dev->dev, "sta2x11 gpio: Can't register (%i)\n",
411 -err);
412 goto err_free_irq;
413 }
414
415 platform_set_drvdata(dev, chip);
416 return 0;
417
418 err_free_irq:
419 free_irq(pdev->irq, chip);
420 err_free_descs:
421 irq_free_descs(chip->irq_base, GSTA_NR_GPIO);
422 return err;
423 }
424
425 static struct platform_driver sta2x11_gpio_platform_driver = {
426 .driver = {
427 .name = "sta2x11-gpio",
428 .owner = THIS_MODULE,
429 },
430 .probe = gsta_probe,
431 };
432
433 module_platform_driver(sta2x11_gpio_platform_driver);
434
435 MODULE_LICENSE("GPL v2");
436 MODULE_DESCRIPTION("sta2x11_gpio GPIO driver");
437