1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <subdev/bios.h>
26 #include <subdev/bus.h>
27 #include <subdev/gpio.h>
28 #include <subdev/i2c.h>
29 #include <subdev/clock.h>
30 #include <subdev/therm.h>
31 #include <subdev/mxm.h>
32 #include <subdev/devinit.h>
33 #include <subdev/mc.h>
34 #include <subdev/timer.h>
35 #include <subdev/fb.h>
36 #include <subdev/instmem.h>
37 #include <subdev/vm.h>
38 #include <subdev/bar.h>
39
40 #include <engine/device.h>
41 #include <engine/dmaobj.h>
42 #include <engine/fifo.h>
43 #include <engine/software.h>
44 #include <engine/graph.h>
45 #include <engine/mpeg.h>
46 #include <engine/vp.h>
47 #include <engine/crypt.h>
48 #include <engine/bsp.h>
49 #include <engine/ppp.h>
50 #include <engine/copy.h>
51 #include <engine/disp.h>
52
53 int
nv50_identify(struct nouveau_device * device)54 nv50_identify(struct nouveau_device *device)
55 {
56 switch (device->chipset) {
57 case 0x50:
58 device->cname = "G80";
59 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
60 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
61 device->oclass[NVDEV_SUBDEV_I2C ] = &nv50_i2c_oclass;
62 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
63 device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
64 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
65 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
66 device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
67 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
68 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
69 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
70 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
71 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
72 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
73 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
74 device->oclass[NVDEV_ENGINE_FIFO ] = &nv50_fifo_oclass;
75 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
76 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
77 device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
78 device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
79 break;
80 case 0x84:
81 device->cname = "G84";
82 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
83 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
84 device->oclass[NVDEV_SUBDEV_I2C ] = &nv50_i2c_oclass;
85 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
86 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
87 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
88 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
89 device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
90 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
91 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
92 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
93 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
94 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
95 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
96 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
97 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
98 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
99 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
100 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
101 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
102 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
103 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
104 device->oclass[NVDEV_ENGINE_DISP ] = &nv84_disp_oclass;
105 break;
106 case 0x86:
107 device->cname = "G86";
108 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
109 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
110 device->oclass[NVDEV_SUBDEV_I2C ] = &nv50_i2c_oclass;
111 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
112 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
113 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
114 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
115 device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
116 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
117 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
118 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
119 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
120 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
121 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
122 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
123 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
124 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
125 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
126 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
127 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
128 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
129 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
130 device->oclass[NVDEV_ENGINE_DISP ] = &nv84_disp_oclass;
131 break;
132 case 0x92:
133 device->cname = "G92";
134 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
135 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
136 device->oclass[NVDEV_SUBDEV_I2C ] = &nv50_i2c_oclass;
137 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
138 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
139 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
140 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
141 device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
142 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
143 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
144 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
145 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
146 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
147 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
148 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
149 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
150 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
151 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
152 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
153 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
154 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
155 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
156 device->oclass[NVDEV_ENGINE_DISP ] = &nv84_disp_oclass;
157 break;
158 case 0x94:
159 device->cname = "G94";
160 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
161 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
162 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
163 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
164 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
165 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
166 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
167 device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
168 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
169 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
170 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
171 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
172 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
173 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
174 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
175 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
176 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
177 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
178 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
179 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
180 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
181 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
182 device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass;
183 break;
184 case 0x96:
185 device->cname = "G96";
186 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
187 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
188 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
189 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
190 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
191 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
192 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
193 device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
194 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
195 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
196 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
197 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
198 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
199 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
200 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
201 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
202 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
203 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
204 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
205 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
206 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
207 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
208 device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass;
209 break;
210 case 0x98:
211 device->cname = "G98";
212 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
213 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
214 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
215 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
216 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
217 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
218 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
219 device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
220 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
221 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
222 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
223 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
224 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
225 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
226 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
227 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
228 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
229 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
230 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
231 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
232 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
233 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
234 device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass;
235 break;
236 case 0xa0:
237 device->cname = "G200";
238 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
239 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
240 device->oclass[NVDEV_SUBDEV_I2C ] = &nv50_i2c_oclass;
241 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
242 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
243 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
244 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
245 device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
246 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
247 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
248 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
249 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
250 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
251 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
252 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
253 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
254 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
255 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
256 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
257 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
258 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
259 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
260 device->oclass[NVDEV_ENGINE_DISP ] = &nva0_disp_oclass;
261 break;
262 case 0xaa:
263 device->cname = "MCP77/MCP78";
264 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
265 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
266 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
267 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
268 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
269 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
270 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
271 device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
272 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
273 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
274 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
275 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
276 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
277 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
278 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
279 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
280 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
281 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
282 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
283 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
284 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
285 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
286 device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass;
287 break;
288 case 0xac:
289 device->cname = "MCP79/MCP7A";
290 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
291 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
292 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
293 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
294 device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
295 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
296 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
297 device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
298 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
299 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
300 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
301 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
302 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
303 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
304 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
305 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
306 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
307 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
308 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
309 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
310 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
311 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
312 device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass;
313 break;
314 case 0xa3:
315 device->cname = "GT215";
316 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
317 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
318 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
319 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
320 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
321 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
322 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
323 device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
324 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
325 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
326 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
327 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
328 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
329 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
330 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
331 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
332 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
333 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
334 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
335 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
336 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
337 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
338 device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
339 device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
340 break;
341 case 0xa5:
342 device->cname = "GT216";
343 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
344 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
345 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
346 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
347 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
348 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
349 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
350 device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
351 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
352 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
353 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
354 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
355 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
356 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
357 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
358 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
359 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
360 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
361 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
362 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
363 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
364 device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
365 device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
366 break;
367 case 0xa8:
368 device->cname = "GT218";
369 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
370 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
371 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
372 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
373 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
374 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
375 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
376 device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
377 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
378 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
379 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
380 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
381 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
382 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
383 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
384 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
385 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
386 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
387 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
388 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
389 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
390 device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
391 device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
392 break;
393 case 0xaf:
394 device->cname = "MCP89";
395 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
396 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
397 device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
398 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
399 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
400 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
401 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
402 device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
403 device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
404 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
405 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
406 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
407 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
408 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
409 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
410 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
411 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
412 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
413 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
414 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
415 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
416 device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
417 device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
418 break;
419 default:
420 nv_fatal(device, "unknown Tesla chipset\n");
421 return -EINVAL;
422 }
423
424 return 0;
425 }
426