1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <core/os.h>
26 #include <core/class.h>
27
28 #include <subdev/bios.h>
29 #include <subdev/bios/dcb.h>
30 #include <subdev/timer.h>
31
32 #include "nv50.h"
33
34 int
nv50_dac_power(struct nv50_disp_priv * priv,int or,u32 data)35 nv50_dac_power(struct nv50_disp_priv *priv, int or, u32 data)
36 {
37 const u32 stat = (data & NV50_DISP_DAC_PWR_HSYNC) |
38 (data & NV50_DISP_DAC_PWR_VSYNC) |
39 (data & NV50_DISP_DAC_PWR_DATA) |
40 (data & NV50_DISP_DAC_PWR_STATE);
41 const u32 doff = (or * 0x800);
42 nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);
43 nv_mask(priv, 0x61a004 + doff, 0xc000007f, 0x80000000 | stat);
44 nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);
45 return 0;
46 }
47
48 int
nv50_dac_sense(struct nv50_disp_priv * priv,int or,u32 loadval)49 nv50_dac_sense(struct nv50_disp_priv *priv, int or, u32 loadval)
50 {
51 const u32 doff = (or * 0x800);
52 int load = -EINVAL;
53 nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80150000);
54 nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);
55 nv_wr32(priv, 0x61a00c + doff, 0x00100000 | loadval);
56 mdelay(9);
57 udelay(500);
58 nv_wr32(priv, 0x61a00c + doff, 0x80000000);
59 load = (nv_rd32(priv, 0x61a00c + doff) & 0x38000000) >> 27;
60 nv_wr32(priv, 0x61a00c + doff, 0x00000000);
61 nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80550000);
62 nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);
63 return load;
64 }
65
66 int
nv50_dac_mthd(struct nouveau_object * object,u32 mthd,void * args,u32 size)67 nv50_dac_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size)
68 {
69 struct nv50_disp_priv *priv = (void *)object->engine;
70 const u8 or = (mthd & NV50_DISP_DAC_MTHD_OR);
71 u32 *data = args;
72 int ret;
73
74 if (size < sizeof(u32))
75 return -EINVAL;
76
77 switch (mthd & ~0x3f) {
78 case NV50_DISP_DAC_PWR:
79 ret = priv->dac.power(priv, or, data[0]);
80 break;
81 case NV50_DISP_DAC_LOAD:
82 ret = priv->dac.sense(priv, or, data[0]);
83 if (ret >= 0) {
84 data[0] = ret;
85 ret = 0;
86 }
87 break;
88 default:
89 BUG_ON(1);
90 }
91
92 return ret;
93 }
94