1 #ifndef __NVKM_DISP_DPORT_H__ 2 #define __NVKM_DISP_DPORT_H__ 3 4 /* DPCD Receiver Capabilities */ 5 #define DPCD_RC00 0x00000 6 #define DPCD_RC00_DPCD_REV 0xff 7 #define DPCD_RC01 0x00001 8 #define DPCD_RC01_MAX_LINK_RATE 0xff 9 #define DPCD_RC02 0x00002 10 #define DPCD_RC02_ENHANCED_FRAME_CAP 0x80 11 #define DPCD_RC02_MAX_LANE_COUNT 0x1f 12 #define DPCD_RC03 0x00003 13 #define DPCD_RC03_MAX_DOWNSPREAD 0x01 14 15 /* DPCD Link Configuration */ 16 #define DPCD_LC00 0x00100 17 #define DPCD_LC00_LINK_BW_SET 0xff 18 #define DPCD_LC01 0x00101 19 #define DPCD_LC01_ENHANCED_FRAME_EN 0x80 20 #define DPCD_LC01_LANE_COUNT_SET 0x1f 21 #define DPCD_LC02 0x00102 22 #define DPCD_LC02_TRAINING_PATTERN_SET 0x03 23 #define DPCD_LC03(l) ((l) + 0x00103) 24 #define DPCD_LC03_MAX_PRE_EMPHASIS_REACHED 0x20 25 #define DPCD_LC03_PRE_EMPHASIS_SET 0x18 26 #define DPCD_LC03_MAX_SWING_REACHED 0x04 27 #define DPCD_LC03_VOLTAGE_SWING_SET 0x03 28 29 /* DPCD Link/Sink Status */ 30 #define DPCD_LS02 0x00202 31 #define DPCD_LS02_LANE1_SYMBOL_LOCKED 0x40 32 #define DPCD_LS02_LANE1_CHANNEL_EQ_DONE 0x20 33 #define DPCD_LS02_LANE1_CR_DONE 0x10 34 #define DPCD_LS02_LANE0_SYMBOL_LOCKED 0x04 35 #define DPCD_LS02_LANE0_CHANNEL_EQ_DONE 0x02 36 #define DPCD_LS02_LANE0_CR_DONE 0x01 37 #define DPCD_LS03 0x00203 38 #define DPCD_LS03_LANE3_SYMBOL_LOCKED 0x40 39 #define DPCD_LS03_LANE3_CHANNEL_EQ_DONE 0x20 40 #define DPCD_LS03_LANE3_CR_DONE 0x10 41 #define DPCD_LS03_LANE2_SYMBOL_LOCKED 0x04 42 #define DPCD_LS03_LANE2_CHANNEL_EQ_DONE 0x02 43 #define DPCD_LS03_LANE2_CR_DONE 0x01 44 #define DPCD_LS04 0x00204 45 #define DPCD_LS04_LINK_STATUS_UPDATED 0x80 46 #define DPCD_LS04_DOWNSTREAM_PORT_STATUS_CHANGED 0x40 47 #define DPCD_LS04_INTERLANE_ALIGN_DONE 0x01 48 #define DPCD_LS06 0x00206 49 #define DPCD_LS06_LANE1_PRE_EMPHASIS 0xc0 50 #define DPCD_LS06_LANE1_VOLTAGE_SWING 0x30 51 #define DPCD_LS06_LANE0_PRE_EMPHASIS 0x0c 52 #define DPCD_LS06_LANE0_VOLTAGE_SWING 0x03 53 #define DPCD_LS07 0x00207 54 #define DPCD_LS07_LANE3_PRE_EMPHASIS 0xc0 55 #define DPCD_LS07_LANE3_VOLTAGE_SWING 0x30 56 #define DPCD_LS07_LANE2_PRE_EMPHASIS 0x0c 57 #define DPCD_LS07_LANE2_VOLTAGE_SWING 0x03 58 59 struct nouveau_disp; 60 struct dcb_output; 61 62 struct nouveau_dp_func { 63 int (*pattern)(struct nouveau_disp *, struct dcb_output *, 64 int head, int pattern); 65 int (*lnk_ctl)(struct nouveau_disp *, struct dcb_output *, int head, 66 int link_nr, int link_bw, bool enh_frame); 67 int (*drv_ctl)(struct nouveau_disp *, struct dcb_output *, int head, 68 int lane, int swing, int preem); 69 }; 70 71 extern const struct nouveau_dp_func nv94_sor_dp_func; 72 extern const struct nouveau_dp_func nvd0_sor_dp_func; 73 extern const struct nouveau_dp_func nv50_pior_dp_func; 74 75 int nouveau_dp_train(struct nouveau_disp *, const struct nouveau_dp_func *, 76 struct dcb_output *, int, u32); 77 78 #endif 79