1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <core/gpuobj.h>
26
27 #include <subdev/timer.h>
28 #include <subdev/bar.h>
29 #include <subdev/fb.h>
30 #include <subdev/vm.h>
31
32 struct nvc0_bar_priv {
33 struct nouveau_bar base;
34 spinlock_t lock;
35 struct {
36 struct nouveau_gpuobj *mem;
37 struct nouveau_gpuobj *pgd;
38 struct nouveau_vm *vm;
39 } bar[2];
40 };
41
42 static int
nvc0_bar_kmap(struct nouveau_bar * bar,struct nouveau_mem * mem,u32 flags,struct nouveau_vma * vma)43 nvc0_bar_kmap(struct nouveau_bar *bar, struct nouveau_mem *mem,
44 u32 flags, struct nouveau_vma *vma)
45 {
46 struct nvc0_bar_priv *priv = (void *)bar;
47 int ret;
48
49 ret = nouveau_vm_get(priv->bar[0].vm, mem->size << 12, 12, flags, vma);
50 if (ret)
51 return ret;
52
53 nouveau_vm_map(vma, mem);
54 nvc0_vm_flush_engine(nv_subdev(bar), priv->bar[0].pgd->addr, 5);
55 return 0;
56 }
57
58 static int
nvc0_bar_umap(struct nouveau_bar * bar,struct nouveau_mem * mem,u32 flags,struct nouveau_vma * vma)59 nvc0_bar_umap(struct nouveau_bar *bar, struct nouveau_mem *mem,
60 u32 flags, struct nouveau_vma *vma)
61 {
62 struct nvc0_bar_priv *priv = (void *)bar;
63 int ret;
64
65 ret = nouveau_vm_get(priv->bar[1].vm, mem->size << 12,
66 mem->page_shift, flags, vma);
67 if (ret)
68 return ret;
69
70 nouveau_vm_map(vma, mem);
71 nvc0_vm_flush_engine(nv_subdev(bar), priv->bar[1].pgd->addr, 5);
72 return 0;
73 }
74
75 static void
nvc0_bar_unmap(struct nouveau_bar * bar,struct nouveau_vma * vma)76 nvc0_bar_unmap(struct nouveau_bar *bar, struct nouveau_vma *vma)
77 {
78 struct nvc0_bar_priv *priv = (void *)bar;
79 int i = !(vma->vm == priv->bar[0].vm);
80
81 nouveau_vm_unmap(vma);
82 nvc0_vm_flush_engine(nv_subdev(bar), priv->bar[i].pgd->addr, 5);
83 nouveau_vm_put(vma);
84 }
85
86 static int
nvc0_bar_ctor(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void * data,u32 size,struct nouveau_object ** pobject)87 nvc0_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
88 struct nouveau_oclass *oclass, void *data, u32 size,
89 struct nouveau_object **pobject)
90 {
91 struct nouveau_device *device = nv_device(parent);
92 struct pci_dev *pdev = device->pdev;
93 struct nvc0_bar_priv *priv;
94 struct nouveau_gpuobj *mem;
95 struct nouveau_vm *vm;
96 int ret;
97
98 ret = nouveau_bar_create(parent, engine, oclass, &priv);
99 *pobject = nv_object(priv);
100 if (ret)
101 return ret;
102
103 /* BAR3 */
104 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0,
105 &priv->bar[0].mem);
106 mem = priv->bar[0].mem;
107 if (ret)
108 return ret;
109
110 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0,
111 &priv->bar[0].pgd);
112 if (ret)
113 return ret;
114
115 ret = nouveau_vm_new(device, 0, pci_resource_len(pdev, 3), 0, &vm);
116 if (ret)
117 return ret;
118
119 ret = nouveau_gpuobj_new(nv_object(priv), NULL,
120 (pci_resource_len(pdev, 3) >> 12) * 8,
121 0x1000, NVOBJ_FLAG_ZERO_ALLOC,
122 &vm->pgt[0].obj[0]);
123 vm->pgt[0].refcount[0] = 1;
124 if (ret)
125 return ret;
126
127 ret = nouveau_vm_ref(vm, &priv->bar[0].vm, priv->bar[0].pgd);
128 nouveau_vm_ref(NULL, &vm, NULL);
129 if (ret)
130 return ret;
131
132 nv_wo32(mem, 0x0200, lower_32_bits(priv->bar[0].pgd->addr));
133 nv_wo32(mem, 0x0204, upper_32_bits(priv->bar[0].pgd->addr));
134 nv_wo32(mem, 0x0208, lower_32_bits(pci_resource_len(pdev, 3) - 1));
135 nv_wo32(mem, 0x020c, upper_32_bits(pci_resource_len(pdev, 3) - 1));
136
137 /* BAR1 */
138 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0,
139 &priv->bar[1].mem);
140 mem = priv->bar[1].mem;
141 if (ret)
142 return ret;
143
144 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0,
145 &priv->bar[1].pgd);
146 if (ret)
147 return ret;
148
149 ret = nouveau_vm_new(device, 0, pci_resource_len(pdev, 1), 0, &vm);
150 if (ret)
151 return ret;
152
153 ret = nouveau_vm_ref(vm, &priv->bar[1].vm, priv->bar[1].pgd);
154 nouveau_vm_ref(NULL, &vm, NULL);
155 if (ret)
156 return ret;
157
158 nv_wo32(mem, 0x0200, lower_32_bits(priv->bar[1].pgd->addr));
159 nv_wo32(mem, 0x0204, upper_32_bits(priv->bar[1].pgd->addr));
160 nv_wo32(mem, 0x0208, lower_32_bits(pci_resource_len(pdev, 1) - 1));
161 nv_wo32(mem, 0x020c, upper_32_bits(pci_resource_len(pdev, 1) - 1));
162
163 priv->base.alloc = nouveau_bar_alloc;
164 priv->base.kmap = nvc0_bar_kmap;
165 priv->base.umap = nvc0_bar_umap;
166 priv->base.unmap = nvc0_bar_unmap;
167 priv->base.flush = nv84_bar_flush;
168 spin_lock_init(&priv->lock);
169 return 0;
170 }
171
172 static void
nvc0_bar_dtor(struct nouveau_object * object)173 nvc0_bar_dtor(struct nouveau_object *object)
174 {
175 struct nvc0_bar_priv *priv = (void *)object;
176
177 nouveau_vm_ref(NULL, &priv->bar[1].vm, priv->bar[1].pgd);
178 nouveau_gpuobj_ref(NULL, &priv->bar[1].pgd);
179 nouveau_gpuobj_ref(NULL, &priv->bar[1].mem);
180
181 if (priv->bar[0].vm) {
182 nouveau_gpuobj_ref(NULL, &priv->bar[0].vm->pgt[0].obj[0]);
183 nouveau_vm_ref(NULL, &priv->bar[0].vm, priv->bar[0].pgd);
184 }
185 nouveau_gpuobj_ref(NULL, &priv->bar[0].pgd);
186 nouveau_gpuobj_ref(NULL, &priv->bar[0].mem);
187
188 nouveau_bar_destroy(&priv->base);
189 }
190
191 static int
nvc0_bar_init(struct nouveau_object * object)192 nvc0_bar_init(struct nouveau_object *object)
193 {
194 struct nvc0_bar_priv *priv = (void *)object;
195 int ret;
196
197 ret = nouveau_bar_init(&priv->base);
198 if (ret)
199 return ret;
200
201 nv_mask(priv, 0x000200, 0x00000100, 0x00000000);
202 nv_mask(priv, 0x000200, 0x00000100, 0x00000100);
203 nv_mask(priv, 0x100c80, 0x00000001, 0x00000000);
204
205 nv_wr32(priv, 0x001704, 0x80000000 | priv->bar[1].mem->addr >> 12);
206 nv_wr32(priv, 0x001714, 0xc0000000 | priv->bar[0].mem->addr >> 12);
207 return 0;
208 }
209
210 struct nouveau_oclass
211 nvc0_bar_oclass = {
212 .handle = NV_SUBDEV(BAR, 0xc0),
213 .ofuncs = &(struct nouveau_ofuncs) {
214 .ctor = nvc0_bar_ctor,
215 .dtor = nvc0_bar_dtor,
216 .init = nvc0_bar_init,
217 .fini = _nouveau_bar_fini,
218 },
219 };
220