1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25 #include <subdev/bios.h>
26 #include <subdev/bios/bit.h>
27 #include <subdev/bios/mxm.h>
28
29 u16
mxm_table(struct nouveau_bios * bios,u8 * ver,u8 * hdr)30 mxm_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr)
31 {
32 struct bit_entry x;
33
34 if (bit_entry(bios, 'x', &x)) {
35 nv_debug(bios, "BIT 'x' table not present\n");
36 return 0x0000;
37 }
38
39 *ver = x.version;
40 *hdr = x.length;
41 if (*ver != 1 || *hdr < 3) {
42 nv_warn(bios, "BIT 'x' table %d/%d unknown\n", *ver, *hdr);
43 return 0x0000;
44 }
45
46 return x.offset;
47 }
48
49 /* These map MXM v2.x digital connection values to the appropriate SOR/link,
50 * hopefully they're correct for all boards within the same chipset...
51 *
52 * MXM v3.x VBIOS are nicer and provide pointers to these tables.
53 */
54 static u8 nv84_sor_map[16] = {
55 0x00, 0x12, 0x22, 0x11, 0x32, 0x31, 0x11, 0x31,
56 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
57 };
58
59 static u8 nv92_sor_map[16] = {
60 0x00, 0x12, 0x22, 0x11, 0x32, 0x31, 0x11, 0x31,
61 0x11, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
62 };
63
64 static u8 nv94_sor_map[16] = {
65 0x00, 0x14, 0x24, 0x11, 0x34, 0x31, 0x11, 0x31,
66 0x11, 0x31, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00
67 };
68
69 static u8 nv98_sor_map[16] = {
70 0x00, 0x14, 0x12, 0x11, 0x00, 0x31, 0x11, 0x31,
71 0x11, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
72 };
73
74 u8
mxm_sor_map(struct nouveau_bios * bios,u8 conn)75 mxm_sor_map(struct nouveau_bios *bios, u8 conn)
76 {
77 u8 ver, hdr;
78 u16 mxm = mxm_table(bios, &ver, &hdr);
79 if (mxm && hdr >= 6) {
80 u16 map = nv_ro16(bios, mxm + 4);
81 if (map) {
82 ver = nv_ro08(bios, map);
83 if (ver == 0x10) {
84 if (conn < nv_ro08(bios, map + 3)) {
85 map += nv_ro08(bios, map + 1);
86 map += conn;
87 return nv_ro08(bios, map);
88 }
89
90 return 0x00;
91 }
92
93 nv_warn(bios, "unknown sor map v%02x\n", ver);
94 }
95 }
96
97 if (bios->version.chip == 0x84 || bios->version.chip == 0x86)
98 return nv84_sor_map[conn];
99 if (bios->version.chip == 0x92)
100 return nv92_sor_map[conn];
101 if (bios->version.chip == 0x94 || bios->version.chip == 0x96)
102 return nv94_sor_map[conn];
103 if (bios->version.chip == 0x98)
104 return nv98_sor_map[conn];
105
106 nv_warn(bios, "missing sor map\n");
107 return 0x00;
108 }
109
110 u8
mxm_ddc_map(struct nouveau_bios * bios,u8 port)111 mxm_ddc_map(struct nouveau_bios *bios, u8 port)
112 {
113 u8 ver, hdr;
114 u16 mxm = mxm_table(bios, &ver, &hdr);
115 if (mxm && hdr >= 8) {
116 u16 map = nv_ro16(bios, mxm + 6);
117 if (map) {
118 ver = nv_ro08(bios, map);
119 if (ver == 0x10) {
120 if (port < nv_ro08(bios, map + 3)) {
121 map += nv_ro08(bios, map + 1);
122 map += port;
123 return nv_ro08(bios, map);
124 }
125
126 return 0x00;
127 }
128
129 nv_warn(bios, "unknown ddc map v%02x\n", ver);
130 }
131 }
132
133 /* v2.x: directly write port as dcb i2cidx */
134 return (port << 4) | port;
135 }
136