1 /*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * Copyright(c) 2012 Intel Corporation. All rights reserved.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * BSD LICENSE
25 *
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions
28 * are met:
29 *
30 * * Redistributions of source code must retain the above copyright
31 * notice, this list of conditions and the following disclaimer.
32 * * Redistributions in binary form must reproduce the above copyright
33 * notice, this list of conditions and the following disclaimer in
34 * the documentation and/or other materials provided with the
35 * distribution.
36 * * Neither the name of Intel Corporation nor the names of its
37 * contributors may be used to endorse or promote products derived
38 * from this software without specific prior written permission.
39 *
40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
41 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
42 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
43 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
44 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
45 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
46 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 */
52
53 /*
54 * Supports the SMBus Message Transport (SMT) in the Intel Atom Processor
55 * S12xx Product Family.
56 *
57 * Features supported by this driver:
58 * Hardware PEC yes
59 * Block buffer yes
60 * Block process call transaction no
61 * Slave mode no
62 */
63
64 #include <linux/module.h>
65 #include <linux/init.h>
66 #include <linux/pci.h>
67 #include <linux/kernel.h>
68 #include <linux/stddef.h>
69 #include <linux/completion.h>
70 #include <linux/dma-mapping.h>
71 #include <linux/i2c.h>
72 #include <linux/acpi.h>
73 #include <linux/interrupt.h>
74
75 #include <asm-generic/io-64-nonatomic-lo-hi.h>
76
77 /* PCI Address Constants */
78 #define SMBBAR 0
79
80 /* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */
81 #define PCI_DEVICE_ID_INTEL_S1200_SMT0 0x0c59
82 #define PCI_DEVICE_ID_INTEL_S1200_SMT1 0x0c5a
83 #define PCI_DEVICE_ID_INTEL_AVOTON_SMT 0x1f15
84
85 #define ISMT_DESC_ENTRIES 32 /* number of descriptor entries */
86 #define ISMT_MAX_RETRIES 3 /* number of SMBus retries to attempt */
87
88 /* Hardware Descriptor Constants - Control Field */
89 #define ISMT_DESC_CWRL 0x01 /* Command/Write Length */
90 #define ISMT_DESC_BLK 0X04 /* Perform Block Transaction */
91 #define ISMT_DESC_FAIR 0x08 /* Set fairness flag upon successful arbit. */
92 #define ISMT_DESC_PEC 0x10 /* Packet Error Code */
93 #define ISMT_DESC_I2C 0x20 /* I2C Enable */
94 #define ISMT_DESC_INT 0x40 /* Interrupt */
95 #define ISMT_DESC_SOE 0x80 /* Stop On Error */
96
97 /* Hardware Descriptor Constants - Status Field */
98 #define ISMT_DESC_SCS 0x01 /* Success */
99 #define ISMT_DESC_DLTO 0x04 /* Data Low Time Out */
100 #define ISMT_DESC_NAK 0x08 /* NAK Received */
101 #define ISMT_DESC_CRC 0x10 /* CRC Error */
102 #define ISMT_DESC_CLTO 0x20 /* Clock Low Time Out */
103 #define ISMT_DESC_COL 0x40 /* Collisions */
104 #define ISMT_DESC_LPR 0x80 /* Large Packet Received */
105
106 /* Macros */
107 #define ISMT_DESC_ADDR_RW(addr, rw) (((addr) << 1) | (rw))
108
109 /* iSMT General Register address offsets (SMBBAR + <addr>) */
110 #define ISMT_GR_GCTRL 0x000 /* General Control */
111 #define ISMT_GR_SMTICL 0x008 /* SMT Interrupt Cause Location */
112 #define ISMT_GR_ERRINTMSK 0x010 /* Error Interrupt Mask */
113 #define ISMT_GR_ERRAERMSK 0x014 /* Error AER Mask */
114 #define ISMT_GR_ERRSTS 0x018 /* Error Status */
115 #define ISMT_GR_ERRINFO 0x01c /* Error Information */
116
117 /* iSMT Master Registers */
118 #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */
119 #define ISMT_MSTR_MCTRL 0x108 /* Master Control */
120 #define ISMT_MSTR_MSTS 0x10c /* Master Status */
121 #define ISMT_MSTR_MDS 0x110 /* Master Descriptor Size */
122 #define ISMT_MSTR_RPOLICY 0x114 /* Retry Policy */
123
124 /* iSMT Miscellaneous Registers */
125 #define ISMT_SPGT 0x300 /* SMBus PHY Global Timing */
126
127 /* General Control Register (GCTRL) bit definitions */
128 #define ISMT_GCTRL_TRST 0x04 /* Target Reset */
129 #define ISMT_GCTRL_KILL 0x08 /* Kill */
130 #define ISMT_GCTRL_SRST 0x40 /* Soft Reset */
131
132 /* Master Control Register (MCTRL) bit definitions */
133 #define ISMT_MCTRL_SS 0x01 /* Start/Stop */
134 #define ISMT_MCTRL_MEIE 0x10 /* Master Error Interrupt Enable */
135 #define ISMT_MCTRL_FMHP 0x00ff0000 /* Firmware Master Head Ptr (FMHP) */
136
137 /* Master Status Register (MSTS) bit definitions */
138 #define ISMT_MSTS_HMTP 0xff0000 /* HW Master Tail Pointer (HMTP) */
139 #define ISMT_MSTS_MIS 0x20 /* Master Interrupt Status (MIS) */
140 #define ISMT_MSTS_MEIS 0x10 /* Master Error Int Status (MEIS) */
141 #define ISMT_MSTS_IP 0x01 /* In Progress */
142
143 /* Master Descriptor Size (MDS) bit definitions */
144 #define ISMT_MDS_MASK 0xff /* Master Descriptor Size mask (MDS) */
145
146 /* SMBus PHY Global Timing Register (SPGT) bit definitions */
147 #define ISMT_SPGT_SPD_MASK 0xc0000000 /* SMBus Speed mask */
148 #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */
149 #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */
150 #define ISMT_SPGT_SPD_400K (0x2 << 30) /* 400 kHz */
151 #define ISMT_SPGT_SPD_1M (0x3 << 30) /* 1 MHz */
152
153
154 /* MSI Control Register (MSICTL) bit definitions */
155 #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */
156
157 /* iSMT Hardware Descriptor */
158 struct ismt_desc {
159 u8 tgtaddr_rw; /* target address & r/w bit */
160 u8 wr_len_cmd; /* write length in bytes or a command */
161 u8 rd_len; /* read length */
162 u8 control; /* control bits */
163 u8 status; /* status bits */
164 u8 retry; /* collision retry and retry count */
165 u8 rxbytes; /* received bytes */
166 u8 txbytes; /* transmitted bytes */
167 u32 dptr_low; /* lower 32 bit of the data pointer */
168 u32 dptr_high; /* upper 32 bit of the data pointer */
169 } __packed;
170
171 struct ismt_priv {
172 struct i2c_adapter adapter;
173 void *smba; /* PCI BAR */
174 struct pci_dev *pci_dev;
175 struct ismt_desc *hw; /* descriptor virt base addr */
176 dma_addr_t io_rng_dma; /* descriptor HW base addr */
177 u8 head; /* ring buffer head pointer */
178 struct completion cmp; /* interrupt completion */
179 u8 dma_buffer[I2C_SMBUS_BLOCK_MAX + 1]; /* temp R/W data buffer */
180 bool using_msi; /* type of interrupt flag */
181 };
182
183 /**
184 * ismt_ids - PCI device IDs supported by this driver
185 */
186 static DEFINE_PCI_DEVICE_TABLE(ismt_ids) = {
187 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT0) },
188 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT1) },
189 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMT) },
190 { 0, }
191 };
192
193 MODULE_DEVICE_TABLE(pci, ismt_ids);
194
195 /* Bus speed control bits for slow debuggers - refer to the docs for usage */
196 static unsigned int bus_speed;
197 module_param(bus_speed, uint, S_IRUGO);
198 MODULE_PARM_DESC(bus_speed, "Bus Speed in kHz (0 = BIOS default)");
199
200 /**
201 * __ismt_desc_dump() - dump the contents of a specific descriptor
202 */
__ismt_desc_dump(struct device * dev,const struct ismt_desc * desc)203 static void __ismt_desc_dump(struct device *dev, const struct ismt_desc *desc)
204 {
205
206 dev_dbg(dev, "Descriptor struct: %p\n", desc);
207 dev_dbg(dev, "\ttgtaddr_rw=0x%02X\n", desc->tgtaddr_rw);
208 dev_dbg(dev, "\twr_len_cmd=0x%02X\n", desc->wr_len_cmd);
209 dev_dbg(dev, "\trd_len= 0x%02X\n", desc->rd_len);
210 dev_dbg(dev, "\tcontrol= 0x%02X\n", desc->control);
211 dev_dbg(dev, "\tstatus= 0x%02X\n", desc->status);
212 dev_dbg(dev, "\tretry= 0x%02X\n", desc->retry);
213 dev_dbg(dev, "\trxbytes= 0x%02X\n", desc->rxbytes);
214 dev_dbg(dev, "\ttxbytes= 0x%02X\n", desc->txbytes);
215 dev_dbg(dev, "\tdptr_low= 0x%08X\n", desc->dptr_low);
216 dev_dbg(dev, "\tdptr_high= 0x%08X\n", desc->dptr_high);
217 }
218 /**
219 * ismt_desc_dump() - dump the contents of a descriptor for debug purposes
220 * @priv: iSMT private data
221 */
ismt_desc_dump(struct ismt_priv * priv)222 static void ismt_desc_dump(struct ismt_priv *priv)
223 {
224 struct device *dev = &priv->pci_dev->dev;
225 struct ismt_desc *desc = &priv->hw[priv->head];
226
227 dev_dbg(dev, "Dump of the descriptor struct: 0x%X\n", priv->head);
228 __ismt_desc_dump(dev, desc);
229 }
230
231 /**
232 * ismt_gen_reg_dump() - dump the iSMT General Registers
233 * @priv: iSMT private data
234 */
ismt_gen_reg_dump(struct ismt_priv * priv)235 static void ismt_gen_reg_dump(struct ismt_priv *priv)
236 {
237 struct device *dev = &priv->pci_dev->dev;
238
239 dev_dbg(dev, "Dump of the iSMT General Registers\n");
240 dev_dbg(dev, " GCTRL.... : (0x%p)=0x%X\n",
241 priv->smba + ISMT_GR_GCTRL,
242 readl(priv->smba + ISMT_GR_GCTRL));
243 dev_dbg(dev, " SMTICL... : (0x%p)=0x%016llX\n",
244 priv->smba + ISMT_GR_SMTICL,
245 (long long unsigned int)readq(priv->smba + ISMT_GR_SMTICL));
246 dev_dbg(dev, " ERRINTMSK : (0x%p)=0x%X\n",
247 priv->smba + ISMT_GR_ERRINTMSK,
248 readl(priv->smba + ISMT_GR_ERRINTMSK));
249 dev_dbg(dev, " ERRAERMSK : (0x%p)=0x%X\n",
250 priv->smba + ISMT_GR_ERRAERMSK,
251 readl(priv->smba + ISMT_GR_ERRAERMSK));
252 dev_dbg(dev, " ERRSTS... : (0x%p)=0x%X\n",
253 priv->smba + ISMT_GR_ERRSTS,
254 readl(priv->smba + ISMT_GR_ERRSTS));
255 dev_dbg(dev, " ERRINFO.. : (0x%p)=0x%X\n",
256 priv->smba + ISMT_GR_ERRINFO,
257 readl(priv->smba + ISMT_GR_ERRINFO));
258 }
259
260 /**
261 * ismt_mstr_reg_dump() - dump the iSMT Master Registers
262 * @priv: iSMT private data
263 */
ismt_mstr_reg_dump(struct ismt_priv * priv)264 static void ismt_mstr_reg_dump(struct ismt_priv *priv)
265 {
266 struct device *dev = &priv->pci_dev->dev;
267
268 dev_dbg(dev, "Dump of the iSMT Master Registers\n");
269 dev_dbg(dev, " MDBA..... : (0x%p)=0x%016llX\n",
270 priv->smba + ISMT_MSTR_MDBA,
271 (long long unsigned int)readq(priv->smba + ISMT_MSTR_MDBA));
272 dev_dbg(dev, " MCTRL.... : (0x%p)=0x%X\n",
273 priv->smba + ISMT_MSTR_MCTRL,
274 readl(priv->smba + ISMT_MSTR_MCTRL));
275 dev_dbg(dev, " MSTS..... : (0x%p)=0x%X\n",
276 priv->smba + ISMT_MSTR_MSTS,
277 readl(priv->smba + ISMT_MSTR_MSTS));
278 dev_dbg(dev, " MDS...... : (0x%p)=0x%X\n",
279 priv->smba + ISMT_MSTR_MDS,
280 readl(priv->smba + ISMT_MSTR_MDS));
281 dev_dbg(dev, " RPOLICY.. : (0x%p)=0x%X\n",
282 priv->smba + ISMT_MSTR_RPOLICY,
283 readl(priv->smba + ISMT_MSTR_RPOLICY));
284 dev_dbg(dev, " SPGT..... : (0x%p)=0x%X\n",
285 priv->smba + ISMT_SPGT,
286 readl(priv->smba + ISMT_SPGT));
287 }
288
289 /**
290 * ismt_submit_desc() - add a descriptor to the ring
291 * @priv: iSMT private data
292 */
ismt_submit_desc(struct ismt_priv * priv)293 static void ismt_submit_desc(struct ismt_priv *priv)
294 {
295 uint fmhp;
296 uint val;
297
298 ismt_desc_dump(priv);
299 ismt_gen_reg_dump(priv);
300 ismt_mstr_reg_dump(priv);
301
302 /* Set the FMHP (Firmware Master Head Pointer)*/
303 fmhp = ((priv->head + 1) % ISMT_DESC_ENTRIES) << 16;
304 val = readl(priv->smba + ISMT_MSTR_MCTRL);
305 writel((val & ~ISMT_MCTRL_FMHP) | fmhp,
306 priv->smba + ISMT_MSTR_MCTRL);
307
308 /* Set the start bit */
309 val = readl(priv->smba + ISMT_MSTR_MCTRL);
310 writel(val | ISMT_MCTRL_SS,
311 priv->smba + ISMT_MSTR_MCTRL);
312 }
313
314 /**
315 * ismt_process_desc() - handle the completion of the descriptor
316 * @desc: the iSMT hardware descriptor
317 * @data: data buffer from the upper layer
318 * @priv: ismt_priv struct holding our dma buffer
319 * @size: SMBus transaction type
320 * @read_write: flag to indicate if this is a read or write
321 */
ismt_process_desc(const struct ismt_desc * desc,union i2c_smbus_data * data,struct ismt_priv * priv,int size,char read_write)322 static int ismt_process_desc(const struct ismt_desc *desc,
323 union i2c_smbus_data *data,
324 struct ismt_priv *priv, int size,
325 char read_write)
326 {
327 u8 *dma_buffer = priv->dma_buffer;
328
329 dev_dbg(&priv->pci_dev->dev, "Processing completed descriptor\n");
330 __ismt_desc_dump(&priv->pci_dev->dev, desc);
331
332 if (desc->status & ISMT_DESC_SCS) {
333 if (read_write == I2C_SMBUS_WRITE &&
334 size != I2C_SMBUS_PROC_CALL)
335 return 0;
336
337 switch (size) {
338 case I2C_SMBUS_BYTE:
339 case I2C_SMBUS_BYTE_DATA:
340 data->byte = dma_buffer[0];
341 break;
342 case I2C_SMBUS_WORD_DATA:
343 case I2C_SMBUS_PROC_CALL:
344 data->word = dma_buffer[0] | (dma_buffer[1] << 8);
345 break;
346 case I2C_SMBUS_BLOCK_DATA:
347 memcpy(&data->block[1], dma_buffer, desc->rxbytes);
348 data->block[0] = desc->rxbytes;
349 break;
350 }
351 return 0;
352 }
353
354 if (likely(desc->status & ISMT_DESC_NAK))
355 return -ENXIO;
356
357 if (desc->status & ISMT_DESC_CRC)
358 return -EBADMSG;
359
360 if (desc->status & ISMT_DESC_COL)
361 return -EAGAIN;
362
363 if (desc->status & ISMT_DESC_LPR)
364 return -EPROTO;
365
366 if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO))
367 return -ETIMEDOUT;
368
369 return -EIO;
370 }
371
372 /**
373 * ismt_access() - process an SMBus command
374 * @adap: the i2c host adapter
375 * @addr: address of the i2c/SMBus target
376 * @flags: command options
377 * @read_write: read from or write to device
378 * @command: the i2c/SMBus command to issue
379 * @size: SMBus transaction type
380 * @data: read/write data buffer
381 */
ismt_access(struct i2c_adapter * adap,u16 addr,unsigned short flags,char read_write,u8 command,int size,union i2c_smbus_data * data)382 static int ismt_access(struct i2c_adapter *adap, u16 addr,
383 unsigned short flags, char read_write, u8 command,
384 int size, union i2c_smbus_data *data)
385 {
386 int ret;
387 dma_addr_t dma_addr = 0; /* address of the data buffer */
388 u8 dma_size = 0;
389 enum dma_data_direction dma_direction = 0;
390 struct ismt_desc *desc;
391 struct ismt_priv *priv = i2c_get_adapdata(adap);
392 struct device *dev = &priv->pci_dev->dev;
393
394 desc = &priv->hw[priv->head];
395
396 /* Initialize the descriptor */
397 memset(desc, 0, sizeof(struct ismt_desc));
398 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write);
399
400 /* Initialize common control bits */
401 if (likely(priv->using_msi))
402 desc->control = ISMT_DESC_INT | ISMT_DESC_FAIR;
403 else
404 desc->control = ISMT_DESC_FAIR;
405
406 if ((flags & I2C_CLIENT_PEC) && (size != I2C_SMBUS_QUICK)
407 && (size != I2C_SMBUS_I2C_BLOCK_DATA))
408 desc->control |= ISMT_DESC_PEC;
409
410 switch (size) {
411 case I2C_SMBUS_QUICK:
412 dev_dbg(dev, "I2C_SMBUS_QUICK\n");
413 break;
414
415 case I2C_SMBUS_BYTE:
416 if (read_write == I2C_SMBUS_WRITE) {
417 /*
418 * Send Byte
419 * The command field contains the write data
420 */
421 dev_dbg(dev, "I2C_SMBUS_BYTE: WRITE\n");
422 desc->control |= ISMT_DESC_CWRL;
423 desc->wr_len_cmd = command;
424 } else {
425 /* Receive Byte */
426 dev_dbg(dev, "I2C_SMBUS_BYTE: READ\n");
427 dma_size = 1;
428 dma_direction = DMA_FROM_DEVICE;
429 desc->rd_len = 1;
430 }
431 break;
432
433 case I2C_SMBUS_BYTE_DATA:
434 if (read_write == I2C_SMBUS_WRITE) {
435 /*
436 * Write Byte
437 * Command plus 1 data byte
438 */
439 dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: WRITE\n");
440 desc->wr_len_cmd = 2;
441 dma_size = 2;
442 dma_direction = DMA_TO_DEVICE;
443 priv->dma_buffer[0] = command;
444 priv->dma_buffer[1] = data->byte;
445 } else {
446 /* Read Byte */
447 dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: READ\n");
448 desc->control |= ISMT_DESC_CWRL;
449 desc->wr_len_cmd = command;
450 desc->rd_len = 1;
451 dma_size = 1;
452 dma_direction = DMA_FROM_DEVICE;
453 }
454 break;
455
456 case I2C_SMBUS_WORD_DATA:
457 if (read_write == I2C_SMBUS_WRITE) {
458 /* Write Word */
459 dev_dbg(dev, "I2C_SMBUS_WORD_DATA: WRITE\n");
460 desc->wr_len_cmd = 3;
461 dma_size = 3;
462 dma_direction = DMA_TO_DEVICE;
463 priv->dma_buffer[0] = command;
464 priv->dma_buffer[1] = data->word & 0xff;
465 priv->dma_buffer[2] = data->word >> 8;
466 } else {
467 /* Read Word */
468 dev_dbg(dev, "I2C_SMBUS_WORD_DATA: READ\n");
469 desc->wr_len_cmd = command;
470 desc->control |= ISMT_DESC_CWRL;
471 desc->rd_len = 2;
472 dma_size = 2;
473 dma_direction = DMA_FROM_DEVICE;
474 }
475 break;
476
477 case I2C_SMBUS_PROC_CALL:
478 dev_dbg(dev, "I2C_SMBUS_PROC_CALL\n");
479 desc->wr_len_cmd = 3;
480 desc->rd_len = 2;
481 dma_size = 3;
482 dma_direction = DMA_BIDIRECTIONAL;
483 priv->dma_buffer[0] = command;
484 priv->dma_buffer[1] = data->word & 0xff;
485 priv->dma_buffer[2] = data->word >> 8;
486 break;
487
488 case I2C_SMBUS_BLOCK_DATA:
489 if (read_write == I2C_SMBUS_WRITE) {
490 /* Block Write */
491 dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: WRITE\n");
492 dma_size = data->block[0] + 1;
493 dma_direction = DMA_TO_DEVICE;
494 desc->wr_len_cmd = dma_size;
495 desc->control |= ISMT_DESC_BLK;
496 priv->dma_buffer[0] = command;
497 memcpy(&priv->dma_buffer[1], &data->block[1], dma_size);
498 } else {
499 /* Block Read */
500 dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: READ\n");
501 dma_size = I2C_SMBUS_BLOCK_MAX;
502 dma_direction = DMA_FROM_DEVICE;
503 desc->rd_len = dma_size;
504 desc->wr_len_cmd = command;
505 desc->control |= (ISMT_DESC_BLK | ISMT_DESC_CWRL);
506 }
507 break;
508
509 default:
510 dev_err(dev, "Unsupported transaction %d\n",
511 size);
512 return -EOPNOTSUPP;
513 }
514
515 /* map the data buffer */
516 if (dma_size != 0) {
517 dev_dbg(dev, " dev=%p\n", dev);
518 dev_dbg(dev, " data=%p\n", data);
519 dev_dbg(dev, " dma_buffer=%p\n", priv->dma_buffer);
520 dev_dbg(dev, " dma_size=%d\n", dma_size);
521 dev_dbg(dev, " dma_direction=%d\n", dma_direction);
522
523 dma_addr = dma_map_single(dev,
524 priv->dma_buffer,
525 dma_size,
526 dma_direction);
527
528 if (dma_mapping_error(dev, dma_addr)) {
529 dev_err(dev, "Error in mapping dma buffer %p\n",
530 priv->dma_buffer);
531 return -EIO;
532 }
533
534 dev_dbg(dev, " dma_addr = 0x%016llX\n",
535 (unsigned long long)dma_addr);
536
537 desc->dptr_low = lower_32_bits(dma_addr);
538 desc->dptr_high = upper_32_bits(dma_addr);
539 }
540
541 INIT_COMPLETION(priv->cmp);
542
543 /* Add the descriptor */
544 ismt_submit_desc(priv);
545
546 /* Now we wait for interrupt completion, 1s */
547 ret = wait_for_completion_timeout(&priv->cmp, HZ*1);
548
549 /* unmap the data buffer */
550 if (dma_size != 0)
551 dma_unmap_single(&adap->dev, dma_addr, dma_size, dma_direction);
552
553 if (unlikely(!ret)) {
554 dev_err(dev, "completion wait timed out\n");
555 ret = -ETIMEDOUT;
556 goto out;
557 }
558
559 /* do any post processing of the descriptor here */
560 ret = ismt_process_desc(desc, data, priv, size, read_write);
561
562 out:
563 /* Update the ring pointer */
564 priv->head++;
565 priv->head %= ISMT_DESC_ENTRIES;
566
567 return ret;
568 }
569
570 /**
571 * ismt_func() - report which i2c commands are supported by this adapter
572 * @adap: the i2c host adapter
573 */
ismt_func(struct i2c_adapter * adap)574 static u32 ismt_func(struct i2c_adapter *adap)
575 {
576 return I2C_FUNC_SMBUS_QUICK |
577 I2C_FUNC_SMBUS_BYTE |
578 I2C_FUNC_SMBUS_BYTE_DATA |
579 I2C_FUNC_SMBUS_WORD_DATA |
580 I2C_FUNC_SMBUS_PROC_CALL |
581 I2C_FUNC_SMBUS_BLOCK_DATA |
582 I2C_FUNC_SMBUS_PEC;
583 }
584
585 /**
586 * smbus_algorithm - the adapter algorithm and supported functionality
587 * @smbus_xfer: the adapter algorithm
588 * @functionality: functionality supported by the adapter
589 */
590 static const struct i2c_algorithm smbus_algorithm = {
591 .smbus_xfer = ismt_access,
592 .functionality = ismt_func,
593 };
594
595 /**
596 * ismt_handle_isr() - interrupt handler bottom half
597 * @priv: iSMT private data
598 */
ismt_handle_isr(struct ismt_priv * priv)599 static irqreturn_t ismt_handle_isr(struct ismt_priv *priv)
600 {
601 complete(&priv->cmp);
602
603 return IRQ_HANDLED;
604 }
605
606
607 /**
608 * ismt_do_interrupt() - IRQ interrupt handler
609 * @vec: interrupt vector
610 * @data: iSMT private data
611 */
ismt_do_interrupt(int vec,void * data)612 static irqreturn_t ismt_do_interrupt(int vec, void *data)
613 {
614 u32 val;
615 struct ismt_priv *priv = data;
616
617 /*
618 * check to see it's our interrupt, return IRQ_NONE if not ours
619 * since we are sharing interrupt
620 */
621 val = readl(priv->smba + ISMT_MSTR_MSTS);
622
623 if (!(val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS)))
624 return IRQ_NONE;
625 else
626 writel(val | ISMT_MSTS_MIS | ISMT_MSTS_MEIS,
627 priv->smba + ISMT_MSTR_MSTS);
628
629 return ismt_handle_isr(priv);
630 }
631
632 /**
633 * ismt_do_msi_interrupt() - MSI interrupt handler
634 * @vec: interrupt vector
635 * @data: iSMT private data
636 */
ismt_do_msi_interrupt(int vec,void * data)637 static irqreturn_t ismt_do_msi_interrupt(int vec, void *data)
638 {
639 return ismt_handle_isr(data);
640 }
641
642 /**
643 * ismt_hw_init() - initialize the iSMT hardware
644 * @priv: iSMT private data
645 */
ismt_hw_init(struct ismt_priv * priv)646 static void ismt_hw_init(struct ismt_priv *priv)
647 {
648 u32 val;
649 struct device *dev = &priv->pci_dev->dev;
650
651 /* initialize the Master Descriptor Base Address (MDBA) */
652 writeq(priv->io_rng_dma, priv->smba + ISMT_MSTR_MDBA);
653
654 /* initialize the Master Control Register (MCTRL) */
655 writel(ISMT_MCTRL_MEIE, priv->smba + ISMT_MSTR_MCTRL);
656
657 /* initialize the Master Status Register (MSTS) */
658 writel(0, priv->smba + ISMT_MSTR_MSTS);
659
660 /* initialize the Master Descriptor Size (MDS) */
661 val = readl(priv->smba + ISMT_MSTR_MDS);
662 writel((val & ~ISMT_MDS_MASK) | (ISMT_DESC_ENTRIES - 1),
663 priv->smba + ISMT_MSTR_MDS);
664
665 /*
666 * Set the SMBus speed (could use this for slow HW debuggers)
667 */
668
669 val = readl(priv->smba + ISMT_SPGT);
670
671 switch (bus_speed) {
672 case 0:
673 break;
674
675 case 80:
676 dev_dbg(dev, "Setting SMBus clock to 80 kHz\n");
677 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_80K),
678 priv->smba + ISMT_SPGT);
679 break;
680
681 case 100:
682 dev_dbg(dev, "Setting SMBus clock to 100 kHz\n");
683 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_100K),
684 priv->smba + ISMT_SPGT);
685 break;
686
687 case 400:
688 dev_dbg(dev, "Setting SMBus clock to 400 kHz\n");
689 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_400K),
690 priv->smba + ISMT_SPGT);
691 break;
692
693 case 1000:
694 dev_dbg(dev, "Setting SMBus clock to 1000 kHz\n");
695 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_1M),
696 priv->smba + ISMT_SPGT);
697 break;
698
699 default:
700 dev_warn(dev, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n");
701 break;
702 }
703
704 val = readl(priv->smba + ISMT_SPGT);
705
706 switch (val & ISMT_SPGT_SPD_MASK) {
707 case ISMT_SPGT_SPD_80K:
708 bus_speed = 80;
709 break;
710 case ISMT_SPGT_SPD_100K:
711 bus_speed = 100;
712 break;
713 case ISMT_SPGT_SPD_400K:
714 bus_speed = 400;
715 break;
716 case ISMT_SPGT_SPD_1M:
717 bus_speed = 1000;
718 break;
719 }
720 dev_dbg(dev, "SMBus clock is running at %d kHz\n", bus_speed);
721 }
722
723 /**
724 * ismt_dev_init() - initialize the iSMT data structures
725 * @priv: iSMT private data
726 */
ismt_dev_init(struct ismt_priv * priv)727 static int ismt_dev_init(struct ismt_priv *priv)
728 {
729 /* allocate memory for the descriptor */
730 priv->hw = dmam_alloc_coherent(&priv->pci_dev->dev,
731 (ISMT_DESC_ENTRIES
732 * sizeof(struct ismt_desc)),
733 &priv->io_rng_dma,
734 GFP_KERNEL);
735 if (!priv->hw)
736 return -ENOMEM;
737
738 memset(priv->hw, 0, (ISMT_DESC_ENTRIES * sizeof(struct ismt_desc)));
739
740 priv->head = 0;
741 init_completion(&priv->cmp);
742
743 return 0;
744 }
745
746 /**
747 * ismt_int_init() - initialize interrupts
748 * @priv: iSMT private data
749 */
ismt_int_init(struct ismt_priv * priv)750 static int ismt_int_init(struct ismt_priv *priv)
751 {
752 int err;
753
754 /* Try using MSI interrupts */
755 err = pci_enable_msi(priv->pci_dev);
756 if (err) {
757 dev_warn(&priv->pci_dev->dev,
758 "Unable to use MSI interrupts, falling back to legacy\n");
759 goto intx;
760 }
761
762 err = devm_request_irq(&priv->pci_dev->dev,
763 priv->pci_dev->irq,
764 ismt_do_msi_interrupt,
765 0,
766 "ismt-msi",
767 priv);
768 if (err) {
769 pci_disable_msi(priv->pci_dev);
770 goto intx;
771 }
772
773 priv->using_msi = true;
774 goto done;
775
776 /* Try using legacy interrupts */
777 intx:
778 err = devm_request_irq(&priv->pci_dev->dev,
779 priv->pci_dev->irq,
780 ismt_do_interrupt,
781 IRQF_SHARED,
782 "ismt-intx",
783 priv);
784 if (err) {
785 dev_err(&priv->pci_dev->dev, "no usable interrupts\n");
786 return -ENODEV;
787 }
788
789 priv->using_msi = false;
790
791 done:
792 return 0;
793 }
794
795 static struct pci_driver ismt_driver;
796
797 /**
798 * ismt_probe() - probe for iSMT devices
799 * @pdev: PCI-Express device
800 * @id: PCI-Express device ID
801 */
802 static int
ismt_probe(struct pci_dev * pdev,const struct pci_device_id * id)803 ismt_probe(struct pci_dev *pdev, const struct pci_device_id *id)
804 {
805 int err;
806 struct ismt_priv *priv;
807 unsigned long start, len;
808
809 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
810 if (!priv)
811 return -ENOMEM;
812
813 pci_set_drvdata(pdev, priv);
814 i2c_set_adapdata(&priv->adapter, priv);
815 priv->adapter.owner = THIS_MODULE;
816
817 priv->adapter.class = I2C_CLASS_HWMON;
818
819 priv->adapter.algo = &smbus_algorithm;
820
821 /* set up the sysfs linkage to our parent device */
822 priv->adapter.dev.parent = &pdev->dev;
823
824 /* number of retries on lost arbitration */
825 priv->adapter.retries = ISMT_MAX_RETRIES;
826
827 priv->pci_dev = pdev;
828
829 err = pcim_enable_device(pdev);
830 if (err) {
831 dev_err(&pdev->dev, "Failed to enable SMBus PCI device (%d)\n",
832 err);
833 return err;
834 }
835
836 /* enable bus mastering */
837 pci_set_master(pdev);
838
839 /* Determine the address of the SMBus area */
840 start = pci_resource_start(pdev, SMBBAR);
841 len = pci_resource_len(pdev, SMBBAR);
842 if (!start || !len) {
843 dev_err(&pdev->dev,
844 "SMBus base address uninitialized, upgrade BIOS\n");
845 return -ENODEV;
846 }
847
848 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
849 "SMBus iSMT adapter at %lx", start);
850
851 dev_dbg(&priv->pci_dev->dev, " start=0x%lX\n", start);
852 dev_dbg(&priv->pci_dev->dev, " len=0x%lX\n", len);
853
854 err = acpi_check_resource_conflict(&pdev->resource[SMBBAR]);
855 if (err) {
856 dev_err(&pdev->dev, "ACPI resource conflict!\n");
857 return err;
858 }
859
860 err = pci_request_region(pdev, SMBBAR, ismt_driver.name);
861 if (err) {
862 dev_err(&pdev->dev,
863 "Failed to request SMBus region 0x%lx-0x%lx\n",
864 start, start + len);
865 return err;
866 }
867
868 priv->smba = pcim_iomap(pdev, SMBBAR, len);
869 if (!priv->smba) {
870 dev_err(&pdev->dev, "Unable to ioremap SMBus BAR\n");
871 err = -ENODEV;
872 goto fail;
873 }
874
875 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
876 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
877 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
878 (pci_set_consistent_dma_mask(pdev,
879 DMA_BIT_MASK(32)) != 0)) {
880 dev_err(&pdev->dev, "pci_set_dma_mask fail %p\n",
881 pdev);
882 goto fail;
883 }
884 }
885
886 err = ismt_dev_init(priv);
887 if (err)
888 goto fail;
889
890 ismt_hw_init(priv);
891
892 err = ismt_int_init(priv);
893 if (err)
894 goto fail;
895
896 err = i2c_add_adapter(&priv->adapter);
897 if (err) {
898 dev_err(&pdev->dev, "Failed to add SMBus iSMT adapter\n");
899 err = -ENODEV;
900 goto fail;
901 }
902 return 0;
903
904 fail:
905 pci_release_region(pdev, SMBBAR);
906 return err;
907 }
908
909 /**
910 * ismt_remove() - release driver resources
911 * @pdev: PCI-Express device
912 */
ismt_remove(struct pci_dev * pdev)913 static void ismt_remove(struct pci_dev *pdev)
914 {
915 struct ismt_priv *priv = pci_get_drvdata(pdev);
916
917 i2c_del_adapter(&priv->adapter);
918 pci_release_region(pdev, SMBBAR);
919 }
920
921 /**
922 * ismt_suspend() - place the device in suspend
923 * @pdev: PCI-Express device
924 * @mesg: PM message
925 */
926 #ifdef CONFIG_PM
ismt_suspend(struct pci_dev * pdev,pm_message_t mesg)927 static int ismt_suspend(struct pci_dev *pdev, pm_message_t mesg)
928 {
929 pci_save_state(pdev);
930 pci_set_power_state(pdev, pci_choose_state(pdev, mesg));
931 return 0;
932 }
933
934 /**
935 * ismt_resume() - PCI resume code
936 * @pdev: PCI-Express device
937 */
ismt_resume(struct pci_dev * pdev)938 static int ismt_resume(struct pci_dev *pdev)
939 {
940 pci_set_power_state(pdev, PCI_D0);
941 pci_restore_state(pdev);
942 return pci_enable_device(pdev);
943 }
944
945 #else
946
947 #define ismt_suspend NULL
948 #define ismt_resume NULL
949
950 #endif
951
952 static struct pci_driver ismt_driver = {
953 .name = "ismt_smbus",
954 .id_table = ismt_ids,
955 .probe = ismt_probe,
956 .remove = ismt_remove,
957 .suspend = ismt_suspend,
958 .resume = ismt_resume,
959 };
960
961 module_pci_driver(ismt_driver);
962
963 MODULE_LICENSE("Dual BSD/GPL");
964 MODULE_AUTHOR("Bill E. Brown <bill.e.brown@intel.com>");
965 MODULE_DESCRIPTION("Intel SMBus Message Transport (iSMT) driver");
966