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1 /*
2  * Specific bus support for PMC-TWI compliant implementation on MSP71xx.
3  *
4  * Copyright 2005-2007 PMC-Sierra, Inc.
5  *
6  *  This program is free software; you can redistribute  it and/or modify it
7  *  under  the terms of  the GNU General  Public License as published by the
8  *  Free Software Foundation;  either version 2 of the  License, or (at your
9  *  option) any later version.
10  *
11  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
12  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
13  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
14  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
15  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
17  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
19  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21  *
22  *  You should have received a copy of the  GNU General Public License along
23  *  with this program; if not, write  to the Free Software Foundation, Inc.,
24  *  675 Mass Ave, Cambridge, MA 02139, USA.
25  */
26 
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/platform_device.h>
31 #include <linux/i2c.h>
32 #include <linux/interrupt.h>
33 #include <linux/completion.h>
34 #include <linux/mutex.h>
35 #include <linux/delay.h>
36 #include <linux/io.h>
37 
38 #define DRV_NAME	"pmcmsptwi"
39 
40 #define MSP_TWI_SF_CLK_REG_OFFSET	0x00
41 #define MSP_TWI_HS_CLK_REG_OFFSET	0x04
42 #define MSP_TWI_CFG_REG_OFFSET		0x08
43 #define MSP_TWI_CMD_REG_OFFSET		0x0c
44 #define MSP_TWI_ADD_REG_OFFSET		0x10
45 #define MSP_TWI_DAT_0_REG_OFFSET	0x14
46 #define MSP_TWI_DAT_1_REG_OFFSET	0x18
47 #define MSP_TWI_INT_STS_REG_OFFSET	0x1c
48 #define MSP_TWI_INT_MSK_REG_OFFSET	0x20
49 #define MSP_TWI_BUSY_REG_OFFSET		0x24
50 
51 #define MSP_TWI_INT_STS_DONE			(1 << 0)
52 #define MSP_TWI_INT_STS_LOST_ARBITRATION	(1 << 1)
53 #define MSP_TWI_INT_STS_NO_RESPONSE		(1 << 2)
54 #define MSP_TWI_INT_STS_DATA_COLLISION		(1 << 3)
55 #define MSP_TWI_INT_STS_BUSY			(1 << 4)
56 #define MSP_TWI_INT_STS_ALL			0x1f
57 
58 #define MSP_MAX_BYTES_PER_RW		8
59 #define MSP_MAX_POLL			5
60 #define MSP_POLL_DELAY			10
61 #define MSP_IRQ_TIMEOUT			(MSP_MAX_POLL * MSP_POLL_DELAY)
62 
63 /* IO Operation macros */
64 #define pmcmsptwi_readl		__raw_readl
65 #define pmcmsptwi_writel	__raw_writel
66 
67 /* TWI command type */
68 enum pmcmsptwi_cmd_type {
69 	MSP_TWI_CMD_WRITE	= 0,	/* Write only */
70 	MSP_TWI_CMD_READ	= 1,	/* Read only */
71 	MSP_TWI_CMD_WRITE_READ	= 2,	/* Write then Read */
72 };
73 
74 /* The possible results of the xferCmd */
75 enum pmcmsptwi_xfer_result {
76 	MSP_TWI_XFER_OK	= 0,
77 	MSP_TWI_XFER_TIMEOUT,
78 	MSP_TWI_XFER_BUSY,
79 	MSP_TWI_XFER_DATA_COLLISION,
80 	MSP_TWI_XFER_NO_RESPONSE,
81 	MSP_TWI_XFER_LOST_ARBITRATION,
82 };
83 
84 /* Corresponds to a PMCTWI clock configuration register */
85 struct pmcmsptwi_clock {
86 	u8 filter;	/* Bits 15:12,	default = 0x03 */
87 	u16 clock;	/* Bits 9:0,	default = 0x001f */
88 };
89 
90 struct pmcmsptwi_clockcfg {
91 	struct pmcmsptwi_clock standard;  /* The standard/fast clock config */
92 	struct pmcmsptwi_clock highspeed; /* The highspeed clock config */
93 };
94 
95 /* Corresponds to the main TWI configuration register */
96 struct pmcmsptwi_cfg {
97 	u8 arbf;	/* Bits 15:12,	default=0x03 */
98 	u8 nak;		/* Bits 11:8,	default=0x03 */
99 	u8 add10;	/* Bit 7,	default=0x00 */
100 	u8 mst_code;	/* Bits 6:4,	default=0x00 */
101 	u8 arb;		/* Bit 1,	default=0x01 */
102 	u8 highspeed;	/* Bit 0,	default=0x00 */
103 };
104 
105 /* A single pmctwi command to issue */
106 struct pmcmsptwi_cmd {
107 	u16 addr;	/* The slave address (7 or 10 bits) */
108 	enum pmcmsptwi_cmd_type type;	/* The command type */
109 	u8 write_len;	/* Number of bytes in the write buffer */
110 	u8 read_len;	/* Number of bytes in the read buffer */
111 	u8 *write_data;	/* Buffer of characters to send */
112 	u8 *read_data;	/* Buffer to fill with incoming data */
113 };
114 
115 /* The private data */
116 struct pmcmsptwi_data {
117 	void __iomem *iobase;			/* iomapped base for IO */
118 	int irq;				/* IRQ to use (0 disables) */
119 	struct completion wait;			/* Completion for xfer */
120 	struct mutex lock;			/* Used for threadsafeness */
121 	enum pmcmsptwi_xfer_result last_result;	/* result of last xfer */
122 };
123 
124 /* The default settings */
125 static const struct pmcmsptwi_clockcfg pmcmsptwi_defclockcfg = {
126 	.standard = {
127 		.filter	= 0x3,
128 		.clock	= 0x1f,
129 	},
130 	.highspeed = {
131 		.filter	= 0x3,
132 		.clock	= 0x1f,
133 	},
134 };
135 
136 static const struct pmcmsptwi_cfg pmcmsptwi_defcfg = {
137 	.arbf		= 0x03,
138 	.nak		= 0x03,
139 	.add10		= 0x00,
140 	.mst_code	= 0x00,
141 	.arb		= 0x01,
142 	.highspeed	= 0x00,
143 };
144 
145 static struct pmcmsptwi_data pmcmsptwi_data;
146 
147 static struct i2c_adapter pmcmsptwi_adapter;
148 
149 /* inline helper functions */
pmcmsptwi_clock_to_reg(const struct pmcmsptwi_clock * clock)150 static inline u32 pmcmsptwi_clock_to_reg(
151 			const struct pmcmsptwi_clock *clock)
152 {
153 	return ((clock->filter & 0xf) << 12) | (clock->clock & 0x03ff);
154 }
155 
pmcmsptwi_reg_to_clock(u32 reg,struct pmcmsptwi_clock * clock)156 static inline void pmcmsptwi_reg_to_clock(
157 			u32 reg, struct pmcmsptwi_clock *clock)
158 {
159 	clock->filter = (reg >> 12) & 0xf;
160 	clock->clock = reg & 0x03ff;
161 }
162 
pmcmsptwi_cfg_to_reg(const struct pmcmsptwi_cfg * cfg)163 static inline u32 pmcmsptwi_cfg_to_reg(const struct pmcmsptwi_cfg *cfg)
164 {
165 	return ((cfg->arbf & 0xf) << 12) |
166 		((cfg->nak & 0xf) << 8) |
167 		((cfg->add10 & 0x1) << 7) |
168 		((cfg->mst_code & 0x7) << 4) |
169 		((cfg->arb & 0x1) << 1) |
170 		(cfg->highspeed & 0x1);
171 }
172 
pmcmsptwi_reg_to_cfg(u32 reg,struct pmcmsptwi_cfg * cfg)173 static inline void pmcmsptwi_reg_to_cfg(u32 reg, struct pmcmsptwi_cfg *cfg)
174 {
175 	cfg->arbf = (reg >> 12) & 0xf;
176 	cfg->nak = (reg >> 8) & 0xf;
177 	cfg->add10 = (reg >> 7) & 0x1;
178 	cfg->mst_code = (reg >> 4) & 0x7;
179 	cfg->arb = (reg >> 1) & 0x1;
180 	cfg->highspeed = reg & 0x1;
181 }
182 
183 /*
184  * Sets the current clock configuration
185  */
pmcmsptwi_set_clock_config(const struct pmcmsptwi_clockcfg * cfg,struct pmcmsptwi_data * data)186 static void pmcmsptwi_set_clock_config(const struct pmcmsptwi_clockcfg *cfg,
187 					struct pmcmsptwi_data *data)
188 {
189 	mutex_lock(&data->lock);
190 	pmcmsptwi_writel(pmcmsptwi_clock_to_reg(&cfg->standard),
191 				data->iobase + MSP_TWI_SF_CLK_REG_OFFSET);
192 	pmcmsptwi_writel(pmcmsptwi_clock_to_reg(&cfg->highspeed),
193 				data->iobase + MSP_TWI_HS_CLK_REG_OFFSET);
194 	mutex_unlock(&data->lock);
195 }
196 
197 /*
198  * Gets the current TWI bus configuration
199  */
pmcmsptwi_get_twi_config(struct pmcmsptwi_cfg * cfg,struct pmcmsptwi_data * data)200 static void pmcmsptwi_get_twi_config(struct pmcmsptwi_cfg *cfg,
201 					struct pmcmsptwi_data *data)
202 {
203 	mutex_lock(&data->lock);
204 	pmcmsptwi_reg_to_cfg(pmcmsptwi_readl(
205 				data->iobase + MSP_TWI_CFG_REG_OFFSET), cfg);
206 	mutex_unlock(&data->lock);
207 }
208 
209 /*
210  * Sets the current TWI bus configuration
211  */
pmcmsptwi_set_twi_config(const struct pmcmsptwi_cfg * cfg,struct pmcmsptwi_data * data)212 static void pmcmsptwi_set_twi_config(const struct pmcmsptwi_cfg *cfg,
213 					struct pmcmsptwi_data *data)
214 {
215 	mutex_lock(&data->lock);
216 	pmcmsptwi_writel(pmcmsptwi_cfg_to_reg(cfg),
217 				data->iobase + MSP_TWI_CFG_REG_OFFSET);
218 	mutex_unlock(&data->lock);
219 }
220 
221 /*
222  * Parses the 'int_sts' register and returns a well-defined error code
223  */
pmcmsptwi_get_result(u32 reg)224 static enum pmcmsptwi_xfer_result pmcmsptwi_get_result(u32 reg)
225 {
226 	if (reg & MSP_TWI_INT_STS_LOST_ARBITRATION) {
227 		dev_dbg(&pmcmsptwi_adapter.dev,
228 			"Result: Lost arbitration\n");
229 		return MSP_TWI_XFER_LOST_ARBITRATION;
230 	} else if (reg & MSP_TWI_INT_STS_NO_RESPONSE) {
231 		dev_dbg(&pmcmsptwi_adapter.dev,
232 			"Result: No response\n");
233 		return MSP_TWI_XFER_NO_RESPONSE;
234 	} else if (reg & MSP_TWI_INT_STS_DATA_COLLISION) {
235 		dev_dbg(&pmcmsptwi_adapter.dev,
236 			"Result: Data collision\n");
237 		return MSP_TWI_XFER_DATA_COLLISION;
238 	} else if (reg & MSP_TWI_INT_STS_BUSY) {
239 		dev_dbg(&pmcmsptwi_adapter.dev,
240 			"Result: Bus busy\n");
241 		return MSP_TWI_XFER_BUSY;
242 	}
243 
244 	dev_dbg(&pmcmsptwi_adapter.dev, "Result: Operation succeeded\n");
245 	return MSP_TWI_XFER_OK;
246 }
247 
248 /*
249  * In interrupt mode, handle the interrupt.
250  * NOTE: Assumes data->lock is held.
251  */
pmcmsptwi_interrupt(int irq,void * ptr)252 static irqreturn_t pmcmsptwi_interrupt(int irq, void *ptr)
253 {
254 	struct pmcmsptwi_data *data = ptr;
255 
256 	u32 reason = pmcmsptwi_readl(data->iobase +
257 					MSP_TWI_INT_STS_REG_OFFSET);
258 	pmcmsptwi_writel(reason, data->iobase + MSP_TWI_INT_STS_REG_OFFSET);
259 
260 	dev_dbg(&pmcmsptwi_adapter.dev, "Got interrupt 0x%08x\n", reason);
261 	if (!(reason & MSP_TWI_INT_STS_DONE))
262 		return IRQ_NONE;
263 
264 	data->last_result = pmcmsptwi_get_result(reason);
265 	complete(&data->wait);
266 
267 	return IRQ_HANDLED;
268 }
269 
270 /*
271  * Probe for and register the device and return 0 if there is one.
272  */
pmcmsptwi_probe(struct platform_device * pldev)273 static int pmcmsptwi_probe(struct platform_device *pldev)
274 {
275 	struct resource *res;
276 	int rc = -ENODEV;
277 
278 	/* get the static platform resources */
279 	res = platform_get_resource(pldev, IORESOURCE_MEM, 0);
280 	if (!res) {
281 		dev_err(&pldev->dev, "IOMEM resource not found\n");
282 		goto ret_err;
283 	}
284 
285 	/* reserve the memory region */
286 	if (!request_mem_region(res->start, resource_size(res),
287 				pldev->name)) {
288 		dev_err(&pldev->dev,
289 			"Unable to get memory/io address region 0x%08x\n",
290 			res->start);
291 		rc = -EBUSY;
292 		goto ret_err;
293 	}
294 
295 	/* remap the memory */
296 	pmcmsptwi_data.iobase = ioremap_nocache(res->start,
297 						resource_size(res));
298 	if (!pmcmsptwi_data.iobase) {
299 		dev_err(&pldev->dev,
300 			"Unable to ioremap address 0x%08x\n", res->start);
301 		rc = -EIO;
302 		goto ret_unreserve;
303 	}
304 
305 	/* request the irq */
306 	pmcmsptwi_data.irq = platform_get_irq(pldev, 0);
307 	if (pmcmsptwi_data.irq) {
308 		rc = request_irq(pmcmsptwi_data.irq, &pmcmsptwi_interrupt,
309 				 IRQF_SHARED, pldev->name, &pmcmsptwi_data);
310 		if (rc == 0) {
311 			/*
312 			 * Enable 'DONE' interrupt only.
313 			 *
314 			 * If you enable all interrupts, you will get one on
315 			 * error and another when the operation completes.
316 			 * This way you only have to handle one interrupt,
317 			 * but you can still check all result flags.
318 			 */
319 			pmcmsptwi_writel(MSP_TWI_INT_STS_DONE,
320 					pmcmsptwi_data.iobase +
321 					MSP_TWI_INT_MSK_REG_OFFSET);
322 		} else {
323 			dev_warn(&pldev->dev,
324 				"Could not assign TWI IRQ handler "
325 				"to irq %d (continuing with poll)\n",
326 				pmcmsptwi_data.irq);
327 			pmcmsptwi_data.irq = 0;
328 		}
329 	}
330 
331 	init_completion(&pmcmsptwi_data.wait);
332 	mutex_init(&pmcmsptwi_data.lock);
333 
334 	pmcmsptwi_set_clock_config(&pmcmsptwi_defclockcfg, &pmcmsptwi_data);
335 	pmcmsptwi_set_twi_config(&pmcmsptwi_defcfg, &pmcmsptwi_data);
336 
337 	printk(KERN_INFO DRV_NAME ": Registering MSP71xx I2C adapter\n");
338 
339 	pmcmsptwi_adapter.dev.parent = &pldev->dev;
340 	platform_set_drvdata(pldev, &pmcmsptwi_adapter);
341 	i2c_set_adapdata(&pmcmsptwi_adapter, &pmcmsptwi_data);
342 
343 	rc = i2c_add_adapter(&pmcmsptwi_adapter);
344 	if (rc) {
345 		dev_err(&pldev->dev, "Unable to register I2C adapter\n");
346 		goto ret_unmap;
347 	}
348 
349 	return 0;
350 
351 ret_unmap:
352 	if (pmcmsptwi_data.irq) {
353 		pmcmsptwi_writel(0,
354 			pmcmsptwi_data.iobase + MSP_TWI_INT_MSK_REG_OFFSET);
355 		free_irq(pmcmsptwi_data.irq, &pmcmsptwi_data);
356 	}
357 
358 	iounmap(pmcmsptwi_data.iobase);
359 
360 ret_unreserve:
361 	release_mem_region(res->start, resource_size(res));
362 
363 ret_err:
364 	return rc;
365 }
366 
367 /*
368  * Release the device and return 0 if there is one.
369  */
pmcmsptwi_remove(struct platform_device * pldev)370 static int pmcmsptwi_remove(struct platform_device *pldev)
371 {
372 	struct resource *res;
373 
374 	i2c_del_adapter(&pmcmsptwi_adapter);
375 
376 	if (pmcmsptwi_data.irq) {
377 		pmcmsptwi_writel(0,
378 			pmcmsptwi_data.iobase + MSP_TWI_INT_MSK_REG_OFFSET);
379 		free_irq(pmcmsptwi_data.irq, &pmcmsptwi_data);
380 	}
381 
382 	iounmap(pmcmsptwi_data.iobase);
383 
384 	res = platform_get_resource(pldev, IORESOURCE_MEM, 0);
385 	release_mem_region(res->start, resource_size(res));
386 
387 	return 0;
388 }
389 
390 /*
391  * Polls the 'busy' register until the command is complete.
392  * NOTE: Assumes data->lock is held.
393  */
pmcmsptwi_poll_complete(struct pmcmsptwi_data * data)394 static void pmcmsptwi_poll_complete(struct pmcmsptwi_data *data)
395 {
396 	int i;
397 
398 	for (i = 0; i < MSP_MAX_POLL; i++) {
399 		u32 val = pmcmsptwi_readl(data->iobase +
400 						MSP_TWI_BUSY_REG_OFFSET);
401 		if (val == 0) {
402 			u32 reason = pmcmsptwi_readl(data->iobase +
403 						MSP_TWI_INT_STS_REG_OFFSET);
404 			pmcmsptwi_writel(reason, data->iobase +
405 						MSP_TWI_INT_STS_REG_OFFSET);
406 			data->last_result = pmcmsptwi_get_result(reason);
407 			return;
408 		}
409 		udelay(MSP_POLL_DELAY);
410 	}
411 
412 	dev_dbg(&pmcmsptwi_adapter.dev, "Result: Poll timeout\n");
413 	data->last_result = MSP_TWI_XFER_TIMEOUT;
414 }
415 
416 /*
417  * Do the transfer (low level):
418  *   May use interrupt-driven or polling, depending on if an IRQ is
419  *   presently registered.
420  * NOTE: Assumes data->lock is held.
421  */
pmcmsptwi_do_xfer(u32 reg,struct pmcmsptwi_data * data)422 static enum pmcmsptwi_xfer_result pmcmsptwi_do_xfer(
423 			u32 reg, struct pmcmsptwi_data *data)
424 {
425 	dev_dbg(&pmcmsptwi_adapter.dev, "Writing cmd reg 0x%08x\n", reg);
426 	pmcmsptwi_writel(reg, data->iobase + MSP_TWI_CMD_REG_OFFSET);
427 	if (data->irq) {
428 		unsigned long timeleft = wait_for_completion_timeout(
429 						&data->wait, MSP_IRQ_TIMEOUT);
430 		if (timeleft == 0) {
431 			dev_dbg(&pmcmsptwi_adapter.dev,
432 				"Result: IRQ timeout\n");
433 			complete(&data->wait);
434 			data->last_result = MSP_TWI_XFER_TIMEOUT;
435 		}
436 	} else
437 		pmcmsptwi_poll_complete(data);
438 
439 	return data->last_result;
440 }
441 
442 /*
443  * Helper routine, converts 'pmctwi_cmd' struct to register format
444  */
pmcmsptwi_cmd_to_reg(const struct pmcmsptwi_cmd * cmd)445 static inline u32 pmcmsptwi_cmd_to_reg(const struct pmcmsptwi_cmd *cmd)
446 {
447 	return ((cmd->type & 0x3) << 8) |
448 		(((cmd->write_len - 1) & 0x7) << 4) |
449 		((cmd->read_len - 1) & 0x7);
450 }
451 
452 /*
453  * Do the transfer (high level)
454  */
pmcmsptwi_xfer_cmd(struct pmcmsptwi_cmd * cmd,struct pmcmsptwi_data * data)455 static enum pmcmsptwi_xfer_result pmcmsptwi_xfer_cmd(
456 			struct pmcmsptwi_cmd *cmd,
457 			struct pmcmsptwi_data *data)
458 {
459 	enum pmcmsptwi_xfer_result retval;
460 
461 	if ((cmd->type == MSP_TWI_CMD_WRITE && cmd->write_len == 0) ||
462 	    (cmd->type == MSP_TWI_CMD_READ && cmd->read_len == 0) ||
463 	    (cmd->type == MSP_TWI_CMD_WRITE_READ &&
464 	    (cmd->read_len == 0 || cmd->write_len == 0))) {
465 		dev_err(&pmcmsptwi_adapter.dev,
466 			"%s: Cannot transfer less than 1 byte\n",
467 			__func__);
468 		return -EINVAL;
469 	}
470 
471 	if (cmd->read_len > MSP_MAX_BYTES_PER_RW ||
472 	    cmd->write_len > MSP_MAX_BYTES_PER_RW) {
473 		dev_err(&pmcmsptwi_adapter.dev,
474 			"%s: Cannot transfer more than %d bytes\n",
475 			__func__, MSP_MAX_BYTES_PER_RW);
476 		return -EINVAL;
477 	}
478 
479 	mutex_lock(&data->lock);
480 	dev_dbg(&pmcmsptwi_adapter.dev,
481 		"Setting address to 0x%04x\n", cmd->addr);
482 	pmcmsptwi_writel(cmd->addr, data->iobase + MSP_TWI_ADD_REG_OFFSET);
483 
484 	if (cmd->type == MSP_TWI_CMD_WRITE ||
485 	    cmd->type == MSP_TWI_CMD_WRITE_READ) {
486 		u64 tmp = be64_to_cpup((__be64 *)cmd->write_data);
487 		tmp >>= (MSP_MAX_BYTES_PER_RW - cmd->write_len) * 8;
488 		dev_dbg(&pmcmsptwi_adapter.dev, "Writing 0x%016llx\n", tmp);
489 		pmcmsptwi_writel(tmp & 0x00000000ffffffffLL,
490 				data->iobase + MSP_TWI_DAT_0_REG_OFFSET);
491 		if (cmd->write_len > 4)
492 			pmcmsptwi_writel(tmp >> 32,
493 				data->iobase + MSP_TWI_DAT_1_REG_OFFSET);
494 	}
495 
496 	retval = pmcmsptwi_do_xfer(pmcmsptwi_cmd_to_reg(cmd), data);
497 	if (retval != MSP_TWI_XFER_OK)
498 		goto xfer_err;
499 
500 	if (cmd->type == MSP_TWI_CMD_READ ||
501 	    cmd->type == MSP_TWI_CMD_WRITE_READ) {
502 		int i;
503 		u64 rmsk = ~(0xffffffffffffffffLL << (cmd->read_len * 8));
504 		u64 tmp = (u64)pmcmsptwi_readl(data->iobase +
505 					MSP_TWI_DAT_0_REG_OFFSET);
506 		if (cmd->read_len > 4)
507 			tmp |= (u64)pmcmsptwi_readl(data->iobase +
508 					MSP_TWI_DAT_1_REG_OFFSET) << 32;
509 		tmp &= rmsk;
510 		dev_dbg(&pmcmsptwi_adapter.dev, "Read 0x%016llx\n", tmp);
511 
512 		for (i = 0; i < cmd->read_len; i++)
513 			cmd->read_data[i] = tmp >> i;
514 	}
515 
516 xfer_err:
517 	mutex_unlock(&data->lock);
518 
519 	return retval;
520 }
521 
522 /* -- Algorithm functions -- */
523 
524 /*
525  * Sends an i2c command out on the adapter
526  */
pmcmsptwi_master_xfer(struct i2c_adapter * adap,struct i2c_msg * msg,int num)527 static int pmcmsptwi_master_xfer(struct i2c_adapter *adap,
528 				struct i2c_msg *msg, int num)
529 {
530 	struct pmcmsptwi_data *data = i2c_get_adapdata(adap);
531 	struct pmcmsptwi_cmd cmd;
532 	struct pmcmsptwi_cfg oldcfg, newcfg;
533 	int ret;
534 
535 	if (num > 2) {
536 		dev_dbg(&adap->dev, "%d messages unsupported\n", num);
537 		return -EINVAL;
538 	} else if (num == 2) {
539 		/* Check for a dual write-then-read command */
540 		struct i2c_msg *nextmsg = msg + 1;
541 		if (!(msg->flags & I2C_M_RD) &&
542 		    (nextmsg->flags & I2C_M_RD) &&
543 		    msg->addr == nextmsg->addr) {
544 			cmd.type = MSP_TWI_CMD_WRITE_READ;
545 			cmd.write_len = msg->len;
546 			cmd.write_data = msg->buf;
547 			cmd.read_len = nextmsg->len;
548 			cmd.read_data = nextmsg->buf;
549 		} else {
550 			dev_dbg(&adap->dev,
551 				"Non write-read dual messages unsupported\n");
552 			return -EINVAL;
553 		}
554 	} else if (msg->flags & I2C_M_RD) {
555 		cmd.type = MSP_TWI_CMD_READ;
556 		cmd.read_len = msg->len;
557 		cmd.read_data = msg->buf;
558 		cmd.write_len = 0;
559 		cmd.write_data = NULL;
560 	} else {
561 		cmd.type = MSP_TWI_CMD_WRITE;
562 		cmd.read_len = 0;
563 		cmd.read_data = NULL;
564 		cmd.write_len = msg->len;
565 		cmd.write_data = msg->buf;
566 	}
567 
568 	if (msg->len == 0) {
569 		dev_err(&adap->dev, "Zero-byte messages unsupported\n");
570 		return -EINVAL;
571 	}
572 
573 	cmd.addr = msg->addr;
574 
575 	if (msg->flags & I2C_M_TEN) {
576 		pmcmsptwi_get_twi_config(&newcfg, data);
577 		memcpy(&oldcfg, &newcfg, sizeof(oldcfg));
578 
579 		/* Set the special 10-bit address flag */
580 		newcfg.add10 = 1;
581 
582 		pmcmsptwi_set_twi_config(&newcfg, data);
583 	}
584 
585 	/* Execute the command */
586 	ret = pmcmsptwi_xfer_cmd(&cmd, data);
587 
588 	if (msg->flags & I2C_M_TEN)
589 		pmcmsptwi_set_twi_config(&oldcfg, data);
590 
591 	dev_dbg(&adap->dev, "I2C %s of %d bytes %s\n",
592 		(msg->flags & I2C_M_RD) ? "read" : "write", msg->len,
593 		(ret == MSP_TWI_XFER_OK) ? "succeeded" : "failed");
594 
595 	if (ret != MSP_TWI_XFER_OK) {
596 		/*
597 		 * TODO: We could potentially loop and retry in the case
598 		 * of MSP_TWI_XFER_TIMEOUT.
599 		 */
600 		return -1;
601 	}
602 
603 	return 0;
604 }
605 
pmcmsptwi_i2c_func(struct i2c_adapter * adapter)606 static u32 pmcmsptwi_i2c_func(struct i2c_adapter *adapter)
607 {
608 	return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
609 		I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA |
610 		I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_PROC_CALL;
611 }
612 
613 /* -- Initialization -- */
614 
615 static struct i2c_algorithm pmcmsptwi_algo = {
616 	.master_xfer	= pmcmsptwi_master_xfer,
617 	.functionality	= pmcmsptwi_i2c_func,
618 };
619 
620 static struct i2c_adapter pmcmsptwi_adapter = {
621 	.owner		= THIS_MODULE,
622 	.class		= I2C_CLASS_HWMON | I2C_CLASS_SPD,
623 	.algo		= &pmcmsptwi_algo,
624 	.name		= DRV_NAME,
625 };
626 
627 static struct platform_driver pmcmsptwi_driver = {
628 	.probe  = pmcmsptwi_probe,
629 	.remove	= pmcmsptwi_remove,
630 	.driver = {
631 		.name	= DRV_NAME,
632 		.owner	= THIS_MODULE,
633 	},
634 };
635 
636 module_platform_driver(pmcmsptwi_driver);
637 
638 MODULE_DESCRIPTION("PMC MSP TWI/SMBus/I2C driver");
639 MODULE_LICENSE("GPL");
640 MODULE_ALIAS("platform:" DRV_NAME);
641