1 /*
2 * Copyright © 2012 Mike Dunn <mikedunn@newsguy.com>
3 *
4 * mtd nand driver for M-Systems DiskOnChip G4
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * Tested on the Palm Treo 680. The G4 is also present on Toshiba Portege, Asus
12 * P526, some HTC smartphones (Wizard, Prophet, ...), O2 XDA Zinc, maybe others.
13 * Should work on these as well. Let me know!
14 *
15 * TODO:
16 *
17 * Mechanism for management of password-protected areas
18 *
19 * Hamming ecc when reading oob only
20 *
21 * According to the M-Sys documentation, this device is also available in a
22 * "dual-die" configuration having a 256MB capacity, but no mechanism for
23 * detecting this variant is documented. Currently this driver assumes 128MB
24 * capacity.
25 *
26 * Support for multiple cascaded devices ("floors"). Not sure which gadgets
27 * contain multiple G4s in a cascaded configuration, if any.
28 *
29 */
30
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/init.h>
34 #include <linux/string.h>
35 #include <linux/sched.h>
36 #include <linux/delay.h>
37 #include <linux/module.h>
38 #include <linux/export.h>
39 #include <linux/platform_device.h>
40 #include <linux/io.h>
41 #include <linux/bitops.h>
42 #include <linux/mtd/partitions.h>
43 #include <linux/mtd/mtd.h>
44 #include <linux/mtd/nand.h>
45 #include <linux/bch.h>
46 #include <linux/bitrev.h>
47
48 /*
49 * In "reliable mode" consecutive 2k pages are used in parallel (in some
50 * fashion) to store the same data. The data can be read back from the
51 * even-numbered pages in the normal manner; odd-numbered pages will appear to
52 * contain junk. Systems that boot from the docg4 typically write the secondary
53 * program loader (SPL) code in this mode. The SPL is loaded by the initial
54 * program loader (IPL, stored in the docg4's 2k NOR-like region that is mapped
55 * to the reset vector address). This module parameter enables you to use this
56 * driver to write the SPL. When in this mode, no more than 2k of data can be
57 * written at a time, because the addresses do not increment in the normal
58 * manner, and the starting offset must be within an even-numbered 2k region;
59 * i.e., invalid starting offsets are 0x800, 0xa00, 0xc00, 0xe00, 0x1800,
60 * 0x1a00, ... Reliable mode is a special case and should not be used unless
61 * you know what you're doing.
62 */
63 static bool reliable_mode;
64 module_param(reliable_mode, bool, 0);
65 MODULE_PARM_DESC(reliable_mode, "pages are programmed in reliable mode");
66
67 /*
68 * You'll want to ignore badblocks if you're reading a partition that contains
69 * data written by the TrueFFS library (i.e., by PalmOS, Windows, etc), since
70 * it does not use mtd nand's method for marking bad blocks (using oob area).
71 * This will also skip the check of the "page written" flag.
72 */
73 static bool ignore_badblocks;
74 module_param(ignore_badblocks, bool, 0);
75 MODULE_PARM_DESC(ignore_badblocks, "no badblock checking performed");
76
77 struct docg4_priv {
78 struct mtd_info *mtd;
79 struct device *dev;
80 void __iomem *virtadr;
81 int status;
82 struct {
83 unsigned int command;
84 int column;
85 int page;
86 } last_command;
87 uint8_t oob_buf[16];
88 uint8_t ecc_buf[7];
89 int oob_page;
90 struct bch_control *bch;
91 };
92
93 /*
94 * Defines prefixed with DOCG4 are unique to the diskonchip G4. All others are
95 * shared with other diskonchip devices (P3, G3 at least).
96 *
97 * Functions with names prefixed with docg4_ are mtd / nand interface functions
98 * (though they may also be called internally). All others are internal.
99 */
100
101 #define DOC_IOSPACE_DATA 0x0800
102
103 /* register offsets */
104 #define DOC_CHIPID 0x1000
105 #define DOC_DEVICESELECT 0x100a
106 #define DOC_ASICMODE 0x100c
107 #define DOC_DATAEND 0x101e
108 #define DOC_NOP 0x103e
109
110 #define DOC_FLASHSEQUENCE 0x1032
111 #define DOC_FLASHCOMMAND 0x1034
112 #define DOC_FLASHADDRESS 0x1036
113 #define DOC_FLASHCONTROL 0x1038
114 #define DOC_ECCCONF0 0x1040
115 #define DOC_ECCCONF1 0x1042
116 #define DOC_HAMMINGPARITY 0x1046
117 #define DOC_BCH_SYNDROM(idx) (0x1048 + idx)
118
119 #define DOC_ASICMODECONFIRM 0x1072
120 #define DOC_CHIPID_INV 0x1074
121 #define DOC_POWERMODE 0x107c
122
123 #define DOCG4_MYSTERY_REG 0x1050
124
125 /* apparently used only to write oob bytes 6 and 7 */
126 #define DOCG4_OOB_6_7 0x1052
127
128 /* DOC_FLASHSEQUENCE register commands */
129 #define DOC_SEQ_RESET 0x00
130 #define DOCG4_SEQ_PAGE_READ 0x03
131 #define DOCG4_SEQ_FLUSH 0x29
132 #define DOCG4_SEQ_PAGEWRITE 0x16
133 #define DOCG4_SEQ_PAGEPROG 0x1e
134 #define DOCG4_SEQ_BLOCKERASE 0x24
135 #define DOCG4_SEQ_SETMODE 0x45
136
137 /* DOC_FLASHCOMMAND register commands */
138 #define DOCG4_CMD_PAGE_READ 0x00
139 #define DOC_CMD_ERASECYCLE2 0xd0
140 #define DOCG4_CMD_FLUSH 0x70
141 #define DOCG4_CMD_READ2 0x30
142 #define DOC_CMD_PROG_BLOCK_ADDR 0x60
143 #define DOCG4_CMD_PAGEWRITE 0x80
144 #define DOC_CMD_PROG_CYCLE2 0x10
145 #define DOCG4_CMD_FAST_MODE 0xa3 /* functionality guessed */
146 #define DOC_CMD_RELIABLE_MODE 0x22
147 #define DOC_CMD_RESET 0xff
148
149 /* DOC_POWERMODE register bits */
150 #define DOC_POWERDOWN_READY 0x80
151
152 /* DOC_FLASHCONTROL register bits */
153 #define DOC_CTRL_CE 0x10
154 #define DOC_CTRL_UNKNOWN 0x40
155 #define DOC_CTRL_FLASHREADY 0x01
156
157 /* DOC_ECCCONF0 register bits */
158 #define DOC_ECCCONF0_READ_MODE 0x8000
159 #define DOC_ECCCONF0_UNKNOWN 0x2000
160 #define DOC_ECCCONF0_ECC_ENABLE 0x1000
161 #define DOC_ECCCONF0_DATA_BYTES_MASK 0x07ff
162
163 /* DOC_ECCCONF1 register bits */
164 #define DOC_ECCCONF1_BCH_SYNDROM_ERR 0x80
165 #define DOC_ECCCONF1_ECC_ENABLE 0x07
166 #define DOC_ECCCONF1_PAGE_IS_WRITTEN 0x20
167
168 /* DOC_ASICMODE register bits */
169 #define DOC_ASICMODE_RESET 0x00
170 #define DOC_ASICMODE_NORMAL 0x01
171 #define DOC_ASICMODE_POWERDOWN 0x02
172 #define DOC_ASICMODE_MDWREN 0x04
173 #define DOC_ASICMODE_BDETCT_RESET 0x08
174 #define DOC_ASICMODE_RSTIN_RESET 0x10
175 #define DOC_ASICMODE_RAM_WE 0x20
176
177 /* good status values read after read/write/erase operations */
178 #define DOCG4_PROGSTATUS_GOOD 0x51
179 #define DOCG4_PROGSTATUS_GOOD_2 0xe0
180
181 /*
182 * On read operations (page and oob-only), the first byte read from I/O reg is a
183 * status. On error, it reads 0x73; otherwise, it reads either 0x71 (first read
184 * after reset only) or 0x51, so bit 1 is presumed to be an error indicator.
185 */
186 #define DOCG4_READ_ERROR 0x02 /* bit 1 indicates read error */
187
188 /* anatomy of the device */
189 #define DOCG4_CHIP_SIZE 0x8000000
190 #define DOCG4_PAGE_SIZE 0x200
191 #define DOCG4_PAGES_PER_BLOCK 0x200
192 #define DOCG4_BLOCK_SIZE (DOCG4_PAGES_PER_BLOCK * DOCG4_PAGE_SIZE)
193 #define DOCG4_NUMBLOCKS (DOCG4_CHIP_SIZE / DOCG4_BLOCK_SIZE)
194 #define DOCG4_OOB_SIZE 0x10
195 #define DOCG4_CHIP_SHIFT 27 /* log_2(DOCG4_CHIP_SIZE) */
196 #define DOCG4_PAGE_SHIFT 9 /* log_2(DOCG4_PAGE_SIZE) */
197 #define DOCG4_ERASE_SHIFT 18 /* log_2(DOCG4_BLOCK_SIZE) */
198
199 /* all but the last byte is included in ecc calculation */
200 #define DOCG4_BCH_SIZE (DOCG4_PAGE_SIZE + DOCG4_OOB_SIZE - 1)
201
202 #define DOCG4_USERDATA_LEN 520 /* 512 byte page plus 8 oob avail to user */
203
204 /* expected values from the ID registers */
205 #define DOCG4_IDREG1_VALUE 0x0400
206 #define DOCG4_IDREG2_VALUE 0xfbff
207
208 /* primitive polynomial used to build the Galois field used by hw ecc gen */
209 #define DOCG4_PRIMITIVE_POLY 0x4443
210
211 #define DOCG4_M 14 /* Galois field is of order 2^14 */
212 #define DOCG4_T 4 /* BCH alg corrects up to 4 bit errors */
213
214 #define DOCG4_FACTORY_BBT_PAGE 16 /* page where read-only factory bbt lives */
215 #define DOCG4_REDUNDANT_BBT_PAGE 24 /* page where redundant factory bbt lives */
216
217 /*
218 * Bytes 0, 1 are used as badblock marker.
219 * Bytes 2 - 6 are available to the user.
220 * Byte 7 is hamming ecc for first 7 oob bytes only.
221 * Bytes 8 - 14 are hw-generated ecc covering entire page + oob bytes 0 - 14.
222 * Byte 15 (the last) is used by the driver as a "page written" flag.
223 */
224 static struct nand_ecclayout docg4_oobinfo = {
225 .eccbytes = 9,
226 .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
227 .oobavail = 5,
228 .oobfree = { {.offset = 2, .length = 5} }
229 };
230
231 /*
232 * The device has a nop register which M-Sys claims is for the purpose of
233 * inserting precise delays. But beware; at least some operations fail if the
234 * nop writes are replaced with a generic delay!
235 */
write_nop(void __iomem * docptr)236 static inline void write_nop(void __iomem *docptr)
237 {
238 writew(0, docptr + DOC_NOP);
239 }
240
docg4_read_buf(struct mtd_info * mtd,uint8_t * buf,int len)241 static void docg4_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
242 {
243 int i;
244 struct nand_chip *nand = mtd->priv;
245 uint16_t *p = (uint16_t *) buf;
246 len >>= 1;
247
248 for (i = 0; i < len; i++)
249 p[i] = readw(nand->IO_ADDR_R);
250 }
251
docg4_write_buf16(struct mtd_info * mtd,const uint8_t * buf,int len)252 static void docg4_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
253 {
254 int i;
255 struct nand_chip *nand = mtd->priv;
256 uint16_t *p = (uint16_t *) buf;
257 len >>= 1;
258
259 for (i = 0; i < len; i++)
260 writew(p[i], nand->IO_ADDR_W);
261 }
262
poll_status(struct docg4_priv * doc)263 static int poll_status(struct docg4_priv *doc)
264 {
265 /*
266 * Busy-wait for the FLASHREADY bit to be set in the FLASHCONTROL
267 * register. Operations known to take a long time (e.g., block erase)
268 * should sleep for a while before calling this.
269 */
270
271 uint16_t flash_status;
272 unsigned int timeo;
273 void __iomem *docptr = doc->virtadr;
274
275 dev_dbg(doc->dev, "%s...\n", __func__);
276
277 /* hardware quirk requires reading twice initially */
278 flash_status = readw(docptr + DOC_FLASHCONTROL);
279
280 timeo = 1000;
281 do {
282 cpu_relax();
283 flash_status = readb(docptr + DOC_FLASHCONTROL);
284 } while (!(flash_status & DOC_CTRL_FLASHREADY) && --timeo);
285
286
287 if (!timeo) {
288 dev_err(doc->dev, "%s: timed out!\n", __func__);
289 return NAND_STATUS_FAIL;
290 }
291
292 if (unlikely(timeo < 50))
293 dev_warn(doc->dev, "%s: nearly timed out; %d remaining\n",
294 __func__, timeo);
295
296 return 0;
297 }
298
299
docg4_wait(struct mtd_info * mtd,struct nand_chip * nand)300 static int docg4_wait(struct mtd_info *mtd, struct nand_chip *nand)
301 {
302
303 struct docg4_priv *doc = nand->priv;
304 int status = NAND_STATUS_WP; /* inverse logic?? */
305 dev_dbg(doc->dev, "%s...\n", __func__);
306
307 /* report any previously unreported error */
308 if (doc->status) {
309 status |= doc->status;
310 doc->status = 0;
311 return status;
312 }
313
314 status |= poll_status(doc);
315 return status;
316 }
317
docg4_select_chip(struct mtd_info * mtd,int chip)318 static void docg4_select_chip(struct mtd_info *mtd, int chip)
319 {
320 /*
321 * Select among multiple cascaded chips ("floors"). Multiple floors are
322 * not yet supported, so the only valid non-negative value is 0.
323 */
324 struct nand_chip *nand = mtd->priv;
325 struct docg4_priv *doc = nand->priv;
326 void __iomem *docptr = doc->virtadr;
327
328 dev_dbg(doc->dev, "%s: chip %d\n", __func__, chip);
329
330 if (chip < 0)
331 return; /* deselected */
332
333 if (chip > 0)
334 dev_warn(doc->dev, "multiple floors currently unsupported\n");
335
336 writew(0, docptr + DOC_DEVICESELECT);
337 }
338
reset(struct mtd_info * mtd)339 static void reset(struct mtd_info *mtd)
340 {
341 /* full device reset */
342
343 struct nand_chip *nand = mtd->priv;
344 struct docg4_priv *doc = nand->priv;
345 void __iomem *docptr = doc->virtadr;
346
347 writew(DOC_ASICMODE_RESET | DOC_ASICMODE_MDWREN,
348 docptr + DOC_ASICMODE);
349 writew(~(DOC_ASICMODE_RESET | DOC_ASICMODE_MDWREN),
350 docptr + DOC_ASICMODECONFIRM);
351 write_nop(docptr);
352
353 writew(DOC_ASICMODE_NORMAL | DOC_ASICMODE_MDWREN,
354 docptr + DOC_ASICMODE);
355 writew(~(DOC_ASICMODE_NORMAL | DOC_ASICMODE_MDWREN),
356 docptr + DOC_ASICMODECONFIRM);
357
358 writew(DOC_ECCCONF1_ECC_ENABLE, docptr + DOC_ECCCONF1);
359
360 poll_status(doc);
361 }
362
read_hw_ecc(void __iomem * docptr,uint8_t * ecc_buf)363 static void read_hw_ecc(void __iomem *docptr, uint8_t *ecc_buf)
364 {
365 /* read the 7 hw-generated ecc bytes */
366
367 int i;
368 for (i = 0; i < 7; i++) { /* hw quirk; read twice */
369 ecc_buf[i] = readb(docptr + DOC_BCH_SYNDROM(i));
370 ecc_buf[i] = readb(docptr + DOC_BCH_SYNDROM(i));
371 }
372 }
373
correct_data(struct mtd_info * mtd,uint8_t * buf,int page)374 static int correct_data(struct mtd_info *mtd, uint8_t *buf, int page)
375 {
376 /*
377 * Called after a page read when hardware reports bitflips.
378 * Up to four bitflips can be corrected.
379 */
380
381 struct nand_chip *nand = mtd->priv;
382 struct docg4_priv *doc = nand->priv;
383 void __iomem *docptr = doc->virtadr;
384 int i, numerrs, errpos[4];
385 const uint8_t blank_read_hwecc[8] = {
386 0xcf, 0x72, 0xfc, 0x1b, 0xa9, 0xc7, 0xb9, 0 };
387
388 read_hw_ecc(docptr, doc->ecc_buf); /* read 7 hw-generated ecc bytes */
389
390 /* check if read error is due to a blank page */
391 if (!memcmp(doc->ecc_buf, blank_read_hwecc, 7))
392 return 0; /* yes */
393
394 /* skip additional check of "written flag" if ignore_badblocks */
395 if (ignore_badblocks == false) {
396
397 /*
398 * If the hw ecc bytes are not those of a blank page, there's
399 * still a chance that the page is blank, but was read with
400 * errors. Check the "written flag" in last oob byte, which
401 * is set to zero when a page is written. If more than half
402 * the bits are set, assume a blank page. Unfortunately, the
403 * bit flips(s) are not reported in stats.
404 */
405
406 if (nand->oob_poi[15]) {
407 int bit, numsetbits = 0;
408 unsigned long written_flag = nand->oob_poi[15];
409 for_each_set_bit(bit, &written_flag, 8)
410 numsetbits++;
411 if (numsetbits > 4) { /* assume blank */
412 dev_warn(doc->dev,
413 "error(s) in blank page "
414 "at offset %08x\n",
415 page * DOCG4_PAGE_SIZE);
416 return 0;
417 }
418 }
419 }
420
421 /*
422 * The hardware ecc unit produces oob_ecc ^ calc_ecc. The kernel's bch
423 * algorithm is used to decode this. However the hw operates on page
424 * data in a bit order that is the reverse of that of the bch alg,
425 * requiring that the bits be reversed on the result. Thanks to Ivan
426 * Djelic for his analysis!
427 */
428 for (i = 0; i < 7; i++)
429 doc->ecc_buf[i] = bitrev8(doc->ecc_buf[i]);
430
431 numerrs = decode_bch(doc->bch, NULL, DOCG4_USERDATA_LEN, NULL,
432 doc->ecc_buf, NULL, errpos);
433
434 if (numerrs == -EBADMSG) {
435 dev_warn(doc->dev, "uncorrectable errors at offset %08x\n",
436 page * DOCG4_PAGE_SIZE);
437 return -EBADMSG;
438 }
439
440 BUG_ON(numerrs < 0); /* -EINVAL, or anything other than -EBADMSG */
441
442 /* undo last step in BCH alg (modulo mirroring not needed) */
443 for (i = 0; i < numerrs; i++)
444 errpos[i] = (errpos[i] & ~7)|(7-(errpos[i] & 7));
445
446 /* fix the errors */
447 for (i = 0; i < numerrs; i++) {
448
449 /* ignore if error within oob ecc bytes */
450 if (errpos[i] > DOCG4_USERDATA_LEN * 8)
451 continue;
452
453 /* if error within oob area preceeding ecc bytes... */
454 if (errpos[i] > DOCG4_PAGE_SIZE * 8)
455 change_bit(errpos[i] - DOCG4_PAGE_SIZE * 8,
456 (unsigned long *)nand->oob_poi);
457
458 else /* error in page data */
459 change_bit(errpos[i], (unsigned long *)buf);
460 }
461
462 dev_notice(doc->dev, "%d error(s) corrected at offset %08x\n",
463 numerrs, page * DOCG4_PAGE_SIZE);
464
465 return numerrs;
466 }
467
docg4_read_byte(struct mtd_info * mtd)468 static uint8_t docg4_read_byte(struct mtd_info *mtd)
469 {
470 struct nand_chip *nand = mtd->priv;
471 struct docg4_priv *doc = nand->priv;
472
473 dev_dbg(doc->dev, "%s\n", __func__);
474
475 if (doc->last_command.command == NAND_CMD_STATUS) {
476 int status;
477
478 /*
479 * Previous nand command was status request, so nand
480 * infrastructure code expects to read the status here. If an
481 * error occurred in a previous operation, report it.
482 */
483 doc->last_command.command = 0;
484
485 if (doc->status) {
486 status = doc->status;
487 doc->status = 0;
488 }
489
490 /* why is NAND_STATUS_WP inverse logic?? */
491 else
492 status = NAND_STATUS_WP | NAND_STATUS_READY;
493
494 return status;
495 }
496
497 dev_warn(doc->dev, "unexpectd call to read_byte()\n");
498
499 return 0;
500 }
501
write_addr(struct docg4_priv * doc,uint32_t docg4_addr)502 static void write_addr(struct docg4_priv *doc, uint32_t docg4_addr)
503 {
504 /* write the four address bytes packed in docg4_addr to the device */
505
506 void __iomem *docptr = doc->virtadr;
507 writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
508 docg4_addr >>= 8;
509 writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
510 docg4_addr >>= 8;
511 writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
512 docg4_addr >>= 8;
513 writeb(docg4_addr & 0xff, docptr + DOC_FLASHADDRESS);
514 }
515
read_progstatus(struct docg4_priv * doc)516 static int read_progstatus(struct docg4_priv *doc)
517 {
518 /*
519 * This apparently checks the status of programming. Done after an
520 * erasure, and after page data is written. On error, the status is
521 * saved, to be later retrieved by the nand infrastructure code.
522 */
523 void __iomem *docptr = doc->virtadr;
524
525 /* status is read from the I/O reg */
526 uint16_t status1 = readw(docptr + DOC_IOSPACE_DATA);
527 uint16_t status2 = readw(docptr + DOC_IOSPACE_DATA);
528 uint16_t status3 = readw(docptr + DOCG4_MYSTERY_REG);
529
530 dev_dbg(doc->dev, "docg4: %s: %02x %02x %02x\n",
531 __func__, status1, status2, status3);
532
533 if (status1 != DOCG4_PROGSTATUS_GOOD
534 || status2 != DOCG4_PROGSTATUS_GOOD_2
535 || status3 != DOCG4_PROGSTATUS_GOOD_2) {
536 doc->status = NAND_STATUS_FAIL;
537 dev_warn(doc->dev, "read_progstatus failed: "
538 "%02x, %02x, %02x\n", status1, status2, status3);
539 return -EIO;
540 }
541 return 0;
542 }
543
pageprog(struct mtd_info * mtd)544 static int pageprog(struct mtd_info *mtd)
545 {
546 /*
547 * Final step in writing a page. Writes the contents of its
548 * internal buffer out to the flash array, or some such.
549 */
550
551 struct nand_chip *nand = mtd->priv;
552 struct docg4_priv *doc = nand->priv;
553 void __iomem *docptr = doc->virtadr;
554 int retval = 0;
555
556 dev_dbg(doc->dev, "docg4: %s\n", __func__);
557
558 writew(DOCG4_SEQ_PAGEPROG, docptr + DOC_FLASHSEQUENCE);
559 writew(DOC_CMD_PROG_CYCLE2, docptr + DOC_FLASHCOMMAND);
560 write_nop(docptr);
561 write_nop(docptr);
562
563 /* Just busy-wait; usleep_range() slows things down noticeably. */
564 poll_status(doc);
565
566 writew(DOCG4_SEQ_FLUSH, docptr + DOC_FLASHSEQUENCE);
567 writew(DOCG4_CMD_FLUSH, docptr + DOC_FLASHCOMMAND);
568 writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0);
569 write_nop(docptr);
570 write_nop(docptr);
571 write_nop(docptr);
572 write_nop(docptr);
573 write_nop(docptr);
574
575 retval = read_progstatus(doc);
576 writew(0, docptr + DOC_DATAEND);
577 write_nop(docptr);
578 poll_status(doc);
579 write_nop(docptr);
580
581 return retval;
582 }
583
sequence_reset(struct mtd_info * mtd)584 static void sequence_reset(struct mtd_info *mtd)
585 {
586 /* common starting sequence for all operations */
587
588 struct nand_chip *nand = mtd->priv;
589 struct docg4_priv *doc = nand->priv;
590 void __iomem *docptr = doc->virtadr;
591
592 writew(DOC_CTRL_UNKNOWN | DOC_CTRL_CE, docptr + DOC_FLASHCONTROL);
593 writew(DOC_SEQ_RESET, docptr + DOC_FLASHSEQUENCE);
594 writew(DOC_CMD_RESET, docptr + DOC_FLASHCOMMAND);
595 write_nop(docptr);
596 write_nop(docptr);
597 poll_status(doc);
598 write_nop(docptr);
599 }
600
read_page_prologue(struct mtd_info * mtd,uint32_t docg4_addr)601 static void read_page_prologue(struct mtd_info *mtd, uint32_t docg4_addr)
602 {
603 /* first step in reading a page */
604
605 struct nand_chip *nand = mtd->priv;
606 struct docg4_priv *doc = nand->priv;
607 void __iomem *docptr = doc->virtadr;
608
609 dev_dbg(doc->dev,
610 "docg4: %s: g4 page %08x\n", __func__, docg4_addr);
611
612 sequence_reset(mtd);
613
614 writew(DOCG4_SEQ_PAGE_READ, docptr + DOC_FLASHSEQUENCE);
615 writew(DOCG4_CMD_PAGE_READ, docptr + DOC_FLASHCOMMAND);
616 write_nop(docptr);
617
618 write_addr(doc, docg4_addr);
619
620 write_nop(docptr);
621 writew(DOCG4_CMD_READ2, docptr + DOC_FLASHCOMMAND);
622 write_nop(docptr);
623 write_nop(docptr);
624
625 poll_status(doc);
626 }
627
write_page_prologue(struct mtd_info * mtd,uint32_t docg4_addr)628 static void write_page_prologue(struct mtd_info *mtd, uint32_t docg4_addr)
629 {
630 /* first step in writing a page */
631
632 struct nand_chip *nand = mtd->priv;
633 struct docg4_priv *doc = nand->priv;
634 void __iomem *docptr = doc->virtadr;
635
636 dev_dbg(doc->dev,
637 "docg4: %s: g4 addr: %x\n", __func__, docg4_addr);
638 sequence_reset(mtd);
639
640 if (unlikely(reliable_mode)) {
641 writew(DOCG4_SEQ_SETMODE, docptr + DOC_FLASHSEQUENCE);
642 writew(DOCG4_CMD_FAST_MODE, docptr + DOC_FLASHCOMMAND);
643 writew(DOC_CMD_RELIABLE_MODE, docptr + DOC_FLASHCOMMAND);
644 write_nop(docptr);
645 }
646
647 writew(DOCG4_SEQ_PAGEWRITE, docptr + DOC_FLASHSEQUENCE);
648 writew(DOCG4_CMD_PAGEWRITE, docptr + DOC_FLASHCOMMAND);
649 write_nop(docptr);
650 write_addr(doc, docg4_addr);
651 write_nop(docptr);
652 write_nop(docptr);
653 poll_status(doc);
654 }
655
mtd_to_docg4_address(int page,int column)656 static uint32_t mtd_to_docg4_address(int page, int column)
657 {
658 /*
659 * Convert mtd address to format used by the device, 32 bit packed.
660 *
661 * Some notes on G4 addressing... The M-Sys documentation on this device
662 * claims that pages are 2K in length, and indeed, the format of the
663 * address used by the device reflects that. But within each page are
664 * four 512 byte "sub-pages", each with its own oob data that is
665 * read/written immediately after the 512 bytes of page data. This oob
666 * data contains the ecc bytes for the preceeding 512 bytes.
667 *
668 * Rather than tell the mtd nand infrastructure that page size is 2k,
669 * with four sub-pages each, we engage in a little subterfuge and tell
670 * the infrastructure code that pages are 512 bytes in size. This is
671 * done because during the course of reverse-engineering the device, I
672 * never observed an instance where an entire 2K "page" was read or
673 * written as a unit. Each "sub-page" is always addressed individually,
674 * its data read/written, and ecc handled before the next "sub-page" is
675 * addressed.
676 *
677 * This requires us to convert addresses passed by the mtd nand
678 * infrastructure code to those used by the device.
679 *
680 * The address that is written to the device consists of four bytes: the
681 * first two are the 2k page number, and the second is the index into
682 * the page. The index is in terms of 16-bit half-words and includes
683 * the preceeding oob data, so e.g., the index into the second
684 * "sub-page" is 0x108, and the full device address of the start of mtd
685 * page 0x201 is 0x00800108.
686 */
687 int g4_page = page / 4; /* device's 2K page */
688 int g4_index = (page % 4) * 0x108 + column/2; /* offset into page */
689 return (g4_page << 16) | g4_index; /* pack */
690 }
691
docg4_command(struct mtd_info * mtd,unsigned command,int column,int page_addr)692 static void docg4_command(struct mtd_info *mtd, unsigned command, int column,
693 int page_addr)
694 {
695 /* handle standard nand commands */
696
697 struct nand_chip *nand = mtd->priv;
698 struct docg4_priv *doc = nand->priv;
699 uint32_t g4_addr = mtd_to_docg4_address(page_addr, column);
700
701 dev_dbg(doc->dev, "%s %x, page_addr=%x, column=%x\n",
702 __func__, command, page_addr, column);
703
704 /*
705 * Save the command and its arguments. This enables emulation of
706 * standard flash devices, and also some optimizations.
707 */
708 doc->last_command.command = command;
709 doc->last_command.column = column;
710 doc->last_command.page = page_addr;
711
712 switch (command) {
713
714 case NAND_CMD_RESET:
715 reset(mtd);
716 break;
717
718 case NAND_CMD_READ0:
719 read_page_prologue(mtd, g4_addr);
720 break;
721
722 case NAND_CMD_STATUS:
723 /* next call to read_byte() will expect a status */
724 break;
725
726 case NAND_CMD_SEQIN:
727 if (unlikely(reliable_mode)) {
728 uint16_t g4_page = g4_addr >> 16;
729
730 /* writes to odd-numbered 2k pages are invalid */
731 if (g4_page & 0x01)
732 dev_warn(doc->dev,
733 "invalid reliable mode address\n");
734 }
735
736 write_page_prologue(mtd, g4_addr);
737
738 /* hack for deferred write of oob bytes */
739 if (doc->oob_page == page_addr)
740 memcpy(nand->oob_poi, doc->oob_buf, 16);
741 break;
742
743 case NAND_CMD_PAGEPROG:
744 pageprog(mtd);
745 break;
746
747 /* we don't expect these, based on review of nand_base.c */
748 case NAND_CMD_READOOB:
749 case NAND_CMD_READID:
750 case NAND_CMD_ERASE1:
751 case NAND_CMD_ERASE2:
752 dev_warn(doc->dev, "docg4_command: "
753 "unexpected nand command 0x%x\n", command);
754 break;
755
756 }
757 }
758
read_page(struct mtd_info * mtd,struct nand_chip * nand,uint8_t * buf,int page,bool use_ecc)759 static int read_page(struct mtd_info *mtd, struct nand_chip *nand,
760 uint8_t *buf, int page, bool use_ecc)
761 {
762 struct docg4_priv *doc = nand->priv;
763 void __iomem *docptr = doc->virtadr;
764 uint16_t status, edc_err, *buf16;
765 int bits_corrected = 0;
766
767 dev_dbg(doc->dev, "%s: page %08x\n", __func__, page);
768
769 writew(DOC_ECCCONF0_READ_MODE |
770 DOC_ECCCONF0_ECC_ENABLE |
771 DOC_ECCCONF0_UNKNOWN |
772 DOCG4_BCH_SIZE,
773 docptr + DOC_ECCCONF0);
774 write_nop(docptr);
775 write_nop(docptr);
776 write_nop(docptr);
777 write_nop(docptr);
778 write_nop(docptr);
779
780 /* the 1st byte from the I/O reg is a status; the rest is page data */
781 status = readw(docptr + DOC_IOSPACE_DATA);
782 if (status & DOCG4_READ_ERROR) {
783 dev_err(doc->dev,
784 "docg4_read_page: bad status: 0x%02x\n", status);
785 writew(0, docptr + DOC_DATAEND);
786 return -EIO;
787 }
788
789 dev_dbg(doc->dev, "%s: status = 0x%x\n", __func__, status);
790
791 docg4_read_buf(mtd, buf, DOCG4_PAGE_SIZE); /* read the page data */
792
793 /* this device always reads oob after page data */
794 /* first 14 oob bytes read from I/O reg */
795 docg4_read_buf(mtd, nand->oob_poi, 14);
796
797 /* last 2 read from another reg */
798 buf16 = (uint16_t *)(nand->oob_poi + 14);
799 *buf16 = readw(docptr + DOCG4_MYSTERY_REG);
800
801 write_nop(docptr);
802
803 if (likely(use_ecc == true)) {
804
805 /* read the register that tells us if bitflip(s) detected */
806 edc_err = readw(docptr + DOC_ECCCONF1);
807 edc_err = readw(docptr + DOC_ECCCONF1);
808 dev_dbg(doc->dev, "%s: edc_err = 0x%02x\n", __func__, edc_err);
809
810 /* If bitflips are reported, attempt to correct with ecc */
811 if (edc_err & DOC_ECCCONF1_BCH_SYNDROM_ERR) {
812 bits_corrected = correct_data(mtd, buf, page);
813 if (bits_corrected == -EBADMSG)
814 mtd->ecc_stats.failed++;
815 else
816 mtd->ecc_stats.corrected += bits_corrected;
817 }
818 }
819
820 writew(0, docptr + DOC_DATAEND);
821 if (bits_corrected == -EBADMSG) /* uncorrectable errors */
822 return 0;
823 return bits_corrected;
824 }
825
826
docg4_read_page_raw(struct mtd_info * mtd,struct nand_chip * nand,uint8_t * buf,int oob_required,int page)827 static int docg4_read_page_raw(struct mtd_info *mtd, struct nand_chip *nand,
828 uint8_t *buf, int oob_required, int page)
829 {
830 return read_page(mtd, nand, buf, page, false);
831 }
832
docg4_read_page(struct mtd_info * mtd,struct nand_chip * nand,uint8_t * buf,int oob_required,int page)833 static int docg4_read_page(struct mtd_info *mtd, struct nand_chip *nand,
834 uint8_t *buf, int oob_required, int page)
835 {
836 return read_page(mtd, nand, buf, page, true);
837 }
838
docg4_read_oob(struct mtd_info * mtd,struct nand_chip * nand,int page)839 static int docg4_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
840 int page)
841 {
842 struct docg4_priv *doc = nand->priv;
843 void __iomem *docptr = doc->virtadr;
844 uint16_t status;
845
846 dev_dbg(doc->dev, "%s: page %x\n", __func__, page);
847
848 docg4_command(mtd, NAND_CMD_READ0, nand->ecc.size, page);
849
850 writew(DOC_ECCCONF0_READ_MODE | DOCG4_OOB_SIZE, docptr + DOC_ECCCONF0);
851 write_nop(docptr);
852 write_nop(docptr);
853 write_nop(docptr);
854 write_nop(docptr);
855 write_nop(docptr);
856
857 /* the 1st byte from the I/O reg is a status; the rest is oob data */
858 status = readw(docptr + DOC_IOSPACE_DATA);
859 if (status & DOCG4_READ_ERROR) {
860 dev_warn(doc->dev,
861 "docg4_read_oob failed: status = 0x%02x\n", status);
862 return -EIO;
863 }
864
865 dev_dbg(doc->dev, "%s: status = 0x%x\n", __func__, status);
866
867 docg4_read_buf(mtd, nand->oob_poi, 16);
868
869 write_nop(docptr);
870 write_nop(docptr);
871 write_nop(docptr);
872 writew(0, docptr + DOC_DATAEND);
873 write_nop(docptr);
874
875 return 0;
876 }
877
docg4_erase_block(struct mtd_info * mtd,int page)878 static void docg4_erase_block(struct mtd_info *mtd, int page)
879 {
880 struct nand_chip *nand = mtd->priv;
881 struct docg4_priv *doc = nand->priv;
882 void __iomem *docptr = doc->virtadr;
883 uint16_t g4_page;
884
885 dev_dbg(doc->dev, "%s: page %04x\n", __func__, page);
886
887 sequence_reset(mtd);
888
889 writew(DOCG4_SEQ_BLOCKERASE, docptr + DOC_FLASHSEQUENCE);
890 writew(DOC_CMD_PROG_BLOCK_ADDR, docptr + DOC_FLASHCOMMAND);
891 write_nop(docptr);
892
893 /* only 2 bytes of address are written to specify erase block */
894 g4_page = (uint16_t)(page / 4); /* to g4's 2k page addressing */
895 writeb(g4_page & 0xff, docptr + DOC_FLASHADDRESS);
896 g4_page >>= 8;
897 writeb(g4_page & 0xff, docptr + DOC_FLASHADDRESS);
898 write_nop(docptr);
899
900 /* start the erasure */
901 writew(DOC_CMD_ERASECYCLE2, docptr + DOC_FLASHCOMMAND);
902 write_nop(docptr);
903 write_nop(docptr);
904
905 usleep_range(500, 1000); /* erasure is long; take a snooze */
906 poll_status(doc);
907 writew(DOCG4_SEQ_FLUSH, docptr + DOC_FLASHSEQUENCE);
908 writew(DOCG4_CMD_FLUSH, docptr + DOC_FLASHCOMMAND);
909 writew(DOC_ECCCONF0_READ_MODE | 4, docptr + DOC_ECCCONF0);
910 write_nop(docptr);
911 write_nop(docptr);
912 write_nop(docptr);
913 write_nop(docptr);
914 write_nop(docptr);
915
916 read_progstatus(doc);
917
918 writew(0, docptr + DOC_DATAEND);
919 write_nop(docptr);
920 poll_status(doc);
921 write_nop(docptr);
922 }
923
write_page(struct mtd_info * mtd,struct nand_chip * nand,const uint8_t * buf,bool use_ecc)924 static int write_page(struct mtd_info *mtd, struct nand_chip *nand,
925 const uint8_t *buf, bool use_ecc)
926 {
927 struct docg4_priv *doc = nand->priv;
928 void __iomem *docptr = doc->virtadr;
929 uint8_t ecc_buf[8];
930
931 dev_dbg(doc->dev, "%s...\n", __func__);
932
933 writew(DOC_ECCCONF0_ECC_ENABLE |
934 DOC_ECCCONF0_UNKNOWN |
935 DOCG4_BCH_SIZE,
936 docptr + DOC_ECCCONF0);
937 write_nop(docptr);
938
939 /* write the page data */
940 docg4_write_buf16(mtd, buf, DOCG4_PAGE_SIZE);
941
942 /* oob bytes 0 through 5 are written to I/O reg */
943 docg4_write_buf16(mtd, nand->oob_poi, 6);
944
945 /* oob byte 6 written to a separate reg */
946 writew(nand->oob_poi[6], docptr + DOCG4_OOB_6_7);
947
948 write_nop(docptr);
949 write_nop(docptr);
950
951 /* write hw-generated ecc bytes to oob */
952 if (likely(use_ecc == true)) {
953 /* oob byte 7 is hamming code */
954 uint8_t hamming = readb(docptr + DOC_HAMMINGPARITY);
955 hamming = readb(docptr + DOC_HAMMINGPARITY); /* 2nd read */
956 writew(hamming, docptr + DOCG4_OOB_6_7);
957 write_nop(docptr);
958
959 /* read the 7 bch bytes from ecc regs */
960 read_hw_ecc(docptr, ecc_buf);
961 ecc_buf[7] = 0; /* clear the "page written" flag */
962 }
963
964 /* write user-supplied bytes to oob */
965 else {
966 writew(nand->oob_poi[7], docptr + DOCG4_OOB_6_7);
967 write_nop(docptr);
968 memcpy(ecc_buf, &nand->oob_poi[8], 8);
969 }
970
971 docg4_write_buf16(mtd, ecc_buf, 8);
972 write_nop(docptr);
973 write_nop(docptr);
974 writew(0, docptr + DOC_DATAEND);
975 write_nop(docptr);
976
977 return 0;
978 }
979
docg4_write_page_raw(struct mtd_info * mtd,struct nand_chip * nand,const uint8_t * buf,int oob_required)980 static int docg4_write_page_raw(struct mtd_info *mtd, struct nand_chip *nand,
981 const uint8_t *buf, int oob_required)
982 {
983 return write_page(mtd, nand, buf, false);
984 }
985
docg4_write_page(struct mtd_info * mtd,struct nand_chip * nand,const uint8_t * buf,int oob_required)986 static int docg4_write_page(struct mtd_info *mtd, struct nand_chip *nand,
987 const uint8_t *buf, int oob_required)
988 {
989 return write_page(mtd, nand, buf, true);
990 }
991
docg4_write_oob(struct mtd_info * mtd,struct nand_chip * nand,int page)992 static int docg4_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
993 int page)
994 {
995 /*
996 * Writing oob-only is not really supported, because MLC nand must write
997 * oob bytes at the same time as page data. Nonetheless, we save the
998 * oob buffer contents here, and then write it along with the page data
999 * if the same page is subsequently written. This allows user space
1000 * utilities that write the oob data prior to the page data to work
1001 * (e.g., nandwrite). The disdvantage is that, if the intention was to
1002 * write oob only, the operation is quietly ignored. Also, oob can get
1003 * corrupted if two concurrent processes are running nandwrite.
1004 */
1005
1006 /* note that bytes 7..14 are hw generated hamming/ecc and overwritten */
1007 struct docg4_priv *doc = nand->priv;
1008 doc->oob_page = page;
1009 memcpy(doc->oob_buf, nand->oob_poi, 16);
1010 return 0;
1011 }
1012
read_factory_bbt(struct mtd_info * mtd)1013 static int __init read_factory_bbt(struct mtd_info *mtd)
1014 {
1015 /*
1016 * The device contains a read-only factory bad block table. Read it and
1017 * update the memory-based bbt accordingly.
1018 */
1019
1020 struct nand_chip *nand = mtd->priv;
1021 struct docg4_priv *doc = nand->priv;
1022 uint32_t g4_addr = mtd_to_docg4_address(DOCG4_FACTORY_BBT_PAGE, 0);
1023 uint8_t *buf;
1024 int i, block;
1025 __u32 eccfailed_stats = mtd->ecc_stats.failed;
1026
1027 buf = kzalloc(DOCG4_PAGE_SIZE, GFP_KERNEL);
1028 if (buf == NULL)
1029 return -ENOMEM;
1030
1031 read_page_prologue(mtd, g4_addr);
1032 docg4_read_page(mtd, nand, buf, 0, DOCG4_FACTORY_BBT_PAGE);
1033
1034 /*
1035 * If no memory-based bbt was created, exit. This will happen if module
1036 * parameter ignore_badblocks is set. Then why even call this function?
1037 * For an unknown reason, block erase always fails if it's the first
1038 * operation after device power-up. The above read ensures it never is.
1039 * Ugly, I know.
1040 */
1041 if (nand->bbt == NULL) /* no memory-based bbt */
1042 goto exit;
1043
1044 if (mtd->ecc_stats.failed > eccfailed_stats) {
1045 /*
1046 * Whoops, an ecc failure ocurred reading the factory bbt.
1047 * It is stored redundantly, so we get another chance.
1048 */
1049 eccfailed_stats = mtd->ecc_stats.failed;
1050 docg4_read_page(mtd, nand, buf, 0, DOCG4_REDUNDANT_BBT_PAGE);
1051 if (mtd->ecc_stats.failed > eccfailed_stats) {
1052 dev_warn(doc->dev,
1053 "The factory bbt could not be read!\n");
1054 goto exit;
1055 }
1056 }
1057
1058 /*
1059 * Parse factory bbt and update memory-based bbt. Factory bbt format is
1060 * simple: one bit per block, block numbers increase left to right (msb
1061 * to lsb). Bit clear means bad block.
1062 */
1063 for (i = block = 0; block < DOCG4_NUMBLOCKS; block += 8, i++) {
1064 int bitnum;
1065 unsigned long bits = ~buf[i];
1066 for_each_set_bit(bitnum, &bits, 8) {
1067 int badblock = block + 7 - bitnum;
1068 nand->bbt[badblock / 4] |=
1069 0x03 << ((badblock % 4) * 2);
1070 mtd->ecc_stats.badblocks++;
1071 dev_notice(doc->dev, "factory-marked bad block: %d\n",
1072 badblock);
1073 }
1074 }
1075 exit:
1076 kfree(buf);
1077 return 0;
1078 }
1079
docg4_block_markbad(struct mtd_info * mtd,loff_t ofs)1080 static int docg4_block_markbad(struct mtd_info *mtd, loff_t ofs)
1081 {
1082 /*
1083 * Mark a block as bad. Bad blocks are marked in the oob area of the
1084 * first page of the block. The default scan_bbt() in the nand
1085 * infrastructure code works fine for building the memory-based bbt
1086 * during initialization, as does the nand infrastructure function that
1087 * checks if a block is bad by reading the bbt. This function replaces
1088 * the nand default because writes to oob-only are not supported.
1089 */
1090
1091 int ret, i;
1092 uint8_t *buf;
1093 struct nand_chip *nand = mtd->priv;
1094 struct docg4_priv *doc = nand->priv;
1095 struct nand_bbt_descr *bbtd = nand->badblock_pattern;
1096 int block = (int)(ofs >> nand->bbt_erase_shift);
1097 int page = (int)(ofs >> nand->page_shift);
1098 uint32_t g4_addr = mtd_to_docg4_address(page, 0);
1099
1100 dev_dbg(doc->dev, "%s: %08llx\n", __func__, ofs);
1101
1102 if (unlikely(ofs & (DOCG4_BLOCK_SIZE - 1)))
1103 dev_warn(doc->dev, "%s: ofs %llx not start of block!\n",
1104 __func__, ofs);
1105
1106 /* allocate blank buffer for page data */
1107 buf = kzalloc(DOCG4_PAGE_SIZE, GFP_KERNEL);
1108 if (buf == NULL)
1109 return -ENOMEM;
1110
1111 /* update bbt in memory */
1112 nand->bbt[block / 4] |= 0x01 << ((block & 0x03) * 2);
1113
1114 /* write bit-wise negation of pattern to oob buffer */
1115 memset(nand->oob_poi, 0xff, mtd->oobsize);
1116 for (i = 0; i < bbtd->len; i++)
1117 nand->oob_poi[bbtd->offs + i] = ~bbtd->pattern[i];
1118
1119 /* write first page of block */
1120 write_page_prologue(mtd, g4_addr);
1121 docg4_write_page(mtd, nand, buf, 1);
1122 ret = pageprog(mtd);
1123 if (!ret)
1124 mtd->ecc_stats.badblocks++;
1125
1126 kfree(buf);
1127
1128 return ret;
1129 }
1130
docg4_block_neverbad(struct mtd_info * mtd,loff_t ofs,int getchip)1131 static int docg4_block_neverbad(struct mtd_info *mtd, loff_t ofs, int getchip)
1132 {
1133 /* only called when module_param ignore_badblocks is set */
1134 return 0;
1135 }
1136
docg4_suspend(struct platform_device * pdev,pm_message_t state)1137 static int docg4_suspend(struct platform_device *pdev, pm_message_t state)
1138 {
1139 /*
1140 * Put the device into "deep power-down" mode. Note that CE# must be
1141 * deasserted for this to take effect. The xscale, e.g., can be
1142 * configured to float this signal when the processor enters power-down,
1143 * and a suitable pull-up ensures its deassertion.
1144 */
1145
1146 int i;
1147 uint8_t pwr_down;
1148 struct docg4_priv *doc = platform_get_drvdata(pdev);
1149 void __iomem *docptr = doc->virtadr;
1150
1151 dev_dbg(doc->dev, "%s...\n", __func__);
1152
1153 /* poll the register that tells us we're ready to go to sleep */
1154 for (i = 0; i < 10; i++) {
1155 pwr_down = readb(docptr + DOC_POWERMODE);
1156 if (pwr_down & DOC_POWERDOWN_READY)
1157 break;
1158 usleep_range(1000, 4000);
1159 }
1160
1161 if (pwr_down & DOC_POWERDOWN_READY) {
1162 dev_err(doc->dev, "suspend failed; "
1163 "timeout polling DOC_POWERDOWN_READY\n");
1164 return -EIO;
1165 }
1166
1167 writew(DOC_ASICMODE_POWERDOWN | DOC_ASICMODE_MDWREN,
1168 docptr + DOC_ASICMODE);
1169 writew(~(DOC_ASICMODE_POWERDOWN | DOC_ASICMODE_MDWREN),
1170 docptr + DOC_ASICMODECONFIRM);
1171
1172 write_nop(docptr);
1173
1174 return 0;
1175 }
1176
docg4_resume(struct platform_device * pdev)1177 static int docg4_resume(struct platform_device *pdev)
1178 {
1179
1180 /*
1181 * Exit power-down. Twelve consecutive reads of the address below
1182 * accomplishes this, assuming CE# has been asserted.
1183 */
1184
1185 struct docg4_priv *doc = platform_get_drvdata(pdev);
1186 void __iomem *docptr = doc->virtadr;
1187 int i;
1188
1189 dev_dbg(doc->dev, "%s...\n", __func__);
1190
1191 for (i = 0; i < 12; i++)
1192 readb(docptr + 0x1fff);
1193
1194 return 0;
1195 }
1196
init_mtd_structs(struct mtd_info * mtd)1197 static void __init init_mtd_structs(struct mtd_info *mtd)
1198 {
1199 /* initialize mtd and nand data structures */
1200
1201 /*
1202 * Note that some of the following initializations are not usually
1203 * required within a nand driver because they are performed by the nand
1204 * infrastructure code as part of nand_scan(). In this case they need
1205 * to be initialized here because we skip call to nand_scan_ident() (the
1206 * first half of nand_scan()). The call to nand_scan_ident() is skipped
1207 * because for this device the chip id is not read in the manner of a
1208 * standard nand device. Unfortunately, nand_scan_ident() does other
1209 * things as well, such as call nand_set_defaults().
1210 */
1211
1212 struct nand_chip *nand = mtd->priv;
1213 struct docg4_priv *doc = nand->priv;
1214
1215 mtd->size = DOCG4_CHIP_SIZE;
1216 mtd->name = "Msys_Diskonchip_G4";
1217 mtd->writesize = DOCG4_PAGE_SIZE;
1218 mtd->erasesize = DOCG4_BLOCK_SIZE;
1219 mtd->oobsize = DOCG4_OOB_SIZE;
1220 nand->chipsize = DOCG4_CHIP_SIZE;
1221 nand->chip_shift = DOCG4_CHIP_SHIFT;
1222 nand->bbt_erase_shift = nand->phys_erase_shift = DOCG4_ERASE_SHIFT;
1223 nand->chip_delay = 20;
1224 nand->page_shift = DOCG4_PAGE_SHIFT;
1225 nand->pagemask = 0x3ffff;
1226 nand->badblockpos = NAND_LARGE_BADBLOCK_POS;
1227 nand->badblockbits = 8;
1228 nand->ecc.layout = &docg4_oobinfo;
1229 nand->ecc.mode = NAND_ECC_HW_SYNDROME;
1230 nand->ecc.size = DOCG4_PAGE_SIZE;
1231 nand->ecc.prepad = 8;
1232 nand->ecc.bytes = 8;
1233 nand->ecc.strength = DOCG4_T;
1234 nand->options = NAND_BUSWIDTH_16 | NAND_NO_SUBPAGE_WRITE;
1235 nand->IO_ADDR_R = nand->IO_ADDR_W = doc->virtadr + DOC_IOSPACE_DATA;
1236 nand->controller = &nand->hwcontrol;
1237 spin_lock_init(&nand->controller->lock);
1238 init_waitqueue_head(&nand->controller->wq);
1239
1240 /* methods */
1241 nand->cmdfunc = docg4_command;
1242 nand->waitfunc = docg4_wait;
1243 nand->select_chip = docg4_select_chip;
1244 nand->read_byte = docg4_read_byte;
1245 nand->block_markbad = docg4_block_markbad;
1246 nand->read_buf = docg4_read_buf;
1247 nand->write_buf = docg4_write_buf16;
1248 nand->scan_bbt = nand_default_bbt;
1249 nand->erase_cmd = docg4_erase_block;
1250 nand->ecc.read_page = docg4_read_page;
1251 nand->ecc.write_page = docg4_write_page;
1252 nand->ecc.read_page_raw = docg4_read_page_raw;
1253 nand->ecc.write_page_raw = docg4_write_page_raw;
1254 nand->ecc.read_oob = docg4_read_oob;
1255 nand->ecc.write_oob = docg4_write_oob;
1256
1257 /*
1258 * The way the nand infrastructure code is written, a memory-based bbt
1259 * is not created if NAND_SKIP_BBTSCAN is set. With no memory bbt,
1260 * nand->block_bad() is used. So when ignoring bad blocks, we skip the
1261 * scan and define a dummy block_bad() which always returns 0.
1262 */
1263 if (ignore_badblocks) {
1264 nand->options |= NAND_SKIP_BBTSCAN;
1265 nand->block_bad = docg4_block_neverbad;
1266 }
1267
1268 }
1269
read_id_reg(struct mtd_info * mtd)1270 static int __init read_id_reg(struct mtd_info *mtd)
1271 {
1272 struct nand_chip *nand = mtd->priv;
1273 struct docg4_priv *doc = nand->priv;
1274 void __iomem *docptr = doc->virtadr;
1275 uint16_t id1, id2;
1276
1277 /* check for presence of g4 chip by reading id registers */
1278 id1 = readw(docptr + DOC_CHIPID);
1279 id1 = readw(docptr + DOCG4_MYSTERY_REG);
1280 id2 = readw(docptr + DOC_CHIPID_INV);
1281 id2 = readw(docptr + DOCG4_MYSTERY_REG);
1282
1283 if (id1 == DOCG4_IDREG1_VALUE && id2 == DOCG4_IDREG2_VALUE) {
1284 dev_info(doc->dev,
1285 "NAND device: 128MiB Diskonchip G4 detected\n");
1286 return 0;
1287 }
1288
1289 return -ENODEV;
1290 }
1291
1292 static char const *part_probes[] = { "cmdlinepart", "saftlpart", NULL };
1293
probe_docg4(struct platform_device * pdev)1294 static int __init probe_docg4(struct platform_device *pdev)
1295 {
1296 struct mtd_info *mtd;
1297 struct nand_chip *nand;
1298 void __iomem *virtadr;
1299 struct docg4_priv *doc;
1300 int len, retval;
1301 struct resource *r;
1302 struct device *dev = &pdev->dev;
1303
1304 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1305 if (r == NULL) {
1306 dev_err(dev, "no io memory resource defined!\n");
1307 return -ENODEV;
1308 }
1309
1310 virtadr = ioremap(r->start, resource_size(r));
1311 if (!virtadr) {
1312 dev_err(dev, "Diskonchip ioremap failed: %pR\n", r);
1313 return -EIO;
1314 }
1315
1316 len = sizeof(struct mtd_info) + sizeof(struct nand_chip) +
1317 sizeof(struct docg4_priv);
1318 mtd = kzalloc(len, GFP_KERNEL);
1319 if (mtd == NULL) {
1320 retval = -ENOMEM;
1321 goto fail;
1322 }
1323 nand = (struct nand_chip *) (mtd + 1);
1324 doc = (struct docg4_priv *) (nand + 1);
1325 mtd->priv = nand;
1326 nand->priv = doc;
1327 mtd->owner = THIS_MODULE;
1328 doc->virtadr = virtadr;
1329 doc->dev = dev;
1330
1331 init_mtd_structs(mtd);
1332
1333 /* initialize kernel bch algorithm */
1334 doc->bch = init_bch(DOCG4_M, DOCG4_T, DOCG4_PRIMITIVE_POLY);
1335 if (doc->bch == NULL) {
1336 retval = -EINVAL;
1337 goto fail;
1338 }
1339
1340 platform_set_drvdata(pdev, doc);
1341
1342 reset(mtd);
1343 retval = read_id_reg(mtd);
1344 if (retval == -ENODEV) {
1345 dev_warn(dev, "No diskonchip G4 device found.\n");
1346 goto fail;
1347 }
1348
1349 retval = nand_scan_tail(mtd);
1350 if (retval)
1351 goto fail;
1352
1353 retval = read_factory_bbt(mtd);
1354 if (retval)
1355 goto fail;
1356
1357 retval = mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0);
1358 if (retval)
1359 goto fail;
1360
1361 doc->mtd = mtd;
1362 return 0;
1363
1364 fail:
1365 iounmap(virtadr);
1366 if (mtd) {
1367 /* re-declarations avoid compiler warning */
1368 struct nand_chip *nand = mtd->priv;
1369 struct docg4_priv *doc = nand->priv;
1370 nand_release(mtd); /* deletes partitions and mtd devices */
1371 platform_set_drvdata(pdev, NULL);
1372 free_bch(doc->bch);
1373 kfree(mtd);
1374 }
1375
1376 return retval;
1377 }
1378
cleanup_docg4(struct platform_device * pdev)1379 static int __exit cleanup_docg4(struct platform_device *pdev)
1380 {
1381 struct docg4_priv *doc = platform_get_drvdata(pdev);
1382 nand_release(doc->mtd);
1383 platform_set_drvdata(pdev, NULL);
1384 free_bch(doc->bch);
1385 kfree(doc->mtd);
1386 iounmap(doc->virtadr);
1387 return 0;
1388 }
1389
1390 static struct platform_driver docg4_driver = {
1391 .driver = {
1392 .name = "docg4",
1393 .owner = THIS_MODULE,
1394 },
1395 .suspend = docg4_suspend,
1396 .resume = docg4_resume,
1397 .remove = __exit_p(cleanup_docg4),
1398 };
1399
1400 module_platform_driver_probe(docg4_driver, probe_docg4);
1401
1402 MODULE_LICENSE("GPL");
1403 MODULE_AUTHOR("Mike Dunn");
1404 MODULE_DESCRIPTION("M-Systems DiskOnChip G4 device driver");
1405