1 /*
2 * drivers/mtd/nand/fsmc_nand.c
3 *
4 * ST Microelectronics
5 * Flexible Static Memory Controller (FSMC)
6 * Driver for NAND portions
7 *
8 * Copyright © 2010 ST Microelectronics
9 * Vipin Kumar <vipin.kumar@st.com>
10 * Ashish Priyadarshi
11 *
12 * Based on drivers/mtd/nand/nomadik_nand.c
13 *
14 * This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without any
16 * warranty of any kind, whether express or implied.
17 */
18
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/dmaengine.h>
22 #include <linux/dma-direction.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/err.h>
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/resource.h>
28 #include <linux/sched.h>
29 #include <linux/types.h>
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/nand.h>
32 #include <linux/mtd/nand_ecc.h>
33 #include <linux/platform_device.h>
34 #include <linux/of.h>
35 #include <linux/mtd/partitions.h>
36 #include <linux/io.h>
37 #include <linux/slab.h>
38 #include <linux/mtd/fsmc.h>
39 #include <linux/amba/bus.h>
40 #include <mtd/mtd-abi.h>
41
42 static struct nand_ecclayout fsmc_ecc1_128_layout = {
43 .eccbytes = 24,
44 .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
45 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
46 .oobfree = {
47 {.offset = 8, .length = 8},
48 {.offset = 24, .length = 8},
49 {.offset = 40, .length = 8},
50 {.offset = 56, .length = 8},
51 {.offset = 72, .length = 8},
52 {.offset = 88, .length = 8},
53 {.offset = 104, .length = 8},
54 {.offset = 120, .length = 8}
55 }
56 };
57
58 static struct nand_ecclayout fsmc_ecc1_64_layout = {
59 .eccbytes = 12,
60 .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52},
61 .oobfree = {
62 {.offset = 8, .length = 8},
63 {.offset = 24, .length = 8},
64 {.offset = 40, .length = 8},
65 {.offset = 56, .length = 8},
66 }
67 };
68
69 static struct nand_ecclayout fsmc_ecc1_16_layout = {
70 .eccbytes = 3,
71 .eccpos = {2, 3, 4},
72 .oobfree = {
73 {.offset = 8, .length = 8},
74 }
75 };
76
77 /*
78 * ECC4 layout for NAND of pagesize 8192 bytes & OOBsize 256 bytes. 13*16 bytes
79 * of OB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 46
80 * bytes are free for use.
81 */
82 static struct nand_ecclayout fsmc_ecc4_256_layout = {
83 .eccbytes = 208,
84 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
85 9, 10, 11, 12, 13, 14,
86 18, 19, 20, 21, 22, 23, 24,
87 25, 26, 27, 28, 29, 30,
88 34, 35, 36, 37, 38, 39, 40,
89 41, 42, 43, 44, 45, 46,
90 50, 51, 52, 53, 54, 55, 56,
91 57, 58, 59, 60, 61, 62,
92 66, 67, 68, 69, 70, 71, 72,
93 73, 74, 75, 76, 77, 78,
94 82, 83, 84, 85, 86, 87, 88,
95 89, 90, 91, 92, 93, 94,
96 98, 99, 100, 101, 102, 103, 104,
97 105, 106, 107, 108, 109, 110,
98 114, 115, 116, 117, 118, 119, 120,
99 121, 122, 123, 124, 125, 126,
100 130, 131, 132, 133, 134, 135, 136,
101 137, 138, 139, 140, 141, 142,
102 146, 147, 148, 149, 150, 151, 152,
103 153, 154, 155, 156, 157, 158,
104 162, 163, 164, 165, 166, 167, 168,
105 169, 170, 171, 172, 173, 174,
106 178, 179, 180, 181, 182, 183, 184,
107 185, 186, 187, 188, 189, 190,
108 194, 195, 196, 197, 198, 199, 200,
109 201, 202, 203, 204, 205, 206,
110 210, 211, 212, 213, 214, 215, 216,
111 217, 218, 219, 220, 221, 222,
112 226, 227, 228, 229, 230, 231, 232,
113 233, 234, 235, 236, 237, 238,
114 242, 243, 244, 245, 246, 247, 248,
115 249, 250, 251, 252, 253, 254
116 },
117 .oobfree = {
118 {.offset = 15, .length = 3},
119 {.offset = 31, .length = 3},
120 {.offset = 47, .length = 3},
121 {.offset = 63, .length = 3},
122 {.offset = 79, .length = 3},
123 {.offset = 95, .length = 3},
124 {.offset = 111, .length = 3},
125 {.offset = 127, .length = 3},
126 {.offset = 143, .length = 3},
127 {.offset = 159, .length = 3},
128 {.offset = 175, .length = 3},
129 {.offset = 191, .length = 3},
130 {.offset = 207, .length = 3},
131 {.offset = 223, .length = 3},
132 {.offset = 239, .length = 3},
133 {.offset = 255, .length = 1}
134 }
135 };
136
137 /*
138 * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 13*8 bytes
139 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118
140 * bytes are free for use.
141 */
142 static struct nand_ecclayout fsmc_ecc4_224_layout = {
143 .eccbytes = 104,
144 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
145 9, 10, 11, 12, 13, 14,
146 18, 19, 20, 21, 22, 23, 24,
147 25, 26, 27, 28, 29, 30,
148 34, 35, 36, 37, 38, 39, 40,
149 41, 42, 43, 44, 45, 46,
150 50, 51, 52, 53, 54, 55, 56,
151 57, 58, 59, 60, 61, 62,
152 66, 67, 68, 69, 70, 71, 72,
153 73, 74, 75, 76, 77, 78,
154 82, 83, 84, 85, 86, 87, 88,
155 89, 90, 91, 92, 93, 94,
156 98, 99, 100, 101, 102, 103, 104,
157 105, 106, 107, 108, 109, 110,
158 114, 115, 116, 117, 118, 119, 120,
159 121, 122, 123, 124, 125, 126
160 },
161 .oobfree = {
162 {.offset = 15, .length = 3},
163 {.offset = 31, .length = 3},
164 {.offset = 47, .length = 3},
165 {.offset = 63, .length = 3},
166 {.offset = 79, .length = 3},
167 {.offset = 95, .length = 3},
168 {.offset = 111, .length = 3},
169 {.offset = 127, .length = 97}
170 }
171 };
172
173 /*
174 * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 128 bytes. 13*8 bytes
175 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 22
176 * bytes are free for use.
177 */
178 static struct nand_ecclayout fsmc_ecc4_128_layout = {
179 .eccbytes = 104,
180 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
181 9, 10, 11, 12, 13, 14,
182 18, 19, 20, 21, 22, 23, 24,
183 25, 26, 27, 28, 29, 30,
184 34, 35, 36, 37, 38, 39, 40,
185 41, 42, 43, 44, 45, 46,
186 50, 51, 52, 53, 54, 55, 56,
187 57, 58, 59, 60, 61, 62,
188 66, 67, 68, 69, 70, 71, 72,
189 73, 74, 75, 76, 77, 78,
190 82, 83, 84, 85, 86, 87, 88,
191 89, 90, 91, 92, 93, 94,
192 98, 99, 100, 101, 102, 103, 104,
193 105, 106, 107, 108, 109, 110,
194 114, 115, 116, 117, 118, 119, 120,
195 121, 122, 123, 124, 125, 126
196 },
197 .oobfree = {
198 {.offset = 15, .length = 3},
199 {.offset = 31, .length = 3},
200 {.offset = 47, .length = 3},
201 {.offset = 63, .length = 3},
202 {.offset = 79, .length = 3},
203 {.offset = 95, .length = 3},
204 {.offset = 111, .length = 3},
205 {.offset = 127, .length = 1}
206 }
207 };
208
209 /*
210 * ECC4 layout for NAND of pagesize 2048 bytes & OOBsize 64 bytes. 13*4 bytes of
211 * OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 10
212 * bytes are free for use.
213 */
214 static struct nand_ecclayout fsmc_ecc4_64_layout = {
215 .eccbytes = 52,
216 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
217 9, 10, 11, 12, 13, 14,
218 18, 19, 20, 21, 22, 23, 24,
219 25, 26, 27, 28, 29, 30,
220 34, 35, 36, 37, 38, 39, 40,
221 41, 42, 43, 44, 45, 46,
222 50, 51, 52, 53, 54, 55, 56,
223 57, 58, 59, 60, 61, 62,
224 },
225 .oobfree = {
226 {.offset = 15, .length = 3},
227 {.offset = 31, .length = 3},
228 {.offset = 47, .length = 3},
229 {.offset = 63, .length = 1},
230 }
231 };
232
233 /*
234 * ECC4 layout for NAND of pagesize 512 bytes & OOBsize 16 bytes. 13 bytes of
235 * OOB size is reserved for ECC, Byte no. 4 & 5 reserved for bad block and One
236 * byte is free for use.
237 */
238 static struct nand_ecclayout fsmc_ecc4_16_layout = {
239 .eccbytes = 13,
240 .eccpos = { 0, 1, 2, 3, 6, 7, 8,
241 9, 10, 11, 12, 13, 14
242 },
243 .oobfree = {
244 {.offset = 15, .length = 1},
245 }
246 };
247
248 /*
249 * ECC placement definitions in oobfree type format.
250 * There are 13 bytes of ecc for every 512 byte block and it has to be read
251 * consecutively and immediately after the 512 byte data block for hardware to
252 * generate the error bit offsets in 512 byte data.
253 * Managing the ecc bytes in the following way makes it easier for software to
254 * read ecc bytes consecutive to data bytes. This way is similar to
255 * oobfree structure maintained already in generic nand driver
256 */
257 static struct fsmc_eccplace fsmc_ecc4_lp_place = {
258 .eccplace = {
259 {.offset = 2, .length = 13},
260 {.offset = 18, .length = 13},
261 {.offset = 34, .length = 13},
262 {.offset = 50, .length = 13},
263 {.offset = 66, .length = 13},
264 {.offset = 82, .length = 13},
265 {.offset = 98, .length = 13},
266 {.offset = 114, .length = 13}
267 }
268 };
269
270 static struct fsmc_eccplace fsmc_ecc4_sp_place = {
271 .eccplace = {
272 {.offset = 0, .length = 4},
273 {.offset = 6, .length = 9}
274 }
275 };
276
277 /**
278 * struct fsmc_nand_data - structure for FSMC NAND device state
279 *
280 * @pid: Part ID on the AMBA PrimeCell format
281 * @mtd: MTD info for a NAND flash.
282 * @nand: Chip related info for a NAND flash.
283 * @partitions: Partition info for a NAND Flash.
284 * @nr_partitions: Total number of partition of a NAND flash.
285 *
286 * @ecc_place: ECC placing locations in oobfree type format.
287 * @bank: Bank number for probed device.
288 * @clk: Clock structure for FSMC.
289 *
290 * @read_dma_chan: DMA channel for read access
291 * @write_dma_chan: DMA channel for write access to NAND
292 * @dma_access_complete: Completion structure
293 *
294 * @data_pa: NAND Physical port for Data.
295 * @data_va: NAND port for Data.
296 * @cmd_va: NAND port for Command.
297 * @addr_va: NAND port for Address.
298 * @regs_va: FSMC regs base address.
299 */
300 struct fsmc_nand_data {
301 u32 pid;
302 struct mtd_info mtd;
303 struct nand_chip nand;
304 struct mtd_partition *partitions;
305 unsigned int nr_partitions;
306
307 struct fsmc_eccplace *ecc_place;
308 unsigned int bank;
309 struct device *dev;
310 enum access_mode mode;
311 struct clk *clk;
312
313 /* DMA related objects */
314 struct dma_chan *read_dma_chan;
315 struct dma_chan *write_dma_chan;
316 struct completion dma_access_complete;
317
318 struct fsmc_nand_timings *dev_timings;
319
320 dma_addr_t data_pa;
321 void __iomem *data_va;
322 void __iomem *cmd_va;
323 void __iomem *addr_va;
324 void __iomem *regs_va;
325
326 void (*select_chip)(uint32_t bank, uint32_t busw);
327 };
328
329 /* Assert CS signal based on chipnr */
fsmc_select_chip(struct mtd_info * mtd,int chipnr)330 static void fsmc_select_chip(struct mtd_info *mtd, int chipnr)
331 {
332 struct nand_chip *chip = mtd->priv;
333 struct fsmc_nand_data *host;
334
335 host = container_of(mtd, struct fsmc_nand_data, mtd);
336
337 switch (chipnr) {
338 case -1:
339 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
340 break;
341 case 0:
342 case 1:
343 case 2:
344 case 3:
345 if (host->select_chip)
346 host->select_chip(chipnr,
347 chip->options & NAND_BUSWIDTH_16);
348 break;
349
350 default:
351 BUG();
352 }
353 }
354
355 /*
356 * fsmc_cmd_ctrl - For facilitaing Hardware access
357 * This routine allows hardware specific access to control-lines(ALE,CLE)
358 */
fsmc_cmd_ctrl(struct mtd_info * mtd,int cmd,unsigned int ctrl)359 static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
360 {
361 struct nand_chip *this = mtd->priv;
362 struct fsmc_nand_data *host = container_of(mtd,
363 struct fsmc_nand_data, mtd);
364 void __iomem *regs = host->regs_va;
365 unsigned int bank = host->bank;
366
367 if (ctrl & NAND_CTRL_CHANGE) {
368 u32 pc;
369
370 if (ctrl & NAND_CLE) {
371 this->IO_ADDR_R = host->cmd_va;
372 this->IO_ADDR_W = host->cmd_va;
373 } else if (ctrl & NAND_ALE) {
374 this->IO_ADDR_R = host->addr_va;
375 this->IO_ADDR_W = host->addr_va;
376 } else {
377 this->IO_ADDR_R = host->data_va;
378 this->IO_ADDR_W = host->data_va;
379 }
380
381 pc = readl(FSMC_NAND_REG(regs, bank, PC));
382 if (ctrl & NAND_NCE)
383 pc |= FSMC_ENABLE;
384 else
385 pc &= ~FSMC_ENABLE;
386 writel_relaxed(pc, FSMC_NAND_REG(regs, bank, PC));
387 }
388
389 mb();
390
391 if (cmd != NAND_CMD_NONE)
392 writeb_relaxed(cmd, this->IO_ADDR_W);
393 }
394
395 /*
396 * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
397 *
398 * This routine initializes timing parameters related to NAND memory access in
399 * FSMC registers
400 */
fsmc_nand_setup(void __iomem * regs,uint32_t bank,uint32_t busw,struct fsmc_nand_timings * timings)401 static void fsmc_nand_setup(void __iomem *regs, uint32_t bank,
402 uint32_t busw, struct fsmc_nand_timings *timings)
403 {
404 uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
405 uint32_t tclr, tar, thiz, thold, twait, tset;
406 struct fsmc_nand_timings *tims;
407 struct fsmc_nand_timings default_timings = {
408 .tclr = FSMC_TCLR_1,
409 .tar = FSMC_TAR_1,
410 .thiz = FSMC_THIZ_1,
411 .thold = FSMC_THOLD_4,
412 .twait = FSMC_TWAIT_6,
413 .tset = FSMC_TSET_0,
414 };
415
416 if (timings)
417 tims = timings;
418 else
419 tims = &default_timings;
420
421 tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
422 tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
423 thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
424 thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
425 twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
426 tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
427
428 if (busw)
429 writel_relaxed(value | FSMC_DEVWID_16,
430 FSMC_NAND_REG(regs, bank, PC));
431 else
432 writel_relaxed(value | FSMC_DEVWID_8,
433 FSMC_NAND_REG(regs, bank, PC));
434
435 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
436 FSMC_NAND_REG(regs, bank, PC));
437 writel_relaxed(thiz | thold | twait | tset,
438 FSMC_NAND_REG(regs, bank, COMM));
439 writel_relaxed(thiz | thold | twait | tset,
440 FSMC_NAND_REG(regs, bank, ATTRIB));
441 }
442
443 /*
444 * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
445 */
fsmc_enable_hwecc(struct mtd_info * mtd,int mode)446 static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
447 {
448 struct fsmc_nand_data *host = container_of(mtd,
449 struct fsmc_nand_data, mtd);
450 void __iomem *regs = host->regs_va;
451 uint32_t bank = host->bank;
452
453 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
454 FSMC_NAND_REG(regs, bank, PC));
455 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
456 FSMC_NAND_REG(regs, bank, PC));
457 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
458 FSMC_NAND_REG(regs, bank, PC));
459 }
460
461 /*
462 * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
463 * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
464 * max of 8-bits)
465 */
fsmc_read_hwecc_ecc4(struct mtd_info * mtd,const uint8_t * data,uint8_t * ecc)466 static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
467 uint8_t *ecc)
468 {
469 struct fsmc_nand_data *host = container_of(mtd,
470 struct fsmc_nand_data, mtd);
471 void __iomem *regs = host->regs_va;
472 uint32_t bank = host->bank;
473 uint32_t ecc_tmp;
474 unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
475
476 do {
477 if (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
478 break;
479 else
480 cond_resched();
481 } while (!time_after_eq(jiffies, deadline));
482
483 if (time_after_eq(jiffies, deadline)) {
484 dev_err(host->dev, "calculate ecc timed out\n");
485 return -ETIMEDOUT;
486 }
487
488 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
489 ecc[0] = (uint8_t) (ecc_tmp >> 0);
490 ecc[1] = (uint8_t) (ecc_tmp >> 8);
491 ecc[2] = (uint8_t) (ecc_tmp >> 16);
492 ecc[3] = (uint8_t) (ecc_tmp >> 24);
493
494 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
495 ecc[4] = (uint8_t) (ecc_tmp >> 0);
496 ecc[5] = (uint8_t) (ecc_tmp >> 8);
497 ecc[6] = (uint8_t) (ecc_tmp >> 16);
498 ecc[7] = (uint8_t) (ecc_tmp >> 24);
499
500 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
501 ecc[8] = (uint8_t) (ecc_tmp >> 0);
502 ecc[9] = (uint8_t) (ecc_tmp >> 8);
503 ecc[10] = (uint8_t) (ecc_tmp >> 16);
504 ecc[11] = (uint8_t) (ecc_tmp >> 24);
505
506 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
507 ecc[12] = (uint8_t) (ecc_tmp >> 16);
508
509 return 0;
510 }
511
512 /*
513 * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
514 * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
515 * max of 1-bit)
516 */
fsmc_read_hwecc_ecc1(struct mtd_info * mtd,const uint8_t * data,uint8_t * ecc)517 static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
518 uint8_t *ecc)
519 {
520 struct fsmc_nand_data *host = container_of(mtd,
521 struct fsmc_nand_data, mtd);
522 void __iomem *regs = host->regs_va;
523 uint32_t bank = host->bank;
524 uint32_t ecc_tmp;
525
526 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
527 ecc[0] = (uint8_t) (ecc_tmp >> 0);
528 ecc[1] = (uint8_t) (ecc_tmp >> 8);
529 ecc[2] = (uint8_t) (ecc_tmp >> 16);
530
531 return 0;
532 }
533
534 /* Count the number of 0's in buff upto a max of max_bits */
count_written_bits(uint8_t * buff,int size,int max_bits)535 static int count_written_bits(uint8_t *buff, int size, int max_bits)
536 {
537 int k, written_bits = 0;
538
539 for (k = 0; k < size; k++) {
540 written_bits += hweight8(~buff[k]);
541 if (written_bits > max_bits)
542 break;
543 }
544
545 return written_bits;
546 }
547
dma_complete(void * param)548 static void dma_complete(void *param)
549 {
550 struct fsmc_nand_data *host = param;
551
552 complete(&host->dma_access_complete);
553 }
554
dma_xfer(struct fsmc_nand_data * host,void * buffer,int len,enum dma_data_direction direction)555 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
556 enum dma_data_direction direction)
557 {
558 struct dma_chan *chan;
559 struct dma_device *dma_dev;
560 struct dma_async_tx_descriptor *tx;
561 dma_addr_t dma_dst, dma_src, dma_addr;
562 dma_cookie_t cookie;
563 unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
564 int ret;
565
566 if (direction == DMA_TO_DEVICE)
567 chan = host->write_dma_chan;
568 else if (direction == DMA_FROM_DEVICE)
569 chan = host->read_dma_chan;
570 else
571 return -EINVAL;
572
573 dma_dev = chan->device;
574 dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
575
576 flags |= DMA_COMPL_SKIP_SRC_UNMAP | DMA_COMPL_SKIP_DEST_UNMAP;
577
578 if (direction == DMA_TO_DEVICE) {
579 dma_src = dma_addr;
580 dma_dst = host->data_pa;
581 } else {
582 dma_src = host->data_pa;
583 dma_dst = dma_addr;
584 }
585
586 tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
587 len, flags);
588 if (!tx) {
589 dev_err(host->dev, "device_prep_dma_memcpy error\n");
590 ret = -EIO;
591 goto unmap_dma;
592 }
593
594 tx->callback = dma_complete;
595 tx->callback_param = host;
596 cookie = tx->tx_submit(tx);
597
598 ret = dma_submit_error(cookie);
599 if (ret) {
600 dev_err(host->dev, "dma_submit_error %d\n", cookie);
601 goto unmap_dma;
602 }
603
604 dma_async_issue_pending(chan);
605
606 ret =
607 wait_for_completion_timeout(&host->dma_access_complete,
608 msecs_to_jiffies(3000));
609 if (ret <= 0) {
610 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
611 dev_err(host->dev, "wait_for_completion_timeout\n");
612 if (!ret)
613 ret = -ETIMEDOUT;
614 goto unmap_dma;
615 }
616
617 ret = 0;
618
619 unmap_dma:
620 dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
621
622 return ret;
623 }
624
625 /*
626 * fsmc_write_buf - write buffer to chip
627 * @mtd: MTD device structure
628 * @buf: data buffer
629 * @len: number of bytes to write
630 */
fsmc_write_buf(struct mtd_info * mtd,const uint8_t * buf,int len)631 static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
632 {
633 int i;
634 struct nand_chip *chip = mtd->priv;
635
636 if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
637 IS_ALIGNED(len, sizeof(uint32_t))) {
638 uint32_t *p = (uint32_t *)buf;
639 len = len >> 2;
640 for (i = 0; i < len; i++)
641 writel_relaxed(p[i], chip->IO_ADDR_W);
642 } else {
643 for (i = 0; i < len; i++)
644 writeb_relaxed(buf[i], chip->IO_ADDR_W);
645 }
646 }
647
648 /*
649 * fsmc_read_buf - read chip data into buffer
650 * @mtd: MTD device structure
651 * @buf: buffer to store date
652 * @len: number of bytes to read
653 */
fsmc_read_buf(struct mtd_info * mtd,uint8_t * buf,int len)654 static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
655 {
656 int i;
657 struct nand_chip *chip = mtd->priv;
658
659 if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
660 IS_ALIGNED(len, sizeof(uint32_t))) {
661 uint32_t *p = (uint32_t *)buf;
662 len = len >> 2;
663 for (i = 0; i < len; i++)
664 p[i] = readl_relaxed(chip->IO_ADDR_R);
665 } else {
666 for (i = 0; i < len; i++)
667 buf[i] = readb_relaxed(chip->IO_ADDR_R);
668 }
669 }
670
671 /*
672 * fsmc_read_buf_dma - read chip data into buffer
673 * @mtd: MTD device structure
674 * @buf: buffer to store date
675 * @len: number of bytes to read
676 */
fsmc_read_buf_dma(struct mtd_info * mtd,uint8_t * buf,int len)677 static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
678 {
679 struct fsmc_nand_data *host;
680
681 host = container_of(mtd, struct fsmc_nand_data, mtd);
682 dma_xfer(host, buf, len, DMA_FROM_DEVICE);
683 }
684
685 /*
686 * fsmc_write_buf_dma - write buffer to chip
687 * @mtd: MTD device structure
688 * @buf: data buffer
689 * @len: number of bytes to write
690 */
fsmc_write_buf_dma(struct mtd_info * mtd,const uint8_t * buf,int len)691 static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
692 int len)
693 {
694 struct fsmc_nand_data *host;
695
696 host = container_of(mtd, struct fsmc_nand_data, mtd);
697 dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
698 }
699
700 /*
701 * fsmc_read_page_hwecc
702 * @mtd: mtd info structure
703 * @chip: nand chip info structure
704 * @buf: buffer to store read data
705 * @oob_required: caller expects OOB data read to chip->oob_poi
706 * @page: page number to read
707 *
708 * This routine is needed for fsmc version 8 as reading from NAND chip has to be
709 * performed in a strict sequence as follows:
710 * data(512 byte) -> ecc(13 byte)
711 * After this read, fsmc hardware generates and reports error data bits(up to a
712 * max of 8 bits)
713 */
fsmc_read_page_hwecc(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)714 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
715 uint8_t *buf, int oob_required, int page)
716 {
717 struct fsmc_nand_data *host = container_of(mtd,
718 struct fsmc_nand_data, mtd);
719 struct fsmc_eccplace *ecc_place = host->ecc_place;
720 int i, j, s, stat, eccsize = chip->ecc.size;
721 int eccbytes = chip->ecc.bytes;
722 int eccsteps = chip->ecc.steps;
723 uint8_t *p = buf;
724 uint8_t *ecc_calc = chip->buffers->ecccalc;
725 uint8_t *ecc_code = chip->buffers->ecccode;
726 int off, len, group = 0;
727 /*
728 * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
729 * end up reading 14 bytes (7 words) from oob. The local array is
730 * to maintain word alignment
731 */
732 uint16_t ecc_oob[7];
733 uint8_t *oob = (uint8_t *)&ecc_oob[0];
734 unsigned int max_bitflips = 0;
735
736 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
737 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
738 chip->ecc.hwctl(mtd, NAND_ECC_READ);
739 chip->read_buf(mtd, p, eccsize);
740
741 for (j = 0; j < eccbytes;) {
742 off = ecc_place->eccplace[group].offset;
743 len = ecc_place->eccplace[group].length;
744 group++;
745
746 /*
747 * length is intentionally kept a higher multiple of 2
748 * to read at least 13 bytes even in case of 16 bit NAND
749 * devices
750 */
751 if (chip->options & NAND_BUSWIDTH_16)
752 len = roundup(len, 2);
753
754 chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
755 chip->read_buf(mtd, oob + j, len);
756 j += len;
757 }
758
759 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
760 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
761
762 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
763 if (stat < 0) {
764 mtd->ecc_stats.failed++;
765 } else {
766 mtd->ecc_stats.corrected += stat;
767 max_bitflips = max_t(unsigned int, max_bitflips, stat);
768 }
769 }
770
771 return max_bitflips;
772 }
773
774 /*
775 * fsmc_bch8_correct_data
776 * @mtd: mtd info structure
777 * @dat: buffer of read data
778 * @read_ecc: ecc read from device spare area
779 * @calc_ecc: ecc calculated from read data
780 *
781 * calc_ecc is a 104 bit information containing maximum of 8 error
782 * offset informations of 13 bits each in 512 bytes of read data.
783 */
fsmc_bch8_correct_data(struct mtd_info * mtd,uint8_t * dat,uint8_t * read_ecc,uint8_t * calc_ecc)784 static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
785 uint8_t *read_ecc, uint8_t *calc_ecc)
786 {
787 struct fsmc_nand_data *host = container_of(mtd,
788 struct fsmc_nand_data, mtd);
789 struct nand_chip *chip = mtd->priv;
790 void __iomem *regs = host->regs_va;
791 unsigned int bank = host->bank;
792 uint32_t err_idx[8];
793 uint32_t num_err, i;
794 uint32_t ecc1, ecc2, ecc3, ecc4;
795
796 num_err = (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
797
798 /* no bit flipping */
799 if (likely(num_err == 0))
800 return 0;
801
802 /* too many errors */
803 if (unlikely(num_err > 8)) {
804 /*
805 * This is a temporary erase check. A newly erased page read
806 * would result in an ecc error because the oob data is also
807 * erased to FF and the calculated ecc for an FF data is not
808 * FF..FF.
809 * This is a workaround to skip performing correction in case
810 * data is FF..FF
811 *
812 * Logic:
813 * For every page, each bit written as 0 is counted until these
814 * number of bits are greater than 8 (the maximum correction
815 * capability of FSMC for each 512 + 13 bytes)
816 */
817
818 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
819 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
820
821 if ((bits_ecc + bits_data) <= 8) {
822 if (bits_data)
823 memset(dat, 0xff, chip->ecc.size);
824 return bits_data;
825 }
826
827 return -EBADMSG;
828 }
829
830 /*
831 * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
832 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
833 *
834 * calc_ecc is a 104 bit information containing maximum of 8 error
835 * offset informations of 13 bits each. calc_ecc is copied into a
836 * uint64_t array and error offset indexes are populated in err_idx
837 * array
838 */
839 ecc1 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
840 ecc2 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
841 ecc3 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
842 ecc4 = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
843
844 err_idx[0] = (ecc1 >> 0) & 0x1FFF;
845 err_idx[1] = (ecc1 >> 13) & 0x1FFF;
846 err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
847 err_idx[3] = (ecc2 >> 7) & 0x1FFF;
848 err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
849 err_idx[5] = (ecc3 >> 1) & 0x1FFF;
850 err_idx[6] = (ecc3 >> 14) & 0x1FFF;
851 err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
852
853 i = 0;
854 while (num_err--) {
855 change_bit(0, (unsigned long *)&err_idx[i]);
856 change_bit(1, (unsigned long *)&err_idx[i]);
857
858 if (err_idx[i] < chip->ecc.size * 8) {
859 change_bit(err_idx[i], (unsigned long *)dat);
860 i++;
861 }
862 }
863 return i;
864 }
865
filter(struct dma_chan * chan,void * slave)866 static bool filter(struct dma_chan *chan, void *slave)
867 {
868 chan->private = slave;
869 return true;
870 }
871
872 #ifdef CONFIG_OF
fsmc_nand_probe_config_dt(struct platform_device * pdev,struct device_node * np)873 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
874 struct device_node *np)
875 {
876 struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
877 u32 val;
878
879 /* Set default NAND width to 8 bits */
880 pdata->width = 8;
881 if (!of_property_read_u32(np, "bank-width", &val)) {
882 if (val == 2) {
883 pdata->width = 16;
884 } else if (val != 1) {
885 dev_err(&pdev->dev, "invalid bank-width %u\n", val);
886 return -EINVAL;
887 }
888 }
889 if (of_get_property(np, "nand-skip-bbtscan", NULL))
890 pdata->options = NAND_SKIP_BBTSCAN;
891
892 return 0;
893 }
894 #else
fsmc_nand_probe_config_dt(struct platform_device * pdev,struct device_node * np)895 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
896 struct device_node *np)
897 {
898 return -ENOSYS;
899 }
900 #endif
901
902 /*
903 * fsmc_nand_probe - Probe function
904 * @pdev: platform device structure
905 */
fsmc_nand_probe(struct platform_device * pdev)906 static int __init fsmc_nand_probe(struct platform_device *pdev)
907 {
908 struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
909 struct device_node __maybe_unused *np = pdev->dev.of_node;
910 struct mtd_part_parser_data ppdata = {};
911 struct fsmc_nand_data *host;
912 struct mtd_info *mtd;
913 struct nand_chip *nand;
914 struct resource *res;
915 dma_cap_mask_t mask;
916 int ret = 0;
917 u32 pid;
918 int i;
919
920 if (np) {
921 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
922 pdev->dev.platform_data = pdata;
923 ret = fsmc_nand_probe_config_dt(pdev, np);
924 if (ret) {
925 dev_err(&pdev->dev, "no platform data\n");
926 return -ENODEV;
927 }
928 }
929
930 if (!pdata) {
931 dev_err(&pdev->dev, "platform data is NULL\n");
932 return -EINVAL;
933 }
934
935 /* Allocate memory for the device structure (and zero it) */
936 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
937 if (!host) {
938 dev_err(&pdev->dev, "failed to allocate device structure\n");
939 return -ENOMEM;
940 }
941
942 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
943 if (!res)
944 return -EINVAL;
945
946 host->data_va = devm_ioremap_resource(&pdev->dev, res);
947 if (IS_ERR(host->data_va))
948 return PTR_ERR(host->data_va);
949
950 host->data_pa = (dma_addr_t)res->start;
951
952 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
953 if (!res)
954 return -EINVAL;
955
956 host->addr_va = devm_ioremap_resource(&pdev->dev, res);
957 if (IS_ERR(host->addr_va))
958 return PTR_ERR(host->addr_va);
959
960 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
961 if (!res)
962 return -EINVAL;
963
964 host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
965 if (IS_ERR(host->cmd_va))
966 return PTR_ERR(host->cmd_va);
967
968 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
969 if (!res)
970 return -EINVAL;
971
972 host->regs_va = devm_ioremap_resource(&pdev->dev, res);
973 if (IS_ERR(host->regs_va))
974 return PTR_ERR(host->regs_va);
975
976 host->clk = clk_get(&pdev->dev, NULL);
977 if (IS_ERR(host->clk)) {
978 dev_err(&pdev->dev, "failed to fetch block clock\n");
979 return PTR_ERR(host->clk);
980 }
981
982 ret = clk_prepare_enable(host->clk);
983 if (ret)
984 goto err_clk_prepare_enable;
985
986 /*
987 * This device ID is actually a common AMBA ID as used on the
988 * AMBA PrimeCell bus. However it is not a PrimeCell.
989 */
990 for (pid = 0, i = 0; i < 4; i++)
991 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
992 host->pid = pid;
993 dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
994 "revision %02x, config %02x\n",
995 AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
996 AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
997
998 host->bank = pdata->bank;
999 host->select_chip = pdata->select_bank;
1000 host->partitions = pdata->partitions;
1001 host->nr_partitions = pdata->nr_partitions;
1002 host->dev = &pdev->dev;
1003 host->dev_timings = pdata->nand_timings;
1004 host->mode = pdata->mode;
1005
1006 if (host->mode == USE_DMA_ACCESS)
1007 init_completion(&host->dma_access_complete);
1008
1009 /* Link all private pointers */
1010 mtd = &host->mtd;
1011 nand = &host->nand;
1012 mtd->priv = nand;
1013 nand->priv = host;
1014
1015 host->mtd.owner = THIS_MODULE;
1016 nand->IO_ADDR_R = host->data_va;
1017 nand->IO_ADDR_W = host->data_va;
1018 nand->cmd_ctrl = fsmc_cmd_ctrl;
1019 nand->chip_delay = 30;
1020
1021 nand->ecc.mode = NAND_ECC_HW;
1022 nand->ecc.hwctl = fsmc_enable_hwecc;
1023 nand->ecc.size = 512;
1024 nand->options = pdata->options;
1025 nand->select_chip = fsmc_select_chip;
1026 nand->badblockbits = 7;
1027
1028 if (pdata->width == FSMC_NAND_BW16)
1029 nand->options |= NAND_BUSWIDTH_16;
1030
1031 switch (host->mode) {
1032 case USE_DMA_ACCESS:
1033 dma_cap_zero(mask);
1034 dma_cap_set(DMA_MEMCPY, mask);
1035 host->read_dma_chan = dma_request_channel(mask, filter,
1036 pdata->read_dma_priv);
1037 if (!host->read_dma_chan) {
1038 dev_err(&pdev->dev, "Unable to get read dma channel\n");
1039 goto err_req_read_chnl;
1040 }
1041 host->write_dma_chan = dma_request_channel(mask, filter,
1042 pdata->write_dma_priv);
1043 if (!host->write_dma_chan) {
1044 dev_err(&pdev->dev, "Unable to get write dma channel\n");
1045 goto err_req_write_chnl;
1046 }
1047 nand->read_buf = fsmc_read_buf_dma;
1048 nand->write_buf = fsmc_write_buf_dma;
1049 break;
1050
1051 default:
1052 case USE_WORD_ACCESS:
1053 nand->read_buf = fsmc_read_buf;
1054 nand->write_buf = fsmc_write_buf;
1055 break;
1056 }
1057
1058 fsmc_nand_setup(host->regs_va, host->bank,
1059 nand->options & NAND_BUSWIDTH_16,
1060 host->dev_timings);
1061
1062 if (AMBA_REV_BITS(host->pid) >= 8) {
1063 nand->ecc.read_page = fsmc_read_page_hwecc;
1064 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
1065 nand->ecc.correct = fsmc_bch8_correct_data;
1066 nand->ecc.bytes = 13;
1067 nand->ecc.strength = 8;
1068 } else {
1069 nand->ecc.calculate = fsmc_read_hwecc_ecc1;
1070 nand->ecc.correct = nand_correct_data;
1071 nand->ecc.bytes = 3;
1072 nand->ecc.strength = 1;
1073 }
1074
1075 /*
1076 * Scan to find existence of the device
1077 */
1078 if (nand_scan_ident(&host->mtd, 1, NULL)) {
1079 ret = -ENXIO;
1080 dev_err(&pdev->dev, "No NAND Device found!\n");
1081 goto err_scan_ident;
1082 }
1083
1084 if (AMBA_REV_BITS(host->pid) >= 8) {
1085 switch (host->mtd.oobsize) {
1086 case 16:
1087 nand->ecc.layout = &fsmc_ecc4_16_layout;
1088 host->ecc_place = &fsmc_ecc4_sp_place;
1089 break;
1090 case 64:
1091 nand->ecc.layout = &fsmc_ecc4_64_layout;
1092 host->ecc_place = &fsmc_ecc4_lp_place;
1093 break;
1094 case 128:
1095 nand->ecc.layout = &fsmc_ecc4_128_layout;
1096 host->ecc_place = &fsmc_ecc4_lp_place;
1097 break;
1098 case 224:
1099 nand->ecc.layout = &fsmc_ecc4_224_layout;
1100 host->ecc_place = &fsmc_ecc4_lp_place;
1101 break;
1102 case 256:
1103 nand->ecc.layout = &fsmc_ecc4_256_layout;
1104 host->ecc_place = &fsmc_ecc4_lp_place;
1105 break;
1106 default:
1107 printk(KERN_WARNING "No oob scheme defined for "
1108 "oobsize %d\n", mtd->oobsize);
1109 BUG();
1110 }
1111 } else {
1112 switch (host->mtd.oobsize) {
1113 case 16:
1114 nand->ecc.layout = &fsmc_ecc1_16_layout;
1115 break;
1116 case 64:
1117 nand->ecc.layout = &fsmc_ecc1_64_layout;
1118 break;
1119 case 128:
1120 nand->ecc.layout = &fsmc_ecc1_128_layout;
1121 break;
1122 default:
1123 printk(KERN_WARNING "No oob scheme defined for "
1124 "oobsize %d\n", mtd->oobsize);
1125 BUG();
1126 }
1127 }
1128
1129 /* Second stage of scan to fill MTD data-structures */
1130 if (nand_scan_tail(&host->mtd)) {
1131 ret = -ENXIO;
1132 goto err_probe;
1133 }
1134
1135 /*
1136 * The partition information can is accessed by (in the same precedence)
1137 *
1138 * command line through Bootloader,
1139 * platform data,
1140 * default partition information present in driver.
1141 */
1142 /*
1143 * Check for partition info passed
1144 */
1145 host->mtd.name = "nand";
1146 ppdata.of_node = np;
1147 ret = mtd_device_parse_register(&host->mtd, NULL, &ppdata,
1148 host->partitions, host->nr_partitions);
1149 if (ret)
1150 goto err_probe;
1151
1152 platform_set_drvdata(pdev, host);
1153 dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1154 return 0;
1155
1156 err_probe:
1157 err_scan_ident:
1158 if (host->mode == USE_DMA_ACCESS)
1159 dma_release_channel(host->write_dma_chan);
1160 err_req_write_chnl:
1161 if (host->mode == USE_DMA_ACCESS)
1162 dma_release_channel(host->read_dma_chan);
1163 err_req_read_chnl:
1164 clk_disable_unprepare(host->clk);
1165 err_clk_prepare_enable:
1166 clk_put(host->clk);
1167 return ret;
1168 }
1169
1170 /*
1171 * Clean up routine
1172 */
fsmc_nand_remove(struct platform_device * pdev)1173 static int fsmc_nand_remove(struct platform_device *pdev)
1174 {
1175 struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1176
1177 platform_set_drvdata(pdev, NULL);
1178
1179 if (host) {
1180 nand_release(&host->mtd);
1181
1182 if (host->mode == USE_DMA_ACCESS) {
1183 dma_release_channel(host->write_dma_chan);
1184 dma_release_channel(host->read_dma_chan);
1185 }
1186 clk_disable_unprepare(host->clk);
1187 clk_put(host->clk);
1188 }
1189
1190 return 0;
1191 }
1192
1193 #ifdef CONFIG_PM
fsmc_nand_suspend(struct device * dev)1194 static int fsmc_nand_suspend(struct device *dev)
1195 {
1196 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1197 if (host)
1198 clk_disable_unprepare(host->clk);
1199 return 0;
1200 }
1201
fsmc_nand_resume(struct device * dev)1202 static int fsmc_nand_resume(struct device *dev)
1203 {
1204 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1205 if (host) {
1206 clk_prepare_enable(host->clk);
1207 fsmc_nand_setup(host->regs_va, host->bank,
1208 host->nand.options & NAND_BUSWIDTH_16,
1209 host->dev_timings);
1210 }
1211 return 0;
1212 }
1213
1214 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1215 #endif
1216
1217 #ifdef CONFIG_OF
1218 static const struct of_device_id fsmc_nand_id_table[] = {
1219 { .compatible = "st,spear600-fsmc-nand" },
1220 { .compatible = "stericsson,fsmc-nand" },
1221 {}
1222 };
1223 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1224 #endif
1225
1226 static struct platform_driver fsmc_nand_driver = {
1227 .remove = fsmc_nand_remove,
1228 .driver = {
1229 .owner = THIS_MODULE,
1230 .name = "fsmc-nand",
1231 .of_match_table = of_match_ptr(fsmc_nand_id_table),
1232 #ifdef CONFIG_PM
1233 .pm = &fsmc_nand_pm_ops,
1234 #endif
1235 },
1236 };
1237
1238 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
1239
1240 MODULE_LICENSE("GPL");
1241 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1242 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");
1243