1 /*
2 * drivers/mtd/nand/gpio.c
3 *
4 * Updated, and converted to generic GPIO based driver by Russell King.
5 *
6 * Written by Ben Dooks <ben@simtec.co.uk>
7 * Based on 2.4 version by Mark Whittaker
8 *
9 * © 2004 Simtec Electronics
10 *
11 * Device driver for NAND connected via GPIO
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 *
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/slab.h>
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/gpio.h>
25 #include <linux/io.h>
26 #include <linux/mtd/mtd.h>
27 #include <linux/mtd/nand.h>
28 #include <linux/mtd/partitions.h>
29 #include <linux/mtd/nand-gpio.h>
30 #include <linux/of.h>
31 #include <linux/of_address.h>
32 #include <linux/of_gpio.h>
33
34 struct gpiomtd {
35 void __iomem *io_sync;
36 struct mtd_info mtd_info;
37 struct nand_chip nand_chip;
38 struct gpio_nand_platdata plat;
39 };
40
41 #define gpio_nand_getpriv(x) container_of(x, struct gpiomtd, mtd_info)
42
43
44 #ifdef CONFIG_ARM
45 /* gpio_nand_dosync()
46 *
47 * Make sure the GPIO state changes occur in-order with writes to NAND
48 * memory region.
49 * Needed on PXA due to bus-reordering within the SoC itself (see section on
50 * I/O ordering in PXA manual (section 2.3, p35)
51 */
gpio_nand_dosync(struct gpiomtd * gpiomtd)52 static void gpio_nand_dosync(struct gpiomtd *gpiomtd)
53 {
54 unsigned long tmp;
55
56 if (gpiomtd->io_sync) {
57 /*
58 * Linux memory barriers don't cater for what's required here.
59 * What's required is what's here - a read from a separate
60 * region with a dependency on that read.
61 */
62 tmp = readl(gpiomtd->io_sync);
63 asm volatile("mov %1, %0\n" : "=r" (tmp) : "r" (tmp));
64 }
65 }
66 #else
gpio_nand_dosync(struct gpiomtd * gpiomtd)67 static inline void gpio_nand_dosync(struct gpiomtd *gpiomtd) {}
68 #endif
69
gpio_nand_cmd_ctrl(struct mtd_info * mtd,int cmd,unsigned int ctrl)70 static void gpio_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
71 {
72 struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd);
73
74 gpio_nand_dosync(gpiomtd);
75
76 if (ctrl & NAND_CTRL_CHANGE) {
77 gpio_set_value(gpiomtd->plat.gpio_nce, !(ctrl & NAND_NCE));
78 gpio_set_value(gpiomtd->plat.gpio_cle, !!(ctrl & NAND_CLE));
79 gpio_set_value(gpiomtd->plat.gpio_ale, !!(ctrl & NAND_ALE));
80 gpio_nand_dosync(gpiomtd);
81 }
82 if (cmd == NAND_CMD_NONE)
83 return;
84
85 writeb(cmd, gpiomtd->nand_chip.IO_ADDR_W);
86 gpio_nand_dosync(gpiomtd);
87 }
88
gpio_nand_writebuf(struct mtd_info * mtd,const u_char * buf,int len)89 static void gpio_nand_writebuf(struct mtd_info *mtd, const u_char *buf, int len)
90 {
91 struct nand_chip *this = mtd->priv;
92
93 iowrite8_rep(this->IO_ADDR_W, buf, len);
94 }
95
gpio_nand_readbuf(struct mtd_info * mtd,u_char * buf,int len)96 static void gpio_nand_readbuf(struct mtd_info *mtd, u_char *buf, int len)
97 {
98 struct nand_chip *this = mtd->priv;
99
100 ioread8_rep(this->IO_ADDR_R, buf, len);
101 }
102
gpio_nand_writebuf16(struct mtd_info * mtd,const u_char * buf,int len)103 static void gpio_nand_writebuf16(struct mtd_info *mtd, const u_char *buf,
104 int len)
105 {
106 struct nand_chip *this = mtd->priv;
107
108 if (IS_ALIGNED((unsigned long)buf, 2)) {
109 iowrite16_rep(this->IO_ADDR_W, buf, len>>1);
110 } else {
111 int i;
112 unsigned short *ptr = (unsigned short *)buf;
113
114 for (i = 0; i < len; i += 2, ptr++)
115 writew(*ptr, this->IO_ADDR_W);
116 }
117 }
118
gpio_nand_readbuf16(struct mtd_info * mtd,u_char * buf,int len)119 static void gpio_nand_readbuf16(struct mtd_info *mtd, u_char *buf, int len)
120 {
121 struct nand_chip *this = mtd->priv;
122
123 if (IS_ALIGNED((unsigned long)buf, 2)) {
124 ioread16_rep(this->IO_ADDR_R, buf, len>>1);
125 } else {
126 int i;
127 unsigned short *ptr = (unsigned short *)buf;
128
129 for (i = 0; i < len; i += 2, ptr++)
130 *ptr = readw(this->IO_ADDR_R);
131 }
132 }
133
gpio_nand_devready(struct mtd_info * mtd)134 static int gpio_nand_devready(struct mtd_info *mtd)
135 {
136 struct gpiomtd *gpiomtd = gpio_nand_getpriv(mtd);
137
138 if (gpio_is_valid(gpiomtd->plat.gpio_rdy))
139 return gpio_get_value(gpiomtd->plat.gpio_rdy);
140
141 return 1;
142 }
143
144 #ifdef CONFIG_OF
145 static const struct of_device_id gpio_nand_id_table[] = {
146 { .compatible = "gpio-control-nand" },
147 {}
148 };
149 MODULE_DEVICE_TABLE(of, gpio_nand_id_table);
150
gpio_nand_get_config_of(const struct device * dev,struct gpio_nand_platdata * plat)151 static int gpio_nand_get_config_of(const struct device *dev,
152 struct gpio_nand_platdata *plat)
153 {
154 u32 val;
155
156 if (!of_property_read_u32(dev->of_node, "bank-width", &val)) {
157 if (val == 2) {
158 plat->options |= NAND_BUSWIDTH_16;
159 } else if (val != 1) {
160 dev_err(dev, "invalid bank-width %u\n", val);
161 return -EINVAL;
162 }
163 }
164
165 plat->gpio_rdy = of_get_gpio(dev->of_node, 0);
166 plat->gpio_nce = of_get_gpio(dev->of_node, 1);
167 plat->gpio_ale = of_get_gpio(dev->of_node, 2);
168 plat->gpio_cle = of_get_gpio(dev->of_node, 3);
169 plat->gpio_nwp = of_get_gpio(dev->of_node, 4);
170
171 if (!of_property_read_u32(dev->of_node, "chip-delay", &val))
172 plat->chip_delay = val;
173
174 return 0;
175 }
176
gpio_nand_get_io_sync_of(struct platform_device * pdev)177 static struct resource *gpio_nand_get_io_sync_of(struct platform_device *pdev)
178 {
179 struct resource *r = devm_kzalloc(&pdev->dev, sizeof(*r), GFP_KERNEL);
180 u64 addr;
181
182 if (!r || of_property_read_u64(pdev->dev.of_node,
183 "gpio-control-nand,io-sync-reg", &addr))
184 return NULL;
185
186 r->start = addr;
187 r->end = r->start + 0x3;
188 r->flags = IORESOURCE_MEM;
189
190 return r;
191 }
192 #else /* CONFIG_OF */
gpio_nand_get_config_of(const struct device * dev,struct gpio_nand_platdata * plat)193 static inline int gpio_nand_get_config_of(const struct device *dev,
194 struct gpio_nand_platdata *plat)
195 {
196 return -ENOSYS;
197 }
198
199 static inline struct resource *
gpio_nand_get_io_sync_of(struct platform_device * pdev)200 gpio_nand_get_io_sync_of(struct platform_device *pdev)
201 {
202 return NULL;
203 }
204 #endif /* CONFIG_OF */
205
gpio_nand_get_config(const struct device * dev,struct gpio_nand_platdata * plat)206 static inline int gpio_nand_get_config(const struct device *dev,
207 struct gpio_nand_platdata *plat)
208 {
209 int ret = gpio_nand_get_config_of(dev, plat);
210
211 if (!ret)
212 return ret;
213
214 if (dev->platform_data) {
215 memcpy(plat, dev->platform_data, sizeof(*plat));
216 return 0;
217 }
218
219 return -EINVAL;
220 }
221
222 static inline struct resource *
gpio_nand_get_io_sync(struct platform_device * pdev)223 gpio_nand_get_io_sync(struct platform_device *pdev)
224 {
225 struct resource *r = gpio_nand_get_io_sync_of(pdev);
226
227 if (r)
228 return r;
229
230 return platform_get_resource(pdev, IORESOURCE_MEM, 1);
231 }
232
gpio_nand_remove(struct platform_device * dev)233 static int gpio_nand_remove(struct platform_device *dev)
234 {
235 struct gpiomtd *gpiomtd = platform_get_drvdata(dev);
236 struct resource *res;
237
238 nand_release(&gpiomtd->mtd_info);
239
240 res = gpio_nand_get_io_sync(dev);
241 iounmap(gpiomtd->io_sync);
242 if (res)
243 release_mem_region(res->start, resource_size(res));
244
245 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
246 iounmap(gpiomtd->nand_chip.IO_ADDR_R);
247 release_mem_region(res->start, resource_size(res));
248
249 if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
250 gpio_set_value(gpiomtd->plat.gpio_nwp, 0);
251 gpio_set_value(gpiomtd->plat.gpio_nce, 1);
252
253 gpio_free(gpiomtd->plat.gpio_cle);
254 gpio_free(gpiomtd->plat.gpio_ale);
255 gpio_free(gpiomtd->plat.gpio_nce);
256 if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
257 gpio_free(gpiomtd->plat.gpio_nwp);
258 if (gpio_is_valid(gpiomtd->plat.gpio_rdy))
259 gpio_free(gpiomtd->plat.gpio_rdy);
260
261 return 0;
262 }
263
request_and_remap(struct resource * res,size_t size,const char * name,int * err)264 static void __iomem *request_and_remap(struct resource *res, size_t size,
265 const char *name, int *err)
266 {
267 void __iomem *ptr;
268
269 if (!request_mem_region(res->start, resource_size(res), name)) {
270 *err = -EBUSY;
271 return NULL;
272 }
273
274 ptr = ioremap(res->start, size);
275 if (!ptr) {
276 release_mem_region(res->start, resource_size(res));
277 *err = -ENOMEM;
278 }
279 return ptr;
280 }
281
gpio_nand_probe(struct platform_device * dev)282 static int gpio_nand_probe(struct platform_device *dev)
283 {
284 struct gpiomtd *gpiomtd;
285 struct nand_chip *this;
286 struct resource *res0, *res1;
287 struct mtd_part_parser_data ppdata = {};
288 int ret = 0;
289
290 if (!dev->dev.of_node && !dev->dev.platform_data)
291 return -EINVAL;
292
293 res0 = platform_get_resource(dev, IORESOURCE_MEM, 0);
294 if (!res0)
295 return -EINVAL;
296
297 gpiomtd = devm_kzalloc(&dev->dev, sizeof(*gpiomtd), GFP_KERNEL);
298 if (gpiomtd == NULL) {
299 dev_err(&dev->dev, "failed to create NAND MTD\n");
300 return -ENOMEM;
301 }
302
303 this = &gpiomtd->nand_chip;
304 this->IO_ADDR_R = request_and_remap(res0, 2, "NAND", &ret);
305 if (!this->IO_ADDR_R) {
306 dev_err(&dev->dev, "unable to map NAND\n");
307 goto err_map;
308 }
309
310 res1 = gpio_nand_get_io_sync(dev);
311 if (res1) {
312 gpiomtd->io_sync = request_and_remap(res1, 4, "NAND sync", &ret);
313 if (!gpiomtd->io_sync) {
314 dev_err(&dev->dev, "unable to map sync NAND\n");
315 goto err_sync;
316 }
317 }
318
319 ret = gpio_nand_get_config(&dev->dev, &gpiomtd->plat);
320 if (ret)
321 goto err_nce;
322
323 ret = gpio_request(gpiomtd->plat.gpio_nce, "NAND NCE");
324 if (ret)
325 goto err_nce;
326 gpio_direction_output(gpiomtd->plat.gpio_nce, 1);
327 if (gpio_is_valid(gpiomtd->plat.gpio_nwp)) {
328 ret = gpio_request(gpiomtd->plat.gpio_nwp, "NAND NWP");
329 if (ret)
330 goto err_nwp;
331 gpio_direction_output(gpiomtd->plat.gpio_nwp, 1);
332 }
333 ret = gpio_request(gpiomtd->plat.gpio_ale, "NAND ALE");
334 if (ret)
335 goto err_ale;
336 gpio_direction_output(gpiomtd->plat.gpio_ale, 0);
337 ret = gpio_request(gpiomtd->plat.gpio_cle, "NAND CLE");
338 if (ret)
339 goto err_cle;
340 gpio_direction_output(gpiomtd->plat.gpio_cle, 0);
341 if (gpio_is_valid(gpiomtd->plat.gpio_rdy)) {
342 ret = gpio_request(gpiomtd->plat.gpio_rdy, "NAND RDY");
343 if (ret)
344 goto err_rdy;
345 gpio_direction_input(gpiomtd->plat.gpio_rdy);
346 }
347
348
349 this->IO_ADDR_W = this->IO_ADDR_R;
350 this->ecc.mode = NAND_ECC_SOFT;
351 this->options = gpiomtd->plat.options;
352 this->chip_delay = gpiomtd->plat.chip_delay;
353
354 /* install our routines */
355 this->cmd_ctrl = gpio_nand_cmd_ctrl;
356 this->dev_ready = gpio_nand_devready;
357
358 if (this->options & NAND_BUSWIDTH_16) {
359 this->read_buf = gpio_nand_readbuf16;
360 this->write_buf = gpio_nand_writebuf16;
361 } else {
362 this->read_buf = gpio_nand_readbuf;
363 this->write_buf = gpio_nand_writebuf;
364 }
365
366 /* set the mtd private data for the nand driver */
367 gpiomtd->mtd_info.priv = this;
368 gpiomtd->mtd_info.owner = THIS_MODULE;
369
370 if (nand_scan(&gpiomtd->mtd_info, 1)) {
371 dev_err(&dev->dev, "no nand chips found?\n");
372 ret = -ENXIO;
373 goto err_wp;
374 }
375
376 if (gpiomtd->plat.adjust_parts)
377 gpiomtd->plat.adjust_parts(&gpiomtd->plat,
378 gpiomtd->mtd_info.size);
379
380 ppdata.of_node = dev->dev.of_node;
381 ret = mtd_device_parse_register(&gpiomtd->mtd_info, NULL, &ppdata,
382 gpiomtd->plat.parts,
383 gpiomtd->plat.num_parts);
384 if (ret)
385 goto err_wp;
386 platform_set_drvdata(dev, gpiomtd);
387
388 return 0;
389
390 err_wp:
391 if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
392 gpio_set_value(gpiomtd->plat.gpio_nwp, 0);
393 if (gpio_is_valid(gpiomtd->plat.gpio_rdy))
394 gpio_free(gpiomtd->plat.gpio_rdy);
395 err_rdy:
396 gpio_free(gpiomtd->plat.gpio_cle);
397 err_cle:
398 gpio_free(gpiomtd->plat.gpio_ale);
399 err_ale:
400 if (gpio_is_valid(gpiomtd->plat.gpio_nwp))
401 gpio_free(gpiomtd->plat.gpio_nwp);
402 err_nwp:
403 gpio_free(gpiomtd->plat.gpio_nce);
404 err_nce:
405 iounmap(gpiomtd->io_sync);
406 if (res1)
407 release_mem_region(res1->start, resource_size(res1));
408 err_sync:
409 iounmap(gpiomtd->nand_chip.IO_ADDR_R);
410 release_mem_region(res0->start, resource_size(res0));
411 err_map:
412 return ret;
413 }
414
415 static struct platform_driver gpio_nand_driver = {
416 .probe = gpio_nand_probe,
417 .remove = gpio_nand_remove,
418 .driver = {
419 .name = "gpio-nand",
420 .of_match_table = of_match_ptr(gpio_nand_id_table),
421 },
422 };
423
424 module_platform_driver(gpio_nand_driver);
425
426 MODULE_LICENSE("GPL");
427 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
428 MODULE_DESCRIPTION("GPIO NAND Driver");
429