1 /*******************************************************************************
2 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
3 DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
4 developing this code.
5
6 This only implements the mac core functions for this chip.
7
8 Copyright (C) 2007-2009 STMicroelectronics Ltd
9
10 This program is free software; you can redistribute it and/or modify it
11 under the terms and conditions of the GNU General Public License,
12 version 2, as published by the Free Software Foundation.
13
14 This program is distributed in the hope it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 more details.
18
19 You should have received a copy of the GNU General Public License along with
20 this program; if not, write to the Free Software Foundation, Inc.,
21 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22
23 The full GNU General Public License is included in this distribution in
24 the file called "COPYING".
25
26 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
27 *******************************************************************************/
28
29 #include <linux/crc32.h>
30 #include <linux/slab.h>
31 #include <linux/ethtool.h>
32 #include <asm/io.h>
33 #include "dwmac1000.h"
34
dwmac1000_core_init(void __iomem * ioaddr)35 static void dwmac1000_core_init(void __iomem *ioaddr)
36 {
37 u32 value = readl(ioaddr + GMAC_CONTROL);
38 value |= GMAC_CORE_INIT;
39 writel(value, ioaddr + GMAC_CONTROL);
40
41 /* Mask GMAC interrupts */
42 writel(0x207, ioaddr + GMAC_INT_MASK);
43
44 #ifdef STMMAC_VLAN_TAG_USED
45 /* Tag detection without filtering */
46 writel(0x0, ioaddr + GMAC_VLAN_TAG);
47 #endif
48 }
49
dwmac1000_rx_ipc_enable(void __iomem * ioaddr)50 static int dwmac1000_rx_ipc_enable(void __iomem *ioaddr)
51 {
52 u32 value = readl(ioaddr + GMAC_CONTROL);
53
54 value |= GMAC_CONTROL_IPC;
55 writel(value, ioaddr + GMAC_CONTROL);
56
57 value = readl(ioaddr + GMAC_CONTROL);
58
59 return !!(value & GMAC_CONTROL_IPC);
60 }
61
dwmac1000_dump_regs(void __iomem * ioaddr)62 static void dwmac1000_dump_regs(void __iomem *ioaddr)
63 {
64 int i;
65 pr_info("\tDWMAC1000 regs (base addr = 0x%p)\n", ioaddr);
66
67 for (i = 0; i < 55; i++) {
68 int offset = i * 4;
69 pr_info("\tReg No. %d (offset 0x%x): 0x%08x\n", i,
70 offset, readl(ioaddr + offset));
71 }
72 }
73
dwmac1000_set_umac_addr(void __iomem * ioaddr,unsigned char * addr,unsigned int reg_n)74 static void dwmac1000_set_umac_addr(void __iomem *ioaddr, unsigned char *addr,
75 unsigned int reg_n)
76 {
77 stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
78 GMAC_ADDR_LOW(reg_n));
79 }
80
dwmac1000_get_umac_addr(void __iomem * ioaddr,unsigned char * addr,unsigned int reg_n)81 static void dwmac1000_get_umac_addr(void __iomem *ioaddr, unsigned char *addr,
82 unsigned int reg_n)
83 {
84 stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
85 GMAC_ADDR_LOW(reg_n));
86 }
87
dwmac1000_set_filter(struct net_device * dev,int id)88 static void dwmac1000_set_filter(struct net_device *dev, int id)
89 {
90 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
91 unsigned int value = 0;
92 unsigned int perfect_addr_number;
93
94 CHIP_DBG(KERN_INFO "%s: # mcasts %d, # unicast %d\n",
95 __func__, netdev_mc_count(dev), netdev_uc_count(dev));
96
97 if (dev->flags & IFF_PROMISC)
98 value = GMAC_FRAME_FILTER_PR;
99 else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
100 || (dev->flags & IFF_ALLMULTI)) {
101 value = GMAC_FRAME_FILTER_PM; /* pass all multi */
102 writel(0xffffffff, ioaddr + GMAC_HASH_HIGH);
103 writel(0xffffffff, ioaddr + GMAC_HASH_LOW);
104 } else if (!netdev_mc_empty(dev)) {
105 u32 mc_filter[2];
106 struct netdev_hw_addr *ha;
107
108 /* Hash filter for multicast */
109 value = GMAC_FRAME_FILTER_HMC;
110
111 memset(mc_filter, 0, sizeof(mc_filter));
112 netdev_for_each_mc_addr(ha, dev) {
113 /* The upper 6 bits of the calculated CRC are used to
114 * index the contens of the hash table
115 */
116 int bit_nr = bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26;
117 /* The most significant bit determines the register to
118 * use (H/L) while the other 5 bits determine the bit
119 * within the register.
120 */
121 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
122 }
123 writel(mc_filter[0], ioaddr + GMAC_HASH_LOW);
124 writel(mc_filter[1], ioaddr + GMAC_HASH_HIGH);
125 }
126
127 /* Extra 16 regs are available in cores newer than the 3.40. */
128 if (id > DWMAC_CORE_3_40)
129 perfect_addr_number = GMAC_MAX_PERFECT_ADDRESSES;
130 else
131 perfect_addr_number = GMAC_MAX_PERFECT_ADDRESSES / 2;
132
133 /* Handle multiple unicast addresses (perfect filtering) */
134 if (netdev_uc_count(dev) > perfect_addr_number)
135 /* Switch to promiscuous mode if more than 16 addrs
136 * are required
137 */
138 value |= GMAC_FRAME_FILTER_PR;
139 else {
140 int reg = 1;
141 struct netdev_hw_addr *ha;
142
143 netdev_for_each_uc_addr(ha, dev) {
144 dwmac1000_set_umac_addr(ioaddr, ha->addr, reg);
145 reg++;
146 }
147 }
148
149 #ifdef FRAME_FILTER_DEBUG
150 /* Enable Receive all mode (to debug filtering_fail errors) */
151 value |= GMAC_FRAME_FILTER_RA;
152 #endif
153 writel(value, ioaddr + GMAC_FRAME_FILTER);
154
155 CHIP_DBG(KERN_INFO "\tFilter: 0x%08x\n\tHash: HI 0x%08x, LO 0x%08x\n",
156 readl(ioaddr + GMAC_FRAME_FILTER),
157 readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW));
158 }
159
dwmac1000_flow_ctrl(void __iomem * ioaddr,unsigned int duplex,unsigned int fc,unsigned int pause_time)160 static void dwmac1000_flow_ctrl(void __iomem *ioaddr, unsigned int duplex,
161 unsigned int fc, unsigned int pause_time)
162 {
163 unsigned int flow = 0;
164
165 CHIP_DBG(KERN_DEBUG "GMAC Flow-Control:\n");
166 if (fc & FLOW_RX) {
167 CHIP_DBG(KERN_DEBUG "\tReceive Flow-Control ON\n");
168 flow |= GMAC_FLOW_CTRL_RFE;
169 }
170 if (fc & FLOW_TX) {
171 CHIP_DBG(KERN_DEBUG "\tTransmit Flow-Control ON\n");
172 flow |= GMAC_FLOW_CTRL_TFE;
173 }
174
175 if (duplex) {
176 CHIP_DBG(KERN_DEBUG "\tduplex mode: PAUSE %d\n", pause_time);
177 flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
178 }
179
180 writel(flow, ioaddr + GMAC_FLOW_CTRL);
181 }
182
dwmac1000_pmt(void __iomem * ioaddr,unsigned long mode)183 static void dwmac1000_pmt(void __iomem *ioaddr, unsigned long mode)
184 {
185 unsigned int pmt = 0;
186
187 if (mode & WAKE_MAGIC) {
188 CHIP_DBG(KERN_DEBUG "GMAC: WOL Magic frame\n");
189 pmt |= power_down | magic_pkt_en;
190 }
191 if (mode & WAKE_UCAST) {
192 CHIP_DBG(KERN_DEBUG "GMAC: WOL on global unicast\n");
193 pmt |= global_unicast;
194 }
195
196 writel(pmt, ioaddr + GMAC_PMT);
197 }
198
dwmac1000_irq_status(void __iomem * ioaddr,struct stmmac_extra_stats * x)199 static int dwmac1000_irq_status(void __iomem *ioaddr,
200 struct stmmac_extra_stats *x)
201 {
202 u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
203 int ret = 0;
204
205 /* Not used events (e.g. MMC interrupts) are not handled. */
206 if ((intr_status & mmc_tx_irq)) {
207 CHIP_DBG(KERN_INFO "GMAC: MMC tx interrupt: 0x%08x\n",
208 readl(ioaddr + GMAC_MMC_TX_INTR));
209 x->mmc_tx_irq_n++;
210 }
211 if (unlikely(intr_status & mmc_rx_irq)) {
212 CHIP_DBG(KERN_INFO "GMAC: MMC rx interrupt: 0x%08x\n",
213 readl(ioaddr + GMAC_MMC_RX_INTR));
214 x->mmc_rx_irq_n++;
215 }
216 if (unlikely(intr_status & mmc_rx_csum_offload_irq)) {
217 CHIP_DBG(KERN_INFO "GMAC: MMC rx csum offload: 0x%08x\n",
218 readl(ioaddr + GMAC_MMC_RX_CSUM_OFFLOAD));
219 x->mmc_rx_csum_offload_irq_n++;
220 }
221 if (unlikely(intr_status & pmt_irq)) {
222 CHIP_DBG(KERN_INFO "GMAC: received Magic frame\n");
223 /* clear the PMT bits 5 and 6 by reading the PMT status reg */
224 readl(ioaddr + GMAC_PMT);
225 x->irq_receive_pmt_irq_n++;
226 }
227 /* MAC trx/rx EEE LPI entry/exit interrupts */
228 if (intr_status & lpiis_irq) {
229 /* Clean LPI interrupt by reading the Reg 12 */
230 ret = readl(ioaddr + LPI_CTRL_STATUS);
231
232 if (ret & LPI_CTRL_STATUS_TLPIEN) {
233 CHIP_DBG(KERN_INFO "GMAC TX entered in LPI\n");
234 x->irq_tx_path_in_lpi_mode_n++;
235 }
236 if (ret & LPI_CTRL_STATUS_TLPIEX) {
237 CHIP_DBG(KERN_INFO "GMAC TX exit from LPI\n");
238 x->irq_tx_path_exit_lpi_mode_n++;
239 }
240 if (ret & LPI_CTRL_STATUS_RLPIEN) {
241 CHIP_DBG(KERN_INFO "GMAC RX entered in LPI\n");
242 x->irq_rx_path_in_lpi_mode_n++;
243 }
244 if (ret & LPI_CTRL_STATUS_RLPIEX) {
245 CHIP_DBG(KERN_INFO "GMAC RX exit from LPI\n");
246 x->irq_rx_path_exit_lpi_mode_n++;
247 }
248 }
249
250 if ((intr_status & pcs_ane_irq) || (intr_status & pcs_link_irq)) {
251 CHIP_DBG(KERN_INFO "GMAC PCS ANE IRQ\n");
252 readl(ioaddr + GMAC_AN_STATUS);
253 x->irq_pcs_ane_n++;
254 }
255 if (intr_status & rgmii_irq) {
256 u32 status = readl(ioaddr + GMAC_S_R_GMII);
257 CHIP_DBG(KERN_INFO "GMAC RGMII/SGMII interrupt\n");
258 x->irq_rgmii_n++;
259
260 /* Save and dump the link status. */
261 if (status & GMAC_S_R_GMII_LINK) {
262 int speed_value = (status & GMAC_S_R_GMII_SPEED) >>
263 GMAC_S_R_GMII_SPEED_SHIFT;
264 x->pcs_duplex = (status & GMAC_S_R_GMII_MODE);
265
266 if (speed_value == GMAC_S_R_GMII_SPEED_125)
267 x->pcs_speed = SPEED_1000;
268 else if (speed_value == GMAC_S_R_GMII_SPEED_25)
269 x->pcs_speed = SPEED_100;
270 else
271 x->pcs_speed = SPEED_10;
272
273 x->pcs_link = 1;
274 pr_debug("Link is Up - %d/%s\n", (int)x->pcs_speed,
275 x->pcs_duplex ? "Full" : "Half");
276 } else {
277 x->pcs_link = 0;
278 pr_debug("Link is Down\n");
279 }
280 }
281
282 return ret;
283 }
284
dwmac1000_set_eee_mode(void __iomem * ioaddr)285 static void dwmac1000_set_eee_mode(void __iomem *ioaddr)
286 {
287 u32 value;
288
289 /* Enable the link status receive on RGMII, SGMII ore SMII
290 * receive path and instruct the transmit to enter in LPI
291 * state.
292 */
293 value = readl(ioaddr + LPI_CTRL_STATUS);
294 value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
295 writel(value, ioaddr + LPI_CTRL_STATUS);
296 }
297
dwmac1000_reset_eee_mode(void __iomem * ioaddr)298 static void dwmac1000_reset_eee_mode(void __iomem *ioaddr)
299 {
300 u32 value;
301
302 value = readl(ioaddr + LPI_CTRL_STATUS);
303 value &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA);
304 writel(value, ioaddr + LPI_CTRL_STATUS);
305 }
306
dwmac1000_set_eee_pls(void __iomem * ioaddr,int link)307 static void dwmac1000_set_eee_pls(void __iomem *ioaddr, int link)
308 {
309 u32 value;
310
311 value = readl(ioaddr + LPI_CTRL_STATUS);
312
313 if (link)
314 value |= LPI_CTRL_STATUS_PLS;
315 else
316 value &= ~LPI_CTRL_STATUS_PLS;
317
318 writel(value, ioaddr + LPI_CTRL_STATUS);
319 }
320
dwmac1000_set_eee_timer(void __iomem * ioaddr,int ls,int tw)321 static void dwmac1000_set_eee_timer(void __iomem *ioaddr, int ls, int tw)
322 {
323 int value = ((tw & 0xffff)) | ((ls & 0x7ff) << 16);
324
325 /* Program the timers in the LPI timer control register:
326 * LS: minimum time (ms) for which the link
327 * status from PHY should be ok before transmitting
328 * the LPI pattern.
329 * TW: minimum time (us) for which the core waits
330 * after it has stopped transmitting the LPI pattern.
331 */
332 writel(value, ioaddr + LPI_TIMER_CTRL);
333 }
334
dwmac1000_ctrl_ane(void __iomem * ioaddr,bool restart)335 static void dwmac1000_ctrl_ane(void __iomem *ioaddr, bool restart)
336 {
337 u32 value;
338
339 value = readl(ioaddr + GMAC_AN_CTRL);
340 /* auto negotiation enable and External Loopback enable */
341 value = GMAC_AN_CTRL_ANE | GMAC_AN_CTRL_ELE;
342
343 if (restart)
344 value |= GMAC_AN_CTRL_RAN;
345
346 writel(value, ioaddr + GMAC_AN_CTRL);
347 }
348
dwmac1000_get_adv(void __iomem * ioaddr,struct rgmii_adv * adv)349 static void dwmac1000_get_adv(void __iomem *ioaddr, struct rgmii_adv *adv)
350 {
351 u32 value = readl(ioaddr + GMAC_ANE_ADV);
352
353 if (value & GMAC_ANE_FD)
354 adv->duplex = DUPLEX_FULL;
355 if (value & GMAC_ANE_HD)
356 adv->duplex |= DUPLEX_HALF;
357
358 adv->pause = (value & GMAC_ANE_PSE) >> GMAC_ANE_PSE_SHIFT;
359
360 value = readl(ioaddr + GMAC_ANE_LPA);
361
362 if (value & GMAC_ANE_FD)
363 adv->lp_duplex = DUPLEX_FULL;
364 if (value & GMAC_ANE_HD)
365 adv->lp_duplex = DUPLEX_HALF;
366
367 adv->lp_pause = (value & GMAC_ANE_PSE) >> GMAC_ANE_PSE_SHIFT;
368 }
369
370 static const struct stmmac_ops dwmac1000_ops = {
371 .core_init = dwmac1000_core_init,
372 .rx_ipc = dwmac1000_rx_ipc_enable,
373 .dump_regs = dwmac1000_dump_regs,
374 .host_irq_status = dwmac1000_irq_status,
375 .set_filter = dwmac1000_set_filter,
376 .flow_ctrl = dwmac1000_flow_ctrl,
377 .pmt = dwmac1000_pmt,
378 .set_umac_addr = dwmac1000_set_umac_addr,
379 .get_umac_addr = dwmac1000_get_umac_addr,
380 .set_eee_mode = dwmac1000_set_eee_mode,
381 .reset_eee_mode = dwmac1000_reset_eee_mode,
382 .set_eee_timer = dwmac1000_set_eee_timer,
383 .set_eee_pls = dwmac1000_set_eee_pls,
384 .ctrl_ane = dwmac1000_ctrl_ane,
385 .get_adv = dwmac1000_get_adv,
386 };
387
dwmac1000_setup(void __iomem * ioaddr)388 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr)
389 {
390 struct mac_device_info *mac;
391 u32 hwid = readl(ioaddr + GMAC_VERSION);
392
393 mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
394 if (!mac)
395 return NULL;
396
397 mac->mac = &dwmac1000_ops;
398 mac->dma = &dwmac1000_dma_ops;
399
400 mac->link.port = GMAC_CONTROL_PS;
401 mac->link.duplex = GMAC_CONTROL_DM;
402 mac->link.speed = GMAC_CONTROL_FES;
403 mac->mii.addr = GMAC_MII_ADDR;
404 mac->mii.data = GMAC_MII_DATA;
405 mac->synopsys_uid = hwid;
406
407 return mac;
408 }
409