1 /*******************************************************************************
2 This is the driver for the MAC 10/100 on-chip Ethernet controller
3 currently tested on all the ST boards based on STb7109 and stx7200 SoCs.
4
5 DWC Ether MAC 10/100 Universal version 4.0 has been used for developing
6 this code.
7
8 This only implements the mac core functions for this chip.
9
10 Copyright (C) 2007-2009 STMicroelectronics Ltd
11
12 This program is free software; you can redistribute it and/or modify it
13 under the terms and conditions of the GNU General Public License,
14 version 2, as published by the Free Software Foundation.
15
16 This program is distributed in the hope it will be useful, but WITHOUT
17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 more details.
20
21 You should have received a copy of the GNU General Public License along with
22 this program; if not, write to the Free Software Foundation, Inc.,
23 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
24
25 The full GNU General Public License is included in this distribution in
26 the file called "COPYING".
27
28 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
29 *******************************************************************************/
30
31 #include <linux/crc32.h>
32 #include <asm/io.h>
33 #include "dwmac100.h"
34
dwmac100_core_init(void __iomem * ioaddr)35 static void dwmac100_core_init(void __iomem *ioaddr)
36 {
37 u32 value = readl(ioaddr + MAC_CONTROL);
38
39 writel((value | MAC_CORE_INIT), ioaddr + MAC_CONTROL);
40
41 #ifdef STMMAC_VLAN_TAG_USED
42 writel(ETH_P_8021Q, ioaddr + MAC_VLAN1);
43 #endif
44 }
45
dwmac100_dump_mac_regs(void __iomem * ioaddr)46 static void dwmac100_dump_mac_regs(void __iomem *ioaddr)
47 {
48 pr_info("\t----------------------------------------------\n"
49 "\t DWMAC 100 CSR (base addr = 0x%p)\n"
50 "\t----------------------------------------------\n", ioaddr);
51 pr_info("\tcontrol reg (offset 0x%x): 0x%08x\n", MAC_CONTROL,
52 readl(ioaddr + MAC_CONTROL));
53 pr_info("\taddr HI (offset 0x%x): 0x%08x\n ", MAC_ADDR_HIGH,
54 readl(ioaddr + MAC_ADDR_HIGH));
55 pr_info("\taddr LO (offset 0x%x): 0x%08x\n", MAC_ADDR_LOW,
56 readl(ioaddr + MAC_ADDR_LOW));
57 pr_info("\tmulticast hash HI (offset 0x%x): 0x%08x\n",
58 MAC_HASH_HIGH, readl(ioaddr + MAC_HASH_HIGH));
59 pr_info("\tmulticast hash LO (offset 0x%x): 0x%08x\n",
60 MAC_HASH_LOW, readl(ioaddr + MAC_HASH_LOW));
61 pr_info("\tflow control (offset 0x%x): 0x%08x\n",
62 MAC_FLOW_CTRL, readl(ioaddr + MAC_FLOW_CTRL));
63 pr_info("\tVLAN1 tag (offset 0x%x): 0x%08x\n", MAC_VLAN1,
64 readl(ioaddr + MAC_VLAN1));
65 pr_info("\tVLAN2 tag (offset 0x%x): 0x%08x\n", MAC_VLAN2,
66 readl(ioaddr + MAC_VLAN2));
67 }
68
dwmac100_rx_ipc_enable(void __iomem * ioaddr)69 static int dwmac100_rx_ipc_enable(void __iomem *ioaddr)
70 {
71 return 0;
72 }
73
dwmac100_irq_status(void __iomem * ioaddr,struct stmmac_extra_stats * x)74 static int dwmac100_irq_status(void __iomem *ioaddr,
75 struct stmmac_extra_stats *x)
76 {
77 return 0;
78 }
79
dwmac100_set_umac_addr(void __iomem * ioaddr,unsigned char * addr,unsigned int reg_n)80 static void dwmac100_set_umac_addr(void __iomem *ioaddr, unsigned char *addr,
81 unsigned int reg_n)
82 {
83 stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
84 }
85
dwmac100_get_umac_addr(void __iomem * ioaddr,unsigned char * addr,unsigned int reg_n)86 static void dwmac100_get_umac_addr(void __iomem *ioaddr, unsigned char *addr,
87 unsigned int reg_n)
88 {
89 stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
90 }
91
dwmac100_set_filter(struct net_device * dev,int id)92 static void dwmac100_set_filter(struct net_device *dev, int id)
93 {
94 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
95 u32 value = readl(ioaddr + MAC_CONTROL);
96
97 if (dev->flags & IFF_PROMISC) {
98 value |= MAC_CONTROL_PR;
99 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_IF | MAC_CONTROL_HO |
100 MAC_CONTROL_HP);
101 } else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
102 || (dev->flags & IFF_ALLMULTI)) {
103 value |= MAC_CONTROL_PM;
104 value &= ~(MAC_CONTROL_PR | MAC_CONTROL_IF | MAC_CONTROL_HO);
105 writel(0xffffffff, ioaddr + MAC_HASH_HIGH);
106 writel(0xffffffff, ioaddr + MAC_HASH_LOW);
107 } else if (netdev_mc_empty(dev)) { /* no multicast */
108 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR | MAC_CONTROL_IF |
109 MAC_CONTROL_HO | MAC_CONTROL_HP);
110 } else {
111 u32 mc_filter[2];
112 struct netdev_hw_addr *ha;
113
114 /* Perfect filter mode for physical address and Hash
115 * filter for multicast
116 */
117 value |= MAC_CONTROL_HP;
118 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR |
119 MAC_CONTROL_IF | MAC_CONTROL_HO);
120
121 memset(mc_filter, 0, sizeof(mc_filter));
122 netdev_for_each_mc_addr(ha, dev) {
123 /* The upper 6 bits of the calculated CRC are used to
124 * index the contens of the hash table
125 */
126 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
127 /* The most significant bit determines the register to
128 * use (H/L) while the other 5 bits determine the bit
129 * within the register.
130 */
131 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
132 }
133 writel(mc_filter[0], ioaddr + MAC_HASH_LOW);
134 writel(mc_filter[1], ioaddr + MAC_HASH_HIGH);
135 }
136
137 writel(value, ioaddr + MAC_CONTROL);
138
139 CHIP_DBG(KERN_INFO "%s: Filter: 0x%08x Hash: HI 0x%08x, LO 0x%08x\n",
140 __func__, readl(ioaddr + MAC_CONTROL),
141 readl(ioaddr + MAC_HASH_HIGH), readl(ioaddr + MAC_HASH_LOW));
142 }
143
dwmac100_flow_ctrl(void __iomem * ioaddr,unsigned int duplex,unsigned int fc,unsigned int pause_time)144 static void dwmac100_flow_ctrl(void __iomem *ioaddr, unsigned int duplex,
145 unsigned int fc, unsigned int pause_time)
146 {
147 unsigned int flow = MAC_FLOW_CTRL_ENABLE;
148
149 if (duplex)
150 flow |= (pause_time << MAC_FLOW_CTRL_PT_SHIFT);
151 writel(flow, ioaddr + MAC_FLOW_CTRL);
152 }
153
154 /* No PMT module supported on ST boards with this Eth chip. */
dwmac100_pmt(void __iomem * ioaddr,unsigned long mode)155 static void dwmac100_pmt(void __iomem *ioaddr, unsigned long mode)
156 {
157 return;
158 }
159
160 static const struct stmmac_ops dwmac100_ops = {
161 .core_init = dwmac100_core_init,
162 .rx_ipc = dwmac100_rx_ipc_enable,
163 .dump_regs = dwmac100_dump_mac_regs,
164 .host_irq_status = dwmac100_irq_status,
165 .set_filter = dwmac100_set_filter,
166 .flow_ctrl = dwmac100_flow_ctrl,
167 .pmt = dwmac100_pmt,
168 .set_umac_addr = dwmac100_set_umac_addr,
169 .get_umac_addr = dwmac100_get_umac_addr,
170 };
171
dwmac100_setup(void __iomem * ioaddr)172 struct mac_device_info *dwmac100_setup(void __iomem *ioaddr)
173 {
174 struct mac_device_info *mac;
175
176 mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
177 if (!mac)
178 return NULL;
179
180 pr_info("\tDWMAC100\n");
181
182 mac->mac = &dwmac100_ops;
183 mac->dma = &dwmac100_dma_ops;
184
185 mac->link.port = MAC_CONTROL_PS;
186 mac->link.duplex = MAC_CONTROL_F;
187 mac->link.speed = 0;
188 mac->mii.addr = MAC_MII_ADDR;
189 mac->mii.data = MAC_MII_DATA;
190 mac->synopsys_uid = 0;
191
192 return mac;
193 }
194