1 /*******************************************************************************
2 STMMAC Ethernet Driver -- MDIO bus implementation
3 Provides Bus interface for MII registers
4
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
10
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
22
23 Author: Carl Shaw <carl.shaw@st.com>
24 Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25 *******************************************************************************/
26
27 #include <linux/mii.h>
28 #include <linux/phy.h>
29 #include <linux/slab.h>
30 #include <asm/io.h>
31
32 #include "stmmac.h"
33
34 #define MII_BUSY 0x00000001
35 #define MII_WRITE 0x00000002
36
stmmac_mdio_busy_wait(void __iomem * ioaddr,unsigned int mii_addr)37 static int stmmac_mdio_busy_wait(void __iomem *ioaddr, unsigned int mii_addr)
38 {
39 unsigned long curr;
40 unsigned long finish = jiffies + 3 * HZ;
41
42 do {
43 curr = jiffies;
44 if (readl(ioaddr + mii_addr) & MII_BUSY)
45 cpu_relax();
46 else
47 return 0;
48 } while (!time_after_eq(curr, finish));
49
50 return -EBUSY;
51 }
52
53 /**
54 * stmmac_mdio_read
55 * @bus: points to the mii_bus structure
56 * @phyaddr: MII addr reg bits 15-11
57 * @phyreg: MII addr reg bits 10-6
58 * Description: it reads data from the MII register from within the phy device.
59 * For the 7111 GMAC, we must set the bit 0 in the MII address register while
60 * accessing the PHY registers.
61 * Fortunately, it seems this has no drawback for the 7109 MAC.
62 */
stmmac_mdio_read(struct mii_bus * bus,int phyaddr,int phyreg)63 static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
64 {
65 struct net_device *ndev = bus->priv;
66 struct stmmac_priv *priv = netdev_priv(ndev);
67 unsigned int mii_address = priv->hw->mii.addr;
68 unsigned int mii_data = priv->hw->mii.data;
69
70 int data;
71 u16 regValue = (((phyaddr << 11) & (0x0000F800)) |
72 ((phyreg << 6) & (0x000007C0)));
73 regValue |= MII_BUSY | ((priv->clk_csr & 0xF) << 2);
74
75 if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
76 return -EBUSY;
77
78 writel(regValue, priv->ioaddr + mii_address);
79
80 if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
81 return -EBUSY;
82
83 /* Read the data from the MII data register */
84 data = (int)readl(priv->ioaddr + mii_data);
85
86 return data;
87 }
88
89 /**
90 * stmmac_mdio_write
91 * @bus: points to the mii_bus structure
92 * @phyaddr: MII addr reg bits 15-11
93 * @phyreg: MII addr reg bits 10-6
94 * @phydata: phy data
95 * Description: it writes the data into the MII register from within the device.
96 */
stmmac_mdio_write(struct mii_bus * bus,int phyaddr,int phyreg,u16 phydata)97 static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
98 u16 phydata)
99 {
100 struct net_device *ndev = bus->priv;
101 struct stmmac_priv *priv = netdev_priv(ndev);
102 unsigned int mii_address = priv->hw->mii.addr;
103 unsigned int mii_data = priv->hw->mii.data;
104
105 u16 value =
106 (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0)))
107 | MII_WRITE;
108
109 value |= MII_BUSY | ((priv->clk_csr & 0xF) << 2);
110
111 /* Wait until any existing MII operation is complete */
112 if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
113 return -EBUSY;
114
115 /* Set the MII address register to write */
116 writel(phydata, priv->ioaddr + mii_data);
117 writel(value, priv->ioaddr + mii_address);
118
119 /* Wait until any existing MII operation is complete */
120 return stmmac_mdio_busy_wait(priv->ioaddr, mii_address);
121 }
122
123 /**
124 * stmmac_mdio_reset
125 * @bus: points to the mii_bus structure
126 * Description: reset the MII bus
127 */
stmmac_mdio_reset(struct mii_bus * bus)128 static int stmmac_mdio_reset(struct mii_bus *bus)
129 {
130 #if defined(CONFIG_STMMAC_PLATFORM)
131 struct net_device *ndev = bus->priv;
132 struct stmmac_priv *priv = netdev_priv(ndev);
133 unsigned int mii_address = priv->hw->mii.addr;
134
135 if (priv->plat->mdio_bus_data->phy_reset) {
136 pr_debug("stmmac_mdio_reset: calling phy_reset\n");
137 priv->plat->mdio_bus_data->phy_reset(priv->plat->bsp_priv);
138 }
139
140 /* This is a workaround for problems with the STE101P PHY.
141 * It doesn't complete its reset until at least one clock cycle
142 * on MDC, so perform a dummy mdio read.
143 */
144 writel(0, priv->ioaddr + mii_address);
145 #endif
146 return 0;
147 }
148
149 /**
150 * stmmac_mdio_register
151 * @ndev: net device structure
152 * Description: it registers the MII bus
153 */
stmmac_mdio_register(struct net_device * ndev)154 int stmmac_mdio_register(struct net_device *ndev)
155 {
156 int err = 0;
157 struct mii_bus *new_bus;
158 int *irqlist;
159 struct stmmac_priv *priv = netdev_priv(ndev);
160 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
161 int addr, found;
162
163 if (!mdio_bus_data)
164 return 0;
165
166 new_bus = mdiobus_alloc();
167 if (new_bus == NULL)
168 return -ENOMEM;
169
170 if (mdio_bus_data->irqs)
171 irqlist = mdio_bus_data->irqs;
172 else
173 irqlist = priv->mii_irq;
174
175 new_bus->name = "stmmac";
176 new_bus->read = &stmmac_mdio_read;
177 new_bus->write = &stmmac_mdio_write;
178 new_bus->reset = &stmmac_mdio_reset;
179 snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%x",
180 new_bus->name, priv->plat->bus_id);
181 new_bus->priv = ndev;
182 new_bus->irq = irqlist;
183 new_bus->phy_mask = mdio_bus_data->phy_mask;
184 new_bus->parent = priv->device;
185 err = mdiobus_register(new_bus);
186 if (err != 0) {
187 pr_err("%s: Cannot register as MDIO bus\n", new_bus->name);
188 goto bus_register_fail;
189 }
190
191 found = 0;
192 for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
193 struct phy_device *phydev = new_bus->phy_map[addr];
194 if (phydev) {
195 int act = 0;
196 char irq_num[4];
197 char *irq_str;
198
199 /*
200 * If an IRQ was provided to be assigned after
201 * the bus probe, do it here.
202 */
203 if ((mdio_bus_data->irqs == NULL) &&
204 (mdio_bus_data->probed_phy_irq > 0)) {
205 irqlist[addr] = mdio_bus_data->probed_phy_irq;
206 phydev->irq = mdio_bus_data->probed_phy_irq;
207 }
208
209 /*
210 * If we're going to bind the MAC to this PHY bus,
211 * and no PHY number was provided to the MAC,
212 * use the one probed here.
213 */
214 if (priv->plat->phy_addr == -1)
215 priv->plat->phy_addr = addr;
216
217 act = (priv->plat->phy_addr == addr);
218 switch (phydev->irq) {
219 case PHY_POLL:
220 irq_str = "POLL";
221 break;
222 case PHY_IGNORE_INTERRUPT:
223 irq_str = "IGNORE";
224 break;
225 default:
226 sprintf(irq_num, "%d", phydev->irq);
227 irq_str = irq_num;
228 break;
229 }
230 pr_info("%s: PHY ID %08x at %d IRQ %s (%s)%s\n",
231 ndev->name, phydev->phy_id, addr,
232 irq_str, dev_name(&phydev->dev),
233 act ? " active" : "");
234 found = 1;
235 }
236 }
237
238 if (!found) {
239 pr_warning("%s: No PHY found\n", ndev->name);
240 mdiobus_unregister(new_bus);
241 mdiobus_free(new_bus);
242 return -ENODEV;
243 }
244
245 priv->mii = new_bus;
246
247 return 0;
248
249 bus_register_fail:
250 mdiobus_free(new_bus);
251 return err;
252 }
253
254 /**
255 * stmmac_mdio_unregister
256 * @ndev: net device structure
257 * Description: it unregisters the MII bus
258 */
stmmac_mdio_unregister(struct net_device * ndev)259 int stmmac_mdio_unregister(struct net_device *ndev)
260 {
261 struct stmmac_priv *priv = netdev_priv(ndev);
262
263 if (!priv->mii)
264 return 0;
265
266 mdiobus_unregister(priv->mii);
267 priv->mii->priv = NULL;
268 mdiobus_free(priv->mii);
269 priv->mii = NULL;
270
271 return 0;
272 }
273