1 /* 2 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com> 3 <http://rt2x00.serialmonkey.com> 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 2 of the License, or 8 (at your option) any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, write to the 17 Free Software Foundation, Inc., 18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 */ 20 21 /* 22 Module: rt2500usb 23 Abstract: Data structures and registers for the rt2500usb module. 24 Supported chipsets: RT2570. 25 */ 26 27 #ifndef RT2500USB_H 28 #define RT2500USB_H 29 30 /* 31 * RF chip defines. 32 */ 33 #define RF2522 0x0000 34 #define RF2523 0x0001 35 #define RF2524 0x0002 36 #define RF2525 0x0003 37 #define RF2525E 0x0005 38 #define RF5222 0x0010 39 40 /* 41 * RT2570 version 42 */ 43 #define RT2570_VERSION_B 2 44 #define RT2570_VERSION_C 3 45 #define RT2570_VERSION_D 4 46 47 /* 48 * Signal information. 49 * Default offset is required for RSSI <-> dBm conversion. 50 */ 51 #define DEFAULT_RSSI_OFFSET 120 52 53 /* 54 * Register layout information. 55 */ 56 #define CSR_REG_BASE 0x0400 57 #define CSR_REG_SIZE 0x0100 58 #define EEPROM_BASE 0x0000 59 #define EEPROM_SIZE 0x006a 60 #define BBP_BASE 0x0000 61 #define BBP_SIZE 0x0060 62 #define RF_BASE 0x0004 63 #define RF_SIZE 0x0010 64 65 /* 66 * Number of TX queues. 67 */ 68 #define NUM_TX_QUEUES 2 69 70 /* 71 * Control/Status Registers(CSR). 72 * Some values are set in TU, whereas 1 TU == 1024 us. 73 */ 74 75 /* 76 * MAC_CSR0: ASIC revision number. 77 */ 78 #define MAC_CSR0 0x0400 79 80 /* 81 * MAC_CSR1: System control. 82 * SOFT_RESET: Software reset, 1: reset, 0: normal. 83 * BBP_RESET: Hardware reset, 1: reset, 0, release. 84 * HOST_READY: Host ready after initialization. 85 */ 86 #define MAC_CSR1 0x0402 87 #define MAC_CSR1_SOFT_RESET FIELD16(0x00000001) 88 #define MAC_CSR1_BBP_RESET FIELD16(0x00000002) 89 #define MAC_CSR1_HOST_READY FIELD16(0x00000004) 90 91 /* 92 * MAC_CSR2: STA MAC register 0. 93 */ 94 #define MAC_CSR2 0x0404 95 #define MAC_CSR2_BYTE0 FIELD16(0x00ff) 96 #define MAC_CSR2_BYTE1 FIELD16(0xff00) 97 98 /* 99 * MAC_CSR3: STA MAC register 1. 100 */ 101 #define MAC_CSR3 0x0406 102 #define MAC_CSR3_BYTE2 FIELD16(0x00ff) 103 #define MAC_CSR3_BYTE3 FIELD16(0xff00) 104 105 /* 106 * MAC_CSR4: STA MAC register 2. 107 */ 108 #define MAC_CSR4 0X0408 109 #define MAC_CSR4_BYTE4 FIELD16(0x00ff) 110 #define MAC_CSR4_BYTE5 FIELD16(0xff00) 111 112 /* 113 * MAC_CSR5: BSSID register 0. 114 */ 115 #define MAC_CSR5 0x040a 116 #define MAC_CSR5_BYTE0 FIELD16(0x00ff) 117 #define MAC_CSR5_BYTE1 FIELD16(0xff00) 118 119 /* 120 * MAC_CSR6: BSSID register 1. 121 */ 122 #define MAC_CSR6 0x040c 123 #define MAC_CSR6_BYTE2 FIELD16(0x00ff) 124 #define MAC_CSR6_BYTE3 FIELD16(0xff00) 125 126 /* 127 * MAC_CSR7: BSSID register 2. 128 */ 129 #define MAC_CSR7 0x040e 130 #define MAC_CSR7_BYTE4 FIELD16(0x00ff) 131 #define MAC_CSR7_BYTE5 FIELD16(0xff00) 132 133 /* 134 * MAC_CSR8: Max frame length. 135 */ 136 #define MAC_CSR8 0x0410 137 #define MAC_CSR8_MAX_FRAME_UNIT FIELD16(0x0fff) 138 139 /* 140 * Misc MAC_CSR registers. 141 * MAC_CSR9: Timer control. 142 * MAC_CSR10: Slot time. 143 * MAC_CSR11: SIFS. 144 * MAC_CSR12: EIFS. 145 * MAC_CSR13: Power mode0. 146 * MAC_CSR14: Power mode1. 147 * MAC_CSR15: Power saving transition0 148 * MAC_CSR16: Power saving transition1 149 */ 150 #define MAC_CSR9 0x0412 151 #define MAC_CSR10 0x0414 152 #define MAC_CSR11 0x0416 153 #define MAC_CSR12 0x0418 154 #define MAC_CSR13 0x041a 155 #define MAC_CSR14 0x041c 156 #define MAC_CSR15 0x041e 157 #define MAC_CSR16 0x0420 158 159 /* 160 * MAC_CSR17: Manual power control / status register. 161 * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake. 162 * SET_STATE: Set state. Write 1 to trigger, self cleared. 163 * BBP_DESIRE_STATE: BBP desired state. 164 * RF_DESIRE_STATE: RF desired state. 165 * BBP_CURRENT_STATE: BBP current state. 166 * RF_CURRENT_STATE: RF current state. 167 * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared. 168 */ 169 #define MAC_CSR17 0x0422 170 #define MAC_CSR17_SET_STATE FIELD16(0x0001) 171 #define MAC_CSR17_BBP_DESIRE_STATE FIELD16(0x0006) 172 #define MAC_CSR17_RF_DESIRE_STATE FIELD16(0x0018) 173 #define MAC_CSR17_BBP_CURR_STATE FIELD16(0x0060) 174 #define MAC_CSR17_RF_CURR_STATE FIELD16(0x0180) 175 #define MAC_CSR17_PUT_TO_SLEEP FIELD16(0x0200) 176 177 /* 178 * MAC_CSR18: Wakeup timer register. 179 * DELAY_AFTER_BEACON: Delay after Tbcn expired in units of 1/16 TU. 180 * BEACONS_BEFORE_WAKEUP: Number of beacon before wakeup. 181 * AUTO_WAKE: Enable auto wakeup / sleep mechanism. 182 */ 183 #define MAC_CSR18 0x0424 184 #define MAC_CSR18_DELAY_AFTER_BEACON FIELD16(0x00ff) 185 #define MAC_CSR18_BEACONS_BEFORE_WAKEUP FIELD16(0x7f00) 186 #define MAC_CSR18_AUTO_WAKE FIELD16(0x8000) 187 188 /* 189 * MAC_CSR19: GPIO control register. 190 * MAC_CSR19_VALx: GPIO value 191 * MAC_CSR19_DIRx: GPIO direction: 0 = input; 1 = output 192 */ 193 #define MAC_CSR19 0x0426 194 #define MAC_CSR19_VAL0 FIELD16(0x0001) 195 #define MAC_CSR19_VAL1 FIELD16(0x0002) 196 #define MAC_CSR19_VAL2 FIELD16(0x0004) 197 #define MAC_CSR19_VAL3 FIELD16(0x0008) 198 #define MAC_CSR19_VAL4 FIELD16(0x0010) 199 #define MAC_CSR19_VAL5 FIELD16(0x0020) 200 #define MAC_CSR19_VAL6 FIELD16(0x0040) 201 #define MAC_CSR19_VAL7 FIELD16(0x0080) 202 #define MAC_CSR19_DIR0 FIELD16(0x0100) 203 #define MAC_CSR19_DIR1 FIELD16(0x0200) 204 #define MAC_CSR19_DIR2 FIELD16(0x0400) 205 #define MAC_CSR19_DIR3 FIELD16(0x0800) 206 #define MAC_CSR19_DIR4 FIELD16(0x1000) 207 #define MAC_CSR19_DIR5 FIELD16(0x2000) 208 #define MAC_CSR19_DIR6 FIELD16(0x4000) 209 #define MAC_CSR19_DIR7 FIELD16(0x8000) 210 211 /* 212 * MAC_CSR20: LED control register. 213 * ACTIVITY: 0: idle, 1: active. 214 * LINK: 0: linkoff, 1: linkup. 215 * ACTIVITY_POLARITY: 0: active low, 1: active high. 216 */ 217 #define MAC_CSR20 0x0428 218 #define MAC_CSR20_ACTIVITY FIELD16(0x0001) 219 #define MAC_CSR20_LINK FIELD16(0x0002) 220 #define MAC_CSR20_ACTIVITY_POLARITY FIELD16(0x0004) 221 222 /* 223 * MAC_CSR21: LED control register. 224 * ON_PERIOD: On period, default 70ms. 225 * OFF_PERIOD: Off period, default 30ms. 226 */ 227 #define MAC_CSR21 0x042a 228 #define MAC_CSR21_ON_PERIOD FIELD16(0x00ff) 229 #define MAC_CSR21_OFF_PERIOD FIELD16(0xff00) 230 231 /* 232 * MAC_CSR22: Collision window control register. 233 */ 234 #define MAC_CSR22 0x042c 235 236 /* 237 * Transmit related CSRs. 238 * Some values are set in TU, whereas 1 TU == 1024 us. 239 */ 240 241 /* 242 * TXRX_CSR0: Security control register. 243 */ 244 #define TXRX_CSR0 0x0440 245 #define TXRX_CSR0_ALGORITHM FIELD16(0x0007) 246 #define TXRX_CSR0_IV_OFFSET FIELD16(0x01f8) 247 #define TXRX_CSR0_KEY_ID FIELD16(0x1e00) 248 249 /* 250 * TXRX_CSR1: TX configuration. 251 * ACK_TIMEOUT: ACK Timeout in unit of 1-us. 252 * TSF_OFFSET: TSF offset in MAC header. 253 * AUTO_SEQUENCE: Let ASIC control frame sequence number. 254 */ 255 #define TXRX_CSR1 0x0442 256 #define TXRX_CSR1_ACK_TIMEOUT FIELD16(0x00ff) 257 #define TXRX_CSR1_TSF_OFFSET FIELD16(0x7f00) 258 #define TXRX_CSR1_AUTO_SEQUENCE FIELD16(0x8000) 259 260 /* 261 * TXRX_CSR2: RX control. 262 * DISABLE_RX: Disable rx engine. 263 * DROP_CRC: Drop crc error. 264 * DROP_PHYSICAL: Drop physical error. 265 * DROP_CONTROL: Drop control frame. 266 * DROP_NOT_TO_ME: Drop not to me unicast frame. 267 * DROP_TODS: Drop frame tods bit is true. 268 * DROP_VERSION_ERROR: Drop version error frame. 269 * DROP_MCAST: Drop multicast frames. 270 * DROP_BCAST: Drop broadcast frames. 271 */ 272 #define TXRX_CSR2 0x0444 273 #define TXRX_CSR2_DISABLE_RX FIELD16(0x0001) 274 #define TXRX_CSR2_DROP_CRC FIELD16(0x0002) 275 #define TXRX_CSR2_DROP_PHYSICAL FIELD16(0x0004) 276 #define TXRX_CSR2_DROP_CONTROL FIELD16(0x0008) 277 #define TXRX_CSR2_DROP_NOT_TO_ME FIELD16(0x0010) 278 #define TXRX_CSR2_DROP_TODS FIELD16(0x0020) 279 #define TXRX_CSR2_DROP_VERSION_ERROR FIELD16(0x0040) 280 #define TXRX_CSR2_DROP_MULTICAST FIELD16(0x0200) 281 #define TXRX_CSR2_DROP_BROADCAST FIELD16(0x0400) 282 283 /* 284 * RX BBP ID registers 285 * TXRX_CSR3: CCK RX BBP ID. 286 * TXRX_CSR4: OFDM RX BBP ID. 287 */ 288 #define TXRX_CSR3 0x0446 289 #define TXRX_CSR4 0x0448 290 291 /* 292 * TXRX_CSR5: CCK TX BBP ID0. 293 */ 294 #define TXRX_CSR5 0x044a 295 #define TXRX_CSR5_BBP_ID0 FIELD16(0x007f) 296 #define TXRX_CSR5_BBP_ID0_VALID FIELD16(0x0080) 297 #define TXRX_CSR5_BBP_ID1 FIELD16(0x7f00) 298 #define TXRX_CSR5_BBP_ID1_VALID FIELD16(0x8000) 299 300 /* 301 * TXRX_CSR6: CCK TX BBP ID1. 302 */ 303 #define TXRX_CSR6 0x044c 304 #define TXRX_CSR6_BBP_ID0 FIELD16(0x007f) 305 #define TXRX_CSR6_BBP_ID0_VALID FIELD16(0x0080) 306 #define TXRX_CSR6_BBP_ID1 FIELD16(0x7f00) 307 #define TXRX_CSR6_BBP_ID1_VALID FIELD16(0x8000) 308 309 /* 310 * TXRX_CSR7: OFDM TX BBP ID0. 311 */ 312 #define TXRX_CSR7 0x044e 313 #define TXRX_CSR7_BBP_ID0 FIELD16(0x007f) 314 #define TXRX_CSR7_BBP_ID0_VALID FIELD16(0x0080) 315 #define TXRX_CSR7_BBP_ID1 FIELD16(0x7f00) 316 #define TXRX_CSR7_BBP_ID1_VALID FIELD16(0x8000) 317 318 /* 319 * TXRX_CSR8: OFDM TX BBP ID1. 320 */ 321 #define TXRX_CSR8 0x0450 322 #define TXRX_CSR8_BBP_ID0 FIELD16(0x007f) 323 #define TXRX_CSR8_BBP_ID0_VALID FIELD16(0x0080) 324 #define TXRX_CSR8_BBP_ID1 FIELD16(0x7f00) 325 #define TXRX_CSR8_BBP_ID1_VALID FIELD16(0x8000) 326 327 /* 328 * TXRX_CSR9: TX ACK time-out. 329 */ 330 #define TXRX_CSR9 0x0452 331 332 /* 333 * TXRX_CSR10: Auto responder control. 334 */ 335 #define TXRX_CSR10 0x0454 336 #define TXRX_CSR10_AUTORESPOND_PREAMBLE FIELD16(0x0004) 337 338 /* 339 * TXRX_CSR11: Auto responder basic rate. 340 */ 341 #define TXRX_CSR11 0x0456 342 343 /* 344 * ACK/CTS time registers. 345 */ 346 #define TXRX_CSR12 0x0458 347 #define TXRX_CSR13 0x045a 348 #define TXRX_CSR14 0x045c 349 #define TXRX_CSR15 0x045e 350 #define TXRX_CSR16 0x0460 351 #define TXRX_CSR17 0x0462 352 353 /* 354 * TXRX_CSR18: Synchronization control register. 355 */ 356 #define TXRX_CSR18 0x0464 357 #define TXRX_CSR18_OFFSET FIELD16(0x000f) 358 #define TXRX_CSR18_INTERVAL FIELD16(0xfff0) 359 360 /* 361 * TXRX_CSR19: Synchronization control register. 362 * TSF_COUNT: Enable TSF auto counting. 363 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode. 364 * TBCN: Enable Tbcn with reload value. 365 * BEACON_GEN: Enable beacon generator. 366 */ 367 #define TXRX_CSR19 0x0466 368 #define TXRX_CSR19_TSF_COUNT FIELD16(0x0001) 369 #define TXRX_CSR19_TSF_SYNC FIELD16(0x0006) 370 #define TXRX_CSR19_TBCN FIELD16(0x0008) 371 #define TXRX_CSR19_BEACON_GEN FIELD16(0x0010) 372 373 /* 374 * TXRX_CSR20: Tx BEACON offset time control register. 375 * OFFSET: In units of usec. 376 * BCN_EXPECT_WINDOW: Default: 2^CWmin 377 */ 378 #define TXRX_CSR20 0x0468 379 #define TXRX_CSR20_OFFSET FIELD16(0x1fff) 380 #define TXRX_CSR20_BCN_EXPECT_WINDOW FIELD16(0xe000) 381 382 /* 383 * TXRX_CSR21 384 */ 385 #define TXRX_CSR21 0x046a 386 387 /* 388 * Encryption related CSRs. 389 * 390 */ 391 392 /* 393 * SEC_CSR0: Shared key 0, word 0 394 * SEC_CSR1: Shared key 0, word 1 395 * SEC_CSR2: Shared key 0, word 2 396 * SEC_CSR3: Shared key 0, word 3 397 * SEC_CSR4: Shared key 0, word 4 398 * SEC_CSR5: Shared key 0, word 5 399 * SEC_CSR6: Shared key 0, word 6 400 * SEC_CSR7: Shared key 0, word 7 401 */ 402 #define SEC_CSR0 0x0480 403 #define SEC_CSR1 0x0482 404 #define SEC_CSR2 0x0484 405 #define SEC_CSR3 0x0486 406 #define SEC_CSR4 0x0488 407 #define SEC_CSR5 0x048a 408 #define SEC_CSR6 0x048c 409 #define SEC_CSR7 0x048e 410 411 /* 412 * SEC_CSR8: Shared key 1, word 0 413 * SEC_CSR9: Shared key 1, word 1 414 * SEC_CSR10: Shared key 1, word 2 415 * SEC_CSR11: Shared key 1, word 3 416 * SEC_CSR12: Shared key 1, word 4 417 * SEC_CSR13: Shared key 1, word 5 418 * SEC_CSR14: Shared key 1, word 6 419 * SEC_CSR15: Shared key 1, word 7 420 */ 421 #define SEC_CSR8 0x0490 422 #define SEC_CSR9 0x0492 423 #define SEC_CSR10 0x0494 424 #define SEC_CSR11 0x0496 425 #define SEC_CSR12 0x0498 426 #define SEC_CSR13 0x049a 427 #define SEC_CSR14 0x049c 428 #define SEC_CSR15 0x049e 429 430 /* 431 * SEC_CSR16: Shared key 2, word 0 432 * SEC_CSR17: Shared key 2, word 1 433 * SEC_CSR18: Shared key 2, word 2 434 * SEC_CSR19: Shared key 2, word 3 435 * SEC_CSR20: Shared key 2, word 4 436 * SEC_CSR21: Shared key 2, word 5 437 * SEC_CSR22: Shared key 2, word 6 438 * SEC_CSR23: Shared key 2, word 7 439 */ 440 #define SEC_CSR16 0x04a0 441 #define SEC_CSR17 0x04a2 442 #define SEC_CSR18 0X04A4 443 #define SEC_CSR19 0x04a6 444 #define SEC_CSR20 0x04a8 445 #define SEC_CSR21 0x04aa 446 #define SEC_CSR22 0x04ac 447 #define SEC_CSR23 0x04ae 448 449 /* 450 * SEC_CSR24: Shared key 3, word 0 451 * SEC_CSR25: Shared key 3, word 1 452 * SEC_CSR26: Shared key 3, word 2 453 * SEC_CSR27: Shared key 3, word 3 454 * SEC_CSR28: Shared key 3, word 4 455 * SEC_CSR29: Shared key 3, word 5 456 * SEC_CSR30: Shared key 3, word 6 457 * SEC_CSR31: Shared key 3, word 7 458 */ 459 #define SEC_CSR24 0x04b0 460 #define SEC_CSR25 0x04b2 461 #define SEC_CSR26 0x04b4 462 #define SEC_CSR27 0x04b6 463 #define SEC_CSR28 0x04b8 464 #define SEC_CSR29 0x04ba 465 #define SEC_CSR30 0x04bc 466 #define SEC_CSR31 0x04be 467 468 #define KEY_ENTRY(__idx) \ 469 ( SEC_CSR0 + ((__idx) * 16) ) 470 471 /* 472 * PHY control registers. 473 */ 474 475 /* 476 * PHY_CSR0: RF switching timing control. 477 */ 478 #define PHY_CSR0 0x04c0 479 480 /* 481 * PHY_CSR1: TX PA configuration. 482 */ 483 #define PHY_CSR1 0x04c2 484 485 /* 486 * MAC configuration registers. 487 */ 488 489 /* 490 * PHY_CSR2: TX MAC configuration. 491 * NOTE: Both register fields are complete dummy, 492 * documentation and legacy drivers are unclear un 493 * what this register means or what fields exists. 494 */ 495 #define PHY_CSR2 0x04c4 496 #define PHY_CSR2_LNA FIELD16(0x0002) 497 #define PHY_CSR2_LNA_MODE FIELD16(0x3000) 498 499 /* 500 * PHY_CSR3: RX MAC configuration. 501 */ 502 #define PHY_CSR3 0x04c6 503 504 /* 505 * PHY_CSR4: Interface configuration. 506 */ 507 #define PHY_CSR4 0x04c8 508 #define PHY_CSR4_LOW_RF_LE FIELD16(0x0001) 509 510 /* 511 * BBP pre-TX registers. 512 * PHY_CSR5: BBP pre-TX CCK. 513 */ 514 #define PHY_CSR5 0x04ca 515 #define PHY_CSR5_CCK FIELD16(0x0003) 516 #define PHY_CSR5_CCK_FLIP FIELD16(0x0004) 517 518 /* 519 * BBP pre-TX registers. 520 * PHY_CSR6: BBP pre-TX OFDM. 521 */ 522 #define PHY_CSR6 0x04cc 523 #define PHY_CSR6_OFDM FIELD16(0x0003) 524 #define PHY_CSR6_OFDM_FLIP FIELD16(0x0004) 525 526 /* 527 * PHY_CSR7: BBP access register 0. 528 * BBP_DATA: BBP data. 529 * BBP_REG_ID: BBP register ID. 530 * BBP_READ_CONTROL: 0: write, 1: read. 531 */ 532 #define PHY_CSR7 0x04ce 533 #define PHY_CSR7_DATA FIELD16(0x00ff) 534 #define PHY_CSR7_REG_ID FIELD16(0x7f00) 535 #define PHY_CSR7_READ_CONTROL FIELD16(0x8000) 536 537 /* 538 * PHY_CSR8: BBP access register 1. 539 * BBP_BUSY: ASIC is busy execute BBP programming. 540 */ 541 #define PHY_CSR8 0x04d0 542 #define PHY_CSR8_BUSY FIELD16(0x0001) 543 544 /* 545 * PHY_CSR9: RF access register. 546 * RF_VALUE: Register value + id to program into rf/if. 547 */ 548 #define PHY_CSR9 0x04d2 549 #define PHY_CSR9_RF_VALUE FIELD16(0xffff) 550 551 /* 552 * PHY_CSR10: RF access register. 553 * RF_VALUE: Register value + id to program into rf/if. 554 * RF_NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22). 555 * RF_IF_SELECT: Chip to program: 0: rf, 1: if. 556 * RF_PLL_LD: Rf pll_ld status. 557 * RF_BUSY: 1: asic is busy execute rf programming. 558 */ 559 #define PHY_CSR10 0x04d4 560 #define PHY_CSR10_RF_VALUE FIELD16(0x00ff) 561 #define PHY_CSR10_RF_NUMBER_OF_BITS FIELD16(0x1f00) 562 #define PHY_CSR10_RF_IF_SELECT FIELD16(0x2000) 563 #define PHY_CSR10_RF_PLL_LD FIELD16(0x4000) 564 #define PHY_CSR10_RF_BUSY FIELD16(0x8000) 565 566 /* 567 * STA_CSR0: FCS error count. 568 * FCS_ERROR: FCS error count, cleared when read. 569 */ 570 #define STA_CSR0 0x04e0 571 #define STA_CSR0_FCS_ERROR FIELD16(0xffff) 572 573 /* 574 * STA_CSR1: PLCP error count. 575 */ 576 #define STA_CSR1 0x04e2 577 578 /* 579 * STA_CSR2: LONG error count. 580 */ 581 #define STA_CSR2 0x04e4 582 583 /* 584 * STA_CSR3: CCA false alarm. 585 * FALSE_CCA_ERROR: False CCA error count, cleared when read. 586 */ 587 #define STA_CSR3 0x04e6 588 #define STA_CSR3_FALSE_CCA_ERROR FIELD16(0xffff) 589 590 /* 591 * STA_CSR4: RX FIFO overflow. 592 */ 593 #define STA_CSR4 0x04e8 594 595 /* 596 * STA_CSR5: Beacon sent counter. 597 */ 598 #define STA_CSR5 0x04ea 599 600 /* 601 * Statistics registers 602 */ 603 #define STA_CSR6 0x04ec 604 #define STA_CSR7 0x04ee 605 #define STA_CSR8 0x04f0 606 #define STA_CSR9 0x04f2 607 #define STA_CSR10 0x04f4 608 609 /* 610 * BBP registers. 611 * The wordsize of the BBP is 8 bits. 612 */ 613 614 /* 615 * R2: TX antenna control 616 */ 617 #define BBP_R2_TX_ANTENNA FIELD8(0x03) 618 #define BBP_R2_TX_IQ_FLIP FIELD8(0x04) 619 620 /* 621 * R14: RX antenna control 622 */ 623 #define BBP_R14_RX_ANTENNA FIELD8(0x03) 624 #define BBP_R14_RX_IQ_FLIP FIELD8(0x04) 625 626 /* 627 * RF registers. 628 */ 629 630 /* 631 * RF 1 632 */ 633 #define RF1_TUNER FIELD32(0x00020000) 634 635 /* 636 * RF 3 637 */ 638 #define RF3_TUNER FIELD32(0x00000100) 639 #define RF3_TXPOWER FIELD32(0x00003e00) 640 641 /* 642 * EEPROM contents. 643 */ 644 645 /* 646 * HW MAC address. 647 */ 648 #define EEPROM_MAC_ADDR_0 0x0002 649 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff) 650 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00) 651 #define EEPROM_MAC_ADDR1 0x0003 652 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff) 653 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00) 654 #define EEPROM_MAC_ADDR_2 0x0004 655 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff) 656 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00) 657 658 /* 659 * EEPROM antenna. 660 * ANTENNA_NUM: Number of antenna's. 661 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. 662 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. 663 * LED_MODE: 0: default, 1: TX/RX activity, 2: Single (ignore link), 3: rsvd. 664 * DYN_TXAGC: Dynamic TX AGC control. 665 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0. 666 * RF_TYPE: Rf_type of this adapter. 667 */ 668 #define EEPROM_ANTENNA 0x000b 669 #define EEPROM_ANTENNA_NUM FIELD16(0x0003) 670 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c) 671 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030) 672 #define EEPROM_ANTENNA_LED_MODE FIELD16(0x01c0) 673 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200) 674 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400) 675 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800) 676 677 /* 678 * EEPROM NIC config. 679 * CARDBUS_ACCEL: 0: enable, 1: disable. 680 * DYN_BBP_TUNE: 0: enable, 1: disable. 681 * CCK_TX_POWER: CCK TX power compensation. 682 */ 683 #define EEPROM_NIC 0x000c 684 #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0001) 685 #define EEPROM_NIC_DYN_BBP_TUNE FIELD16(0x0002) 686 #define EEPROM_NIC_CCK_TX_POWER FIELD16(0x000c) 687 688 /* 689 * EEPROM geography. 690 * GEO: Default geography setting for device. 691 */ 692 #define EEPROM_GEOGRAPHY 0x000d 693 #define EEPROM_GEOGRAPHY_GEO FIELD16(0x0f00) 694 695 /* 696 * EEPROM BBP. 697 */ 698 #define EEPROM_BBP_START 0x000e 699 #define EEPROM_BBP_SIZE 16 700 #define EEPROM_BBP_VALUE FIELD16(0x00ff) 701 #define EEPROM_BBP_REG_ID FIELD16(0xff00) 702 703 /* 704 * EEPROM TXPOWER 705 */ 706 #define EEPROM_TXPOWER_START 0x001e 707 #define EEPROM_TXPOWER_SIZE 7 708 #define EEPROM_TXPOWER_1 FIELD16(0x00ff) 709 #define EEPROM_TXPOWER_2 FIELD16(0xff00) 710 711 /* 712 * EEPROM Tuning threshold 713 */ 714 #define EEPROM_BBPTUNE 0x0030 715 #define EEPROM_BBPTUNE_THRESHOLD FIELD16(0x00ff) 716 717 /* 718 * EEPROM BBP R24 Tuning. 719 */ 720 #define EEPROM_BBPTUNE_R24 0x0031 721 #define EEPROM_BBPTUNE_R24_LOW FIELD16(0x00ff) 722 #define EEPROM_BBPTUNE_R24_HIGH FIELD16(0xff00) 723 724 /* 725 * EEPROM BBP R25 Tuning. 726 */ 727 #define EEPROM_BBPTUNE_R25 0x0032 728 #define EEPROM_BBPTUNE_R25_LOW FIELD16(0x00ff) 729 #define EEPROM_BBPTUNE_R25_HIGH FIELD16(0xff00) 730 731 /* 732 * EEPROM BBP R24 Tuning. 733 */ 734 #define EEPROM_BBPTUNE_R61 0x0033 735 #define EEPROM_BBPTUNE_R61_LOW FIELD16(0x00ff) 736 #define EEPROM_BBPTUNE_R61_HIGH FIELD16(0xff00) 737 738 /* 739 * EEPROM BBP VGC Tuning. 740 */ 741 #define EEPROM_BBPTUNE_VGC 0x0034 742 #define EEPROM_BBPTUNE_VGCUPPER FIELD16(0x00ff) 743 #define EEPROM_BBPTUNE_VGCLOWER FIELD16(0xff00) 744 745 /* 746 * EEPROM BBP R17 Tuning. 747 */ 748 #define EEPROM_BBPTUNE_R17 0x0035 749 #define EEPROM_BBPTUNE_R17_LOW FIELD16(0x00ff) 750 #define EEPROM_BBPTUNE_R17_HIGH FIELD16(0xff00) 751 752 /* 753 * RSSI <-> dBm offset calibration 754 */ 755 #define EEPROM_CALIBRATE_OFFSET 0x0036 756 #define EEPROM_CALIBRATE_OFFSET_RSSI FIELD16(0x00ff) 757 758 /* 759 * DMA descriptor defines. 760 */ 761 #define TXD_DESC_SIZE ( 5 * sizeof(__le32) ) 762 #define RXD_DESC_SIZE ( 4 * sizeof(__le32) ) 763 764 /* 765 * TX descriptor format for TX, PRIO, ATIM and Beacon Ring. 766 */ 767 768 /* 769 * Word0 770 */ 771 #define TXD_W0_PACKET_ID FIELD32(0x0000000f) 772 #define TXD_W0_RETRY_LIMIT FIELD32(0x000000f0) 773 #define TXD_W0_MORE_FRAG FIELD32(0x00000100) 774 #define TXD_W0_ACK FIELD32(0x00000200) 775 #define TXD_W0_TIMESTAMP FIELD32(0x00000400) 776 #define TXD_W0_OFDM FIELD32(0x00000800) 777 #define TXD_W0_NEW_SEQ FIELD32(0x00001000) 778 #define TXD_W0_IFS FIELD32(0x00006000) 779 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000) 780 #define TXD_W0_CIPHER FIELD32(0x20000000) 781 #define TXD_W0_KEY_ID FIELD32(0xc0000000) 782 783 /* 784 * Word1 785 */ 786 #define TXD_W1_IV_OFFSET FIELD32(0x0000003f) 787 #define TXD_W1_AIFS FIELD32(0x000000c0) 788 #define TXD_W1_CWMIN FIELD32(0x00000f00) 789 #define TXD_W1_CWMAX FIELD32(0x0000f000) 790 791 /* 792 * Word2: PLCP information 793 */ 794 #define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff) 795 #define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00) 796 #define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000) 797 #define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000) 798 799 /* 800 * Word3 801 */ 802 #define TXD_W3_IV FIELD32(0xffffffff) 803 804 /* 805 * Word4 806 */ 807 #define TXD_W4_EIV FIELD32(0xffffffff) 808 809 /* 810 * RX descriptor format for RX Ring. 811 */ 812 813 /* 814 * Word0 815 */ 816 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002) 817 #define RXD_W0_MULTICAST FIELD32(0x00000004) 818 #define RXD_W0_BROADCAST FIELD32(0x00000008) 819 #define RXD_W0_MY_BSS FIELD32(0x00000010) 820 #define RXD_W0_CRC_ERROR FIELD32(0x00000020) 821 #define RXD_W0_OFDM FIELD32(0x00000040) 822 #define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080) 823 #define RXD_W0_CIPHER FIELD32(0x00000100) 824 #define RXD_W0_CIPHER_ERROR FIELD32(0x00000200) 825 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000) 826 827 /* 828 * Word1 829 */ 830 #define RXD_W1_RSSI FIELD32(0x000000ff) 831 #define RXD_W1_SIGNAL FIELD32(0x0000ff00) 832 833 /* 834 * Word2 835 */ 836 #define RXD_W2_IV FIELD32(0xffffffff) 837 838 /* 839 * Word3 840 */ 841 #define RXD_W3_EIV FIELD32(0xffffffff) 842 843 /* 844 * Macros for converting txpower from EEPROM to mac80211 value 845 * and from mac80211 value to register value. 846 */ 847 #define MIN_TXPOWER 0 848 #define MAX_TXPOWER 31 849 #define DEFAULT_TXPOWER 24 850 851 #define TXPOWER_FROM_DEV(__txpower) \ 852 (((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower) 853 854 #define TXPOWER_TO_DEV(__txpower) \ 855 clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER) 856 857 #endif /* RT2500USB_H */ 858