1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #ifndef __RTL_PCI_H__
31 #define __RTL_PCI_H__
32
33 #include <linux/pci.h>
34 /*
35 1: MSDU packet queue,
36 2: Rx Command Queue
37 */
38 #define RTL_PCI_RX_MPDU_QUEUE 0
39 #define RTL_PCI_RX_CMD_QUEUE 1
40 #define RTL_PCI_MAX_RX_QUEUE 2
41
42 #define RTL_PCI_MAX_RX_COUNT 64
43 #define RTL_PCI_MAX_TX_QUEUE_COUNT 9
44
45 #define RT_TXDESC_NUM 128
46 #define RT_TXDESC_NUM_BE_QUEUE 256
47
48 #define BK_QUEUE 0
49 #define BE_QUEUE 1
50 #define VI_QUEUE 2
51 #define VO_QUEUE 3
52 #define BEACON_QUEUE 4
53 #define TXCMD_QUEUE 5
54 #define MGNT_QUEUE 6
55 #define HIGH_QUEUE 7
56 #define HCCA_QUEUE 8
57
58 #define RTL_PCI_DEVICE(vend, dev, cfg) \
59 .vendor = (vend), \
60 .device = (dev), \
61 .subvendor = PCI_ANY_ID, \
62 .subdevice = PCI_ANY_ID,\
63 .driver_data = (kernel_ulong_t)&(cfg)
64
65 #define PCI_MAX_BRIDGE_NUMBER 255
66 #define PCI_MAX_DEVICES 32
67 #define PCI_MAX_FUNCTION 8
68
69 #define PCI_CONF_ADDRESS 0x0CF8 /*PCI Configuration Space Address */
70 #define PCI_CONF_DATA 0x0CFC /*PCI Configuration Space Data */
71
72 #define U1DONTCARE 0xFF
73 #define U2DONTCARE 0xFFFF
74 #define U4DONTCARE 0xFFFFFFFF
75
76 #define RTL_PCI_8192_DID 0x8192 /*8192 PCI-E */
77 #define RTL_PCI_8192SE_DID 0x8192 /*8192 SE */
78 #define RTL_PCI_8174_DID 0x8174 /*8192 SE */
79 #define RTL_PCI_8173_DID 0x8173 /*8191 SE Crab */
80 #define RTL_PCI_8172_DID 0x8172 /*8191 SE RE */
81 #define RTL_PCI_8171_DID 0x8171 /*8191 SE Unicron */
82 #define RTL_PCI_8723AE_DID 0x8723 /*8723AE */
83 #define RTL_PCI_0045_DID 0x0045 /*8190 PCI for Ceraga */
84 #define RTL_PCI_0046_DID 0x0046 /*8190 Cardbus for Ceraga */
85 #define RTL_PCI_0044_DID 0x0044 /*8192e PCIE for Ceraga */
86 #define RTL_PCI_0047_DID 0x0047 /*8192e Express Card for Ceraga */
87 #define RTL_PCI_700F_DID 0x700F
88 #define RTL_PCI_701F_DID 0x701F
89 #define RTL_PCI_DLINK_DID 0x3304
90 #define RTL_PCI_8192CET_DID 0x8191 /*8192ce */
91 #define RTL_PCI_8192CE_DID 0x8178 /*8192ce */
92 #define RTL_PCI_8191CE_DID 0x8177 /*8192ce */
93 #define RTL_PCI_8188CE_DID 0x8176 /*8192ce */
94 #define RTL_PCI_8192CU_DID 0x8191 /*8192ce */
95 #define RTL_PCI_8192DE_DID 0x8193 /*8192de */
96 #define RTL_PCI_8192DE_DID2 0x002B /*92DE*/
97 #define RTL_PCI_8188EE_DID 0x8179 /*8188ee*/
98
99 /*8192 support 16 pages of IO registers*/
100 #define RTL_MEM_MAPPED_IO_RANGE_8190PCI 0x1000
101 #define RTL_MEM_MAPPED_IO_RANGE_8192PCIE 0x4000
102 #define RTL_MEM_MAPPED_IO_RANGE_8192SE 0x4000
103 #define RTL_MEM_MAPPED_IO_RANGE_8192CE 0x4000
104 #define RTL_MEM_MAPPED_IO_RANGE_8192DE 0x4000
105
106 #define RTL_PCI_REVISION_ID_8190PCI 0x00
107 #define RTL_PCI_REVISION_ID_8192PCIE 0x01
108 #define RTL_PCI_REVISION_ID_8192SE 0x10
109 #define RTL_PCI_REVISION_ID_8192CE 0x1
110 #define RTL_PCI_REVISION_ID_8192DE 0x0
111
112 #define RTL_DEFAULT_HARDWARE_TYPE HARDWARE_TYPE_RTL8192CE
113
114 enum pci_bridge_vendor {
115 PCI_BRIDGE_VENDOR_INTEL = 0x0, /*0b'0000,0001 */
116 PCI_BRIDGE_VENDOR_ATI, /*0b'0000,0010*/
117 PCI_BRIDGE_VENDOR_AMD, /*0b'0000,0100*/
118 PCI_BRIDGE_VENDOR_SIS, /*0b'0000,1000*/
119 PCI_BRIDGE_VENDOR_UNKNOWN, /*0b'0100,0000*/
120 PCI_BRIDGE_VENDOR_MAX,
121 };
122
123 struct rtl_pci_capabilities_header {
124 u8 capability_id;
125 u8 next;
126 };
127
128 struct rtl_rx_desc {
129 u32 dword[8];
130 } __packed;
131
132 struct rtl_tx_desc {
133 u32 dword[16];
134 } __packed;
135
136 struct rtl_tx_cmd_desc {
137 u32 dword[16];
138 } __packed;
139
140 struct rtl8192_tx_ring {
141 struct rtl_tx_desc *desc;
142 dma_addr_t dma;
143 unsigned int idx;
144 unsigned int entries;
145 struct sk_buff_head queue;
146 };
147
148 struct rtl8192_rx_ring {
149 struct rtl_rx_desc *desc;
150 dma_addr_t dma;
151 unsigned int idx;
152 struct sk_buff *rx_buf[RTL_PCI_MAX_RX_COUNT];
153 };
154
155 struct rtl_pci {
156 struct pci_dev *pdev;
157 bool irq_enabled;
158
159 bool driver_is_goingto_unload;
160 bool up_first_time;
161 bool first_init;
162 bool being_init_adapter;
163 bool init_ready;
164
165 /*Tx */
166 struct rtl8192_tx_ring tx_ring[RTL_PCI_MAX_TX_QUEUE_COUNT];
167 int txringcount[RTL_PCI_MAX_TX_QUEUE_COUNT];
168 u32 transmit_config;
169
170 /*Rx */
171 struct rtl8192_rx_ring rx_ring[RTL_PCI_MAX_RX_QUEUE];
172 int rxringcount;
173 u16 rxbuffersize;
174 u32 receive_config;
175
176 /*irq */
177 u8 irq_alloc;
178 u32 irq_mask[2];
179 u32 sys_irq_mask;
180
181 /*Bcn control register setting */
182 u32 reg_bcn_ctrl_val;
183
184 /*ASPM*/ u8 const_pci_aspm;
185 u8 const_amdpci_aspm;
186 u8 const_hwsw_rfoff_d3;
187 u8 const_support_pciaspm;
188 /*pci-e bridge */
189 u8 const_hostpci_aspm_setting;
190 /*pci-e device */
191 u8 const_devicepci_aspm_setting;
192 /*If it supports ASPM, Offset[560h] = 0x40,
193 otherwise Offset[560h] = 0x00. */
194 bool support_aspm;
195 bool support_backdoor;
196
197 /*QOS & EDCA */
198 enum acm_method acm_method;
199
200 u16 shortretry_limit;
201 u16 longretry_limit;
202 };
203
204 struct mp_adapter {
205 u8 linkctrl_reg;
206
207 u8 busnumber;
208 u8 devnumber;
209 u8 funcnumber;
210
211 u8 pcibridge_busnum;
212 u8 pcibridge_devnum;
213 u8 pcibridge_funcnum;
214
215 u8 pcibridge_vendor;
216 u16 pcibridge_vendorid;
217 u16 pcibridge_deviceid;
218
219 u8 num4bytes;
220
221 u8 pcibridge_pciehdr_offset;
222 u8 pcibridge_linkctrlreg;
223
224 bool amd_l1_patch;
225 };
226
227 struct rtl_pci_priv {
228 struct rtl_pci dev;
229 struct mp_adapter ndis_adapter;
230 struct rtl_led_ctl ledctl;
231 struct bt_coexist_info bt_coexist;
232 };
233
234 #define rtl_pcipriv(hw) (((struct rtl_pci_priv *)(rtl_priv(hw))->priv))
235 #define rtl_pcidev(pcipriv) (&((pcipriv)->dev))
236
237 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw);
238
239 extern struct rtl_intf_ops rtl_pci_ops;
240
241 int rtl_pci_probe(struct pci_dev *pdev,
242 const struct pci_device_id *id);
243 void rtl_pci_disconnect(struct pci_dev *pdev);
244 #ifdef CONFIG_PM_SLEEP
245 int rtl_pci_suspend(struct device *dev);
246 int rtl_pci_resume(struct device *dev);
247 #endif /* CONFIG_PM_SLEEP */
pci_read8_sync(struct rtl_priv * rtlpriv,u32 addr)248 static inline u8 pci_read8_sync(struct rtl_priv *rtlpriv, u32 addr)
249 {
250 return readb((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
251 }
252
pci_read16_sync(struct rtl_priv * rtlpriv,u32 addr)253 static inline u16 pci_read16_sync(struct rtl_priv *rtlpriv, u32 addr)
254 {
255 return readw((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
256 }
257
pci_read32_sync(struct rtl_priv * rtlpriv,u32 addr)258 static inline u32 pci_read32_sync(struct rtl_priv *rtlpriv, u32 addr)
259 {
260 return readl((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
261 }
262
pci_write8_async(struct rtl_priv * rtlpriv,u32 addr,u8 val)263 static inline void pci_write8_async(struct rtl_priv *rtlpriv, u32 addr, u8 val)
264 {
265 writeb(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
266 }
267
pci_write16_async(struct rtl_priv * rtlpriv,u32 addr,u16 val)268 static inline void pci_write16_async(struct rtl_priv *rtlpriv,
269 u32 addr, u16 val)
270 {
271 writew(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
272 }
273
pci_write32_async(struct rtl_priv * rtlpriv,u32 addr,u32 val)274 static inline void pci_write32_async(struct rtl_priv *rtlpriv,
275 u32 addr, u32 val)
276 {
277 writel(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
278 }
279
280 #endif
281