1 /****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * wlanfae <wlanfae@realtek.com> 23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 24 * Hsinchu 300, Taiwan. 25 * 26 * Larry Finger <Larry.Finger@lwfinger.net> 27 * 28 **************************************************************************** 29 */ 30 31 #ifndef __RTL8723E_DEF_H__ 32 #define __RTL8723E_DEF_H__ 33 34 #define HAL_PRIME_CHNL_OFFSET_LOWER 1 35 36 #define RX_MPDU_QUEUE 0 37 38 #define CHIP_8723 BIT(0) 39 #define NORMAL_CHIP BIT(3) 40 #define RF_TYPE_1T2R BIT(4) 41 #define RF_TYPE_2T2R BIT(5) 42 #define CHIP_VENDOR_UMC BIT(7) 43 #define B_CUT_VERSION BIT(12) 44 #define C_CUT_VERSION BIT(13) 45 #define D_CUT_VERSION ((BIT(12)|BIT(13))) 46 #define E_CUT_VERSION BIT(14) 47 #define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28)) 48 49 enum version_8723e { 50 VERSION_TEST_UMC_CHIP_8723 = 0x0081, 51 VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT = 0x0089, 52 VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT = 0x1089, 53 }; 54 55 /* MASK */ 56 #define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2)) 57 #define CHIP_TYPE_MASK BIT(3) 58 #define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6)) 59 #define MANUFACTUER_MASK BIT(7) 60 #define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8)) 61 #define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12)) 62 63 /* Get element */ 64 #define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK) 65 #define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK) 66 #define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK) 67 68 #define IS_81XXC(version) ((GET_CVID_IC_TYPE(version) == 0) ?\ 69 true : false) 70 #define IS_8723_SERIES(version) \ 71 ((GET_CVID_IC_TYPE(version) == CHIP_8723) ? true : false) 72 #define IS_CHIP_VENDOR_UMC(version) \ 73 ((GET_CVID_MANUFACTUER(version)) ? true : false) 74 75 #define IS_VENDOR_UMC_A_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) ? \ 76 ((GET_CVID_CUT_VERSION(version)) ? false : true) : false) 77 #define IS_VENDOR_8723_A_CUT(version) ((IS_8723_SERIES(version)) ? \ 78 ((GET_CVID_CUT_VERSION(version)) ? false : true) : false) 79 #define IS_81xxC_VENDOR_UMC_B_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) \ 80 ? ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? \ 81 true : false) : false) 82 83 enum rf_optype { 84 RF_OP_BY_SW_3WIRE = 0, 85 RF_OP_BY_FW, 86 RF_OP_MAX 87 }; 88 89 enum rf_power_state { 90 RF_ON, 91 RF_OFF, 92 RF_SLEEP, 93 RF_SHUT_DOWN, 94 }; 95 96 enum power_save_mode { 97 POWER_SAVE_MODE_ACTIVE, 98 POWER_SAVE_MODE_SAVE, 99 }; 100 101 enum power_polocy_config { 102 POWERCFG_MAX_POWER_SAVINGS, 103 POWERCFG_GLOBAL_POWER_SAVINGS, 104 POWERCFG_LOCAL_POWER_SAVINGS, 105 POWERCFG_LENOVO, 106 }; 107 108 enum interface_select_pci { 109 INTF_SEL1_MINICARD = 0, 110 INTF_SEL0_PCIE = 1, 111 INTF_SEL2_RSV = 2, 112 INTF_SEL3_RSV = 3, 113 }; 114 115 enum hal_fw_c2h_cmd_id { 116 HAL_FW_C2H_CMD_Read_MACREG = 0, 117 HAL_FW_C2H_CMD_Read_BBREG = 1, 118 HAL_FW_C2H_CMD_Read_RFREG = 2, 119 HAL_FW_C2H_CMD_Read_EEPROM = 3, 120 HAL_FW_C2H_CMD_Read_EFUSE = 4, 121 HAL_FW_C2H_CMD_Read_CAM = 5, 122 HAL_FW_C2H_CMD_Get_BasicRate = 6, 123 HAL_FW_C2H_CMD_Get_DataRate = 7, 124 HAL_FW_C2H_CMD_Survey = 8, 125 HAL_FW_C2H_CMD_SurveyDone = 9, 126 HAL_FW_C2H_CMD_JoinBss = 10, 127 HAL_FW_C2H_CMD_AddSTA = 11, 128 HAL_FW_C2H_CMD_DelSTA = 12, 129 HAL_FW_C2H_CMD_AtimDone = 13, 130 HAL_FW_C2H_CMD_TX_Report = 14, 131 HAL_FW_C2H_CMD_CCX_Report = 15, 132 HAL_FW_C2H_CMD_DTM_Report = 16, 133 HAL_FW_C2H_CMD_TX_Rate_Statistics = 17, 134 HAL_FW_C2H_CMD_C2HLBK = 18, 135 HAL_FW_C2H_CMD_C2HDBG = 19, 136 HAL_FW_C2H_CMD_C2HFEEDBACK = 20, 137 HAL_FW_C2H_CMD_MAX 138 }; 139 140 enum rtl_desc_qsel { 141 QSLT_BK = 0x2, 142 QSLT_BE = 0x0, 143 QSLT_VI = 0x5, 144 QSLT_VO = 0x7, 145 QSLT_BEACON = 0x10, 146 QSLT_HIGH = 0x11, 147 QSLT_MGNT = 0x12, 148 QSLT_CMD = 0x13, 149 }; 150 151 struct phy_sts_cck_8723e_t { 152 u8 adc_pwdb_X[4]; 153 u8 sq_rpt; 154 u8 cck_agc_rpt; 155 }; 156 157 struct h2c_cmd_8723e { 158 u8 element_id; 159 u32 cmd_len; 160 u8 *p_cmdbuffer; 161 }; 162 163 #endif 164