1 /*
2 * Generic GPIO driver for logic cells found in the Nomadik SoC
3 *
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/device.h>
17 #include <linux/platform_device.h>
18 #include <linux/io.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/irqdomain.h>
26 #include <linux/irqchip/chained_irq.h>
27 #include <linux/slab.h>
28 #include <linux/of_device.h>
29 #include <linux/of_address.h>
30 #include <linux/pinctrl/machine.h>
31 #include <linux/pinctrl/pinctrl.h>
32 #include <linux/pinctrl/pinmux.h>
33 #include <linux/pinctrl/pinconf.h>
34 /* Since we request GPIOs from ourself */
35 #include <linux/pinctrl/consumer.h>
36 #include <linux/platform_data/pinctrl-nomadik.h>
37 #include "pinctrl-nomadik.h"
38 #include "core.h"
39
40 /*
41 * The GPIO module in the Nomadik family of Systems-on-Chip is an
42 * AMBA device, managing 32 pins and alternate functions. The logic block
43 * is currently used in the Nomadik and ux500.
44 *
45 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
46 */
47
48 struct nmk_gpio_chip {
49 struct gpio_chip chip;
50 struct irq_domain *domain;
51 void __iomem *addr;
52 struct clk *clk;
53 unsigned int bank;
54 unsigned int parent_irq;
55 int secondary_parent_irq;
56 u32 (*get_secondary_status)(unsigned int bank);
57 void (*set_ioforce)(bool enable);
58 spinlock_t lock;
59 bool sleepmode;
60 /* Keep track of configured edges */
61 u32 edge_rising;
62 u32 edge_falling;
63 u32 real_wake;
64 u32 rwimsc;
65 u32 fwimsc;
66 u32 rimsc;
67 u32 fimsc;
68 u32 pull_up;
69 u32 lowemi;
70 };
71
72 /**
73 * struct nmk_pinctrl - state container for the Nomadik pin controller
74 * @dev: containing device pointer
75 * @pctl: corresponding pin controller device
76 * @soc: SoC data for this specific chip
77 * @prcm_base: PRCM register range virtual base
78 */
79 struct nmk_pinctrl {
80 struct device *dev;
81 struct pinctrl_dev *pctl;
82 const struct nmk_pinctrl_soc_data *soc;
83 void __iomem *prcm_base;
84 };
85
86 static struct nmk_gpio_chip *
87 nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
88
89 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
90
91 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
92
__nmk_gpio_set_mode(struct nmk_gpio_chip * nmk_chip,unsigned offset,int gpio_mode)93 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
94 unsigned offset, int gpio_mode)
95 {
96 u32 bit = 1 << offset;
97 u32 afunc, bfunc;
98
99 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
100 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
101 if (gpio_mode & NMK_GPIO_ALT_A)
102 afunc |= bit;
103 if (gpio_mode & NMK_GPIO_ALT_B)
104 bfunc |= bit;
105 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
106 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
107 }
108
__nmk_gpio_set_slpm(struct nmk_gpio_chip * nmk_chip,unsigned offset,enum nmk_gpio_slpm mode)109 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
110 unsigned offset, enum nmk_gpio_slpm mode)
111 {
112 u32 bit = 1 << offset;
113 u32 slpm;
114
115 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
116 if (mode == NMK_GPIO_SLPM_NOCHANGE)
117 slpm |= bit;
118 else
119 slpm &= ~bit;
120 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
121 }
122
__nmk_gpio_set_pull(struct nmk_gpio_chip * nmk_chip,unsigned offset,enum nmk_gpio_pull pull)123 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
124 unsigned offset, enum nmk_gpio_pull pull)
125 {
126 u32 bit = 1 << offset;
127 u32 pdis;
128
129 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
130 if (pull == NMK_GPIO_PULL_NONE) {
131 pdis |= bit;
132 nmk_chip->pull_up &= ~bit;
133 } else {
134 pdis &= ~bit;
135 }
136
137 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
138
139 if (pull == NMK_GPIO_PULL_UP) {
140 nmk_chip->pull_up |= bit;
141 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
142 } else if (pull == NMK_GPIO_PULL_DOWN) {
143 nmk_chip->pull_up &= ~bit;
144 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
145 }
146 }
147
__nmk_gpio_set_lowemi(struct nmk_gpio_chip * nmk_chip,unsigned offset,bool lowemi)148 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
149 unsigned offset, bool lowemi)
150 {
151 u32 bit = BIT(offset);
152 bool enabled = nmk_chip->lowemi & bit;
153
154 if (lowemi == enabled)
155 return;
156
157 if (lowemi)
158 nmk_chip->lowemi |= bit;
159 else
160 nmk_chip->lowemi &= ~bit;
161
162 writel_relaxed(nmk_chip->lowemi,
163 nmk_chip->addr + NMK_GPIO_LOWEMI);
164 }
165
__nmk_gpio_make_input(struct nmk_gpio_chip * nmk_chip,unsigned offset)166 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
167 unsigned offset)
168 {
169 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
170 }
171
__nmk_gpio_set_output(struct nmk_gpio_chip * nmk_chip,unsigned offset,int val)172 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
173 unsigned offset, int val)
174 {
175 if (val)
176 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
177 else
178 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
179 }
180
__nmk_gpio_make_output(struct nmk_gpio_chip * nmk_chip,unsigned offset,int val)181 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
182 unsigned offset, int val)
183 {
184 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
185 __nmk_gpio_set_output(nmk_chip, offset, val);
186 }
187
__nmk_gpio_set_mode_safe(struct nmk_gpio_chip * nmk_chip,unsigned offset,int gpio_mode,bool glitch)188 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
189 unsigned offset, int gpio_mode,
190 bool glitch)
191 {
192 u32 rwimsc = nmk_chip->rwimsc;
193 u32 fwimsc = nmk_chip->fwimsc;
194
195 if (glitch && nmk_chip->set_ioforce) {
196 u32 bit = BIT(offset);
197
198 /* Prevent spurious wakeups */
199 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
200 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
201
202 nmk_chip->set_ioforce(true);
203 }
204
205 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
206
207 if (glitch && nmk_chip->set_ioforce) {
208 nmk_chip->set_ioforce(false);
209
210 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
211 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
212 }
213 }
214
215 static void
nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip * nmk_chip,unsigned offset)216 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
217 {
218 u32 falling = nmk_chip->fimsc & BIT(offset);
219 u32 rising = nmk_chip->rimsc & BIT(offset);
220 int gpio = nmk_chip->chip.base + offset;
221 int irq = irq_find_mapping(nmk_chip->domain, offset);
222 struct irq_data *d = irq_get_irq_data(irq);
223
224 if (!rising && !falling)
225 return;
226
227 if (!d || !irqd_irq_disabled(d))
228 return;
229
230 if (rising) {
231 nmk_chip->rimsc &= ~BIT(offset);
232 writel_relaxed(nmk_chip->rimsc,
233 nmk_chip->addr + NMK_GPIO_RIMSC);
234 }
235
236 if (falling) {
237 nmk_chip->fimsc &= ~BIT(offset);
238 writel_relaxed(nmk_chip->fimsc,
239 nmk_chip->addr + NMK_GPIO_FIMSC);
240 }
241
242 dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
243 }
244
nmk_write_masked(void __iomem * reg,u32 mask,u32 value)245 static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value)
246 {
247 u32 val;
248
249 val = readl(reg);
250 val = ((val & ~mask) | (value & mask));
251 writel(val, reg);
252 }
253
nmk_prcm_altcx_set_mode(struct nmk_pinctrl * npct,unsigned offset,unsigned alt_num)254 static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
255 unsigned offset, unsigned alt_num)
256 {
257 int i;
258 u16 reg;
259 u8 bit;
260 u8 alt_index;
261 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
262 const u16 *gpiocr_regs;
263
264 if (!npct->prcm_base)
265 return;
266
267 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
268 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
269 alt_num);
270 return;
271 }
272
273 for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
274 if (npct->soc->altcx_pins[i].pin == offset)
275 break;
276 }
277 if (i == npct->soc->npins_altcx) {
278 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
279 offset);
280 return;
281 }
282
283 pin_desc = npct->soc->altcx_pins + i;
284 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
285
286 /*
287 * If alt_num is NULL, just clear current ALTCx selection
288 * to make sure we come back to a pure ALTC selection
289 */
290 if (!alt_num) {
291 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
292 if (pin_desc->altcx[i].used == true) {
293 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
294 bit = pin_desc->altcx[i].control_bit;
295 if (readl(npct->prcm_base + reg) & BIT(bit)) {
296 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
297 dev_dbg(npct->dev,
298 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
299 offset, i+1);
300 }
301 }
302 }
303 return;
304 }
305
306 alt_index = alt_num - 1;
307 if (pin_desc->altcx[alt_index].used == false) {
308 dev_warn(npct->dev,
309 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
310 offset, alt_num);
311 return;
312 }
313
314 /*
315 * Check if any other ALTCx functions are activated on this pin
316 * and disable it first.
317 */
318 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
319 if (i == alt_index)
320 continue;
321 if (pin_desc->altcx[i].used == true) {
322 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
323 bit = pin_desc->altcx[i].control_bit;
324 if (readl(npct->prcm_base + reg) & BIT(bit)) {
325 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
326 dev_dbg(npct->dev,
327 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
328 offset, i+1);
329 }
330 }
331 }
332
333 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
334 bit = pin_desc->altcx[alt_index].control_bit;
335 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
336 offset, alt_index+1);
337 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));
338 }
339
__nmk_config_pin(struct nmk_gpio_chip * nmk_chip,unsigned offset,pin_cfg_t cfg,bool sleep,unsigned int * slpmregs)340 static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
341 pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
342 {
343 static const char *afnames[] = {
344 [NMK_GPIO_ALT_GPIO] = "GPIO",
345 [NMK_GPIO_ALT_A] = "A",
346 [NMK_GPIO_ALT_B] = "B",
347 [NMK_GPIO_ALT_C] = "C"
348 };
349 static const char *pullnames[] = {
350 [NMK_GPIO_PULL_NONE] = "none",
351 [NMK_GPIO_PULL_UP] = "up",
352 [NMK_GPIO_PULL_DOWN] = "down",
353 [3] /* illegal */ = "??"
354 };
355 static const char *slpmnames[] = {
356 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
357 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
358 };
359
360 int pin = PIN_NUM(cfg);
361 int pull = PIN_PULL(cfg);
362 int af = PIN_ALT(cfg);
363 int slpm = PIN_SLPM(cfg);
364 int output = PIN_DIR(cfg);
365 int val = PIN_VAL(cfg);
366 bool glitch = af == NMK_GPIO_ALT_C;
367
368 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
369 pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
370 output ? "output " : "input",
371 output ? (val ? "high" : "low") : "");
372
373 if (sleep) {
374 int slpm_pull = PIN_SLPM_PULL(cfg);
375 int slpm_output = PIN_SLPM_DIR(cfg);
376 int slpm_val = PIN_SLPM_VAL(cfg);
377
378 af = NMK_GPIO_ALT_GPIO;
379
380 /*
381 * The SLPM_* values are normal values + 1 to allow zero to
382 * mean "same as normal".
383 */
384 if (slpm_pull)
385 pull = slpm_pull - 1;
386 if (slpm_output)
387 output = slpm_output - 1;
388 if (slpm_val)
389 val = slpm_val - 1;
390
391 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
392 pin,
393 slpm_pull ? pullnames[pull] : "same",
394 slpm_output ? (output ? "output" : "input") : "same",
395 slpm_val ? (val ? "high" : "low") : "same");
396 }
397
398 if (output)
399 __nmk_gpio_make_output(nmk_chip, offset, val);
400 else {
401 __nmk_gpio_make_input(nmk_chip, offset);
402 __nmk_gpio_set_pull(nmk_chip, offset, pull);
403 }
404
405 __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg));
406
407 /*
408 * If the pin is switching to altfunc, and there was an interrupt
409 * installed on it which has been lazy disabled, actually mask the
410 * interrupt to prevent spurious interrupts that would occur while the
411 * pin is under control of the peripheral. Only SKE does this.
412 */
413 if (af != NMK_GPIO_ALT_GPIO)
414 nmk_gpio_disable_lazy_irq(nmk_chip, offset);
415
416 /*
417 * If we've backed up the SLPM registers (glitch workaround), modify
418 * the backups since they will be restored.
419 */
420 if (slpmregs) {
421 if (slpm == NMK_GPIO_SLPM_NOCHANGE)
422 slpmregs[nmk_chip->bank] |= BIT(offset);
423 else
424 slpmregs[nmk_chip->bank] &= ~BIT(offset);
425 } else
426 __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
427
428 __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
429 }
430
431 /*
432 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
433 * - Save SLPM registers
434 * - Set SLPM=0 for the IOs you want to switch and others to 1
435 * - Configure the GPIO registers for the IOs that are being switched
436 * - Set IOFORCE=1
437 * - Modify the AFLSA/B registers for the IOs that are being switched
438 * - Set IOFORCE=0
439 * - Restore SLPM registers
440 * - Any spurious wake up event during switch sequence to be ignored and
441 * cleared
442 */
nmk_gpio_glitch_slpm_init(unsigned int * slpm)443 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
444 {
445 int i;
446
447 for (i = 0; i < NUM_BANKS; i++) {
448 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
449 unsigned int temp = slpm[i];
450
451 if (!chip)
452 break;
453
454 clk_enable(chip->clk);
455
456 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
457 writel(temp, chip->addr + NMK_GPIO_SLPC);
458 }
459 }
460
nmk_gpio_glitch_slpm_restore(unsigned int * slpm)461 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
462 {
463 int i;
464
465 for (i = 0; i < NUM_BANKS; i++) {
466 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
467
468 if (!chip)
469 break;
470
471 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
472
473 clk_disable(chip->clk);
474 }
475 }
476
__nmk_config_pins(pin_cfg_t * cfgs,int num,bool sleep)477 static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
478 {
479 static unsigned int slpm[NUM_BANKS];
480 unsigned long flags;
481 bool glitch = false;
482 int ret = 0;
483 int i;
484
485 for (i = 0; i < num; i++) {
486 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
487 glitch = true;
488 break;
489 }
490 }
491
492 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
493
494 if (glitch) {
495 memset(slpm, 0xff, sizeof(slpm));
496
497 for (i = 0; i < num; i++) {
498 int pin = PIN_NUM(cfgs[i]);
499 int offset = pin % NMK_GPIO_PER_CHIP;
500
501 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
502 slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
503 }
504
505 nmk_gpio_glitch_slpm_init(slpm);
506 }
507
508 for (i = 0; i < num; i++) {
509 struct nmk_gpio_chip *nmk_chip;
510 int pin = PIN_NUM(cfgs[i]);
511
512 nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP];
513 if (!nmk_chip) {
514 ret = -EINVAL;
515 break;
516 }
517
518 clk_enable(nmk_chip->clk);
519 spin_lock(&nmk_chip->lock);
520 __nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP,
521 cfgs[i], sleep, glitch ? slpm : NULL);
522 spin_unlock(&nmk_chip->lock);
523 clk_disable(nmk_chip->clk);
524 }
525
526 if (glitch)
527 nmk_gpio_glitch_slpm_restore(slpm);
528
529 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
530
531 return ret;
532 }
533
534 /**
535 * nmk_config_pin - configure a pin's mux attributes
536 * @cfg: pin confguration
537 * @sleep: Non-zero to apply the sleep mode configuration
538 * Configures a pin's mode (alternate function or GPIO), its pull up status,
539 * and its sleep mode based on the specified configuration. The @cfg is
540 * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
541 * are constructed using, and can be further enhanced with, the macros in
542 * <linux/platform_data/pinctrl-nomadik.h>
543 *
544 * If a pin's mode is set to GPIO, it is configured as an input to avoid
545 * side-effects. The gpio can be manipulated later using standard GPIO API
546 * calls.
547 */
nmk_config_pin(pin_cfg_t cfg,bool sleep)548 int nmk_config_pin(pin_cfg_t cfg, bool sleep)
549 {
550 return __nmk_config_pins(&cfg, 1, sleep);
551 }
552 EXPORT_SYMBOL(nmk_config_pin);
553
554 /**
555 * nmk_config_pins - configure several pins at once
556 * @cfgs: array of pin configurations
557 * @num: number of elments in the array
558 *
559 * Configures several pins using nmk_config_pin(). Refer to that function for
560 * further information.
561 */
nmk_config_pins(pin_cfg_t * cfgs,int num)562 int nmk_config_pins(pin_cfg_t *cfgs, int num)
563 {
564 return __nmk_config_pins(cfgs, num, false);
565 }
566 EXPORT_SYMBOL(nmk_config_pins);
567
nmk_config_pins_sleep(pin_cfg_t * cfgs,int num)568 int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
569 {
570 return __nmk_config_pins(cfgs, num, true);
571 }
572 EXPORT_SYMBOL(nmk_config_pins_sleep);
573
574 /**
575 * nmk_gpio_set_slpm() - configure the sleep mode of a pin
576 * @gpio: pin number
577 * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
578 *
579 * This register is actually in the pinmux layer, not the GPIO block itself.
580 * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP
581 * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code).
582 * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is
583 * HIGH, overriding the normal setting defined by GPIO_AFSELx registers.
584 * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit),
585 * the GPIOs return to the normal setting defined by GPIO_AFSELx registers.
586 *
587 * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO
588 * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is
589 * entered) regardless of the altfunction selected. Also wake-up detection is
590 * ENABLED.
591 *
592 * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains
593 * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS
594 * (for altfunction GPIO) or respective on-chip peripherals (for other
595 * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED.
596 *
597 * Note that enable_irq_wake() will automatically enable wakeup detection.
598 */
nmk_gpio_set_slpm(int gpio,enum nmk_gpio_slpm mode)599 int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
600 {
601 struct nmk_gpio_chip *nmk_chip;
602 unsigned long flags;
603
604 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
605 if (!nmk_chip)
606 return -EINVAL;
607
608 clk_enable(nmk_chip->clk);
609 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
610 spin_lock(&nmk_chip->lock);
611
612 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode);
613
614 spin_unlock(&nmk_chip->lock);
615 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
616 clk_disable(nmk_chip->clk);
617
618 return 0;
619 }
620
621 /**
622 * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
623 * @gpio: pin number
624 * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
625 *
626 * Enables/disables pull up/down on a specified pin. This only takes effect if
627 * the pin is configured as an input (either explicitly or by the alternate
628 * function).
629 *
630 * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
631 * configured as an input. Otherwise, due to the way the controller registers
632 * work, this function will change the value output on the pin.
633 */
nmk_gpio_set_pull(int gpio,enum nmk_gpio_pull pull)634 int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
635 {
636 struct nmk_gpio_chip *nmk_chip;
637 unsigned long flags;
638
639 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
640 if (!nmk_chip)
641 return -EINVAL;
642
643 clk_enable(nmk_chip->clk);
644 spin_lock_irqsave(&nmk_chip->lock, flags);
645 __nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull);
646 spin_unlock_irqrestore(&nmk_chip->lock, flags);
647 clk_disable(nmk_chip->clk);
648
649 return 0;
650 }
651
652 /* Mode functions */
653 /**
654 * nmk_gpio_set_mode() - set the mux mode of a gpio pin
655 * @gpio: pin number
656 * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
657 * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
658 *
659 * Sets the mode of the specified pin to one of the alternate functions or
660 * plain GPIO.
661 */
nmk_gpio_set_mode(int gpio,int gpio_mode)662 int nmk_gpio_set_mode(int gpio, int gpio_mode)
663 {
664 struct nmk_gpio_chip *nmk_chip;
665 unsigned long flags;
666
667 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
668 if (!nmk_chip)
669 return -EINVAL;
670
671 clk_enable(nmk_chip->clk);
672 spin_lock_irqsave(&nmk_chip->lock, flags);
673 __nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode);
674 spin_unlock_irqrestore(&nmk_chip->lock, flags);
675 clk_disable(nmk_chip->clk);
676
677 return 0;
678 }
679 EXPORT_SYMBOL(nmk_gpio_set_mode);
680
nmk_prcm_gpiocr_get_mode(struct pinctrl_dev * pctldev,int gpio)681 static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
682 {
683 int i;
684 u16 reg;
685 u8 bit;
686 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
687 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
688 const u16 *gpiocr_regs;
689
690 if (!npct->prcm_base)
691 return NMK_GPIO_ALT_C;
692
693 for (i = 0; i < npct->soc->npins_altcx; i++) {
694 if (npct->soc->altcx_pins[i].pin == gpio)
695 break;
696 }
697 if (i == npct->soc->npins_altcx)
698 return NMK_GPIO_ALT_C;
699
700 pin_desc = npct->soc->altcx_pins + i;
701 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
702 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) {
703 if (pin_desc->altcx[i].used == true) {
704 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
705 bit = pin_desc->altcx[i].control_bit;
706 if (readl(npct->prcm_base + reg) & BIT(bit))
707 return NMK_GPIO_ALT_C+i+1;
708 }
709 }
710 return NMK_GPIO_ALT_C;
711 }
712
nmk_gpio_get_mode(int gpio)713 int nmk_gpio_get_mode(int gpio)
714 {
715 struct nmk_gpio_chip *nmk_chip;
716 u32 afunc, bfunc, bit;
717
718 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
719 if (!nmk_chip)
720 return -EINVAL;
721
722 bit = 1 << (gpio % NMK_GPIO_PER_CHIP);
723
724 clk_enable(nmk_chip->clk);
725
726 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
727 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
728
729 clk_disable(nmk_chip->clk);
730
731 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
732 }
733 EXPORT_SYMBOL(nmk_gpio_get_mode);
734
735
736 /* IRQ functions */
nmk_gpio_get_bitmask(int gpio)737 static inline int nmk_gpio_get_bitmask(int gpio)
738 {
739 return 1 << (gpio % NMK_GPIO_PER_CHIP);
740 }
741
nmk_gpio_irq_ack(struct irq_data * d)742 static void nmk_gpio_irq_ack(struct irq_data *d)
743 {
744 struct nmk_gpio_chip *nmk_chip;
745
746 nmk_chip = irq_data_get_irq_chip_data(d);
747 if (!nmk_chip)
748 return;
749
750 clk_enable(nmk_chip->clk);
751 writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
752 clk_disable(nmk_chip->clk);
753 }
754
755 enum nmk_gpio_irq_type {
756 NORMAL,
757 WAKE,
758 };
759
__nmk_gpio_irq_modify(struct nmk_gpio_chip * nmk_chip,int gpio,enum nmk_gpio_irq_type which,bool enable)760 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
761 int gpio, enum nmk_gpio_irq_type which,
762 bool enable)
763 {
764 u32 bitmask = nmk_gpio_get_bitmask(gpio);
765 u32 *rimscval;
766 u32 *fimscval;
767 u32 rimscreg;
768 u32 fimscreg;
769
770 if (which == NORMAL) {
771 rimscreg = NMK_GPIO_RIMSC;
772 fimscreg = NMK_GPIO_FIMSC;
773 rimscval = &nmk_chip->rimsc;
774 fimscval = &nmk_chip->fimsc;
775 } else {
776 rimscreg = NMK_GPIO_RWIMSC;
777 fimscreg = NMK_GPIO_FWIMSC;
778 rimscval = &nmk_chip->rwimsc;
779 fimscval = &nmk_chip->fwimsc;
780 }
781
782 /* we must individually set/clear the two edges */
783 if (nmk_chip->edge_rising & bitmask) {
784 if (enable)
785 *rimscval |= bitmask;
786 else
787 *rimscval &= ~bitmask;
788 writel(*rimscval, nmk_chip->addr + rimscreg);
789 }
790 if (nmk_chip->edge_falling & bitmask) {
791 if (enable)
792 *fimscval |= bitmask;
793 else
794 *fimscval &= ~bitmask;
795 writel(*fimscval, nmk_chip->addr + fimscreg);
796 }
797 }
798
__nmk_gpio_set_wake(struct nmk_gpio_chip * nmk_chip,int gpio,bool on)799 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
800 int gpio, bool on)
801 {
802 /*
803 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
804 * disabled, since setting SLPM to 1 increases power consumption, and
805 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
806 */
807 if (nmk_chip->sleepmode && on) {
808 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP,
809 NMK_GPIO_SLPM_WAKEUP_ENABLE);
810 }
811
812 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
813 }
814
nmk_gpio_irq_maskunmask(struct irq_data * d,bool enable)815 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
816 {
817 struct nmk_gpio_chip *nmk_chip;
818 unsigned long flags;
819 u32 bitmask;
820
821 nmk_chip = irq_data_get_irq_chip_data(d);
822 bitmask = nmk_gpio_get_bitmask(d->hwirq);
823 if (!nmk_chip)
824 return -EINVAL;
825
826 clk_enable(nmk_chip->clk);
827 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
828 spin_lock(&nmk_chip->lock);
829
830 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
831
832 if (!(nmk_chip->real_wake & bitmask))
833 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
834
835 spin_unlock(&nmk_chip->lock);
836 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
837 clk_disable(nmk_chip->clk);
838
839 return 0;
840 }
841
nmk_gpio_irq_mask(struct irq_data * d)842 static void nmk_gpio_irq_mask(struct irq_data *d)
843 {
844 nmk_gpio_irq_maskunmask(d, false);
845 }
846
nmk_gpio_irq_unmask(struct irq_data * d)847 static void nmk_gpio_irq_unmask(struct irq_data *d)
848 {
849 nmk_gpio_irq_maskunmask(d, true);
850 }
851
nmk_gpio_irq_set_wake(struct irq_data * d,unsigned int on)852 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
853 {
854 struct nmk_gpio_chip *nmk_chip;
855 unsigned long flags;
856 u32 bitmask;
857
858 nmk_chip = irq_data_get_irq_chip_data(d);
859 if (!nmk_chip)
860 return -EINVAL;
861 bitmask = nmk_gpio_get_bitmask(d->hwirq);
862
863 clk_enable(nmk_chip->clk);
864 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
865 spin_lock(&nmk_chip->lock);
866
867 if (irqd_irq_disabled(d))
868 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
869
870 if (on)
871 nmk_chip->real_wake |= bitmask;
872 else
873 nmk_chip->real_wake &= ~bitmask;
874
875 spin_unlock(&nmk_chip->lock);
876 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
877 clk_disable(nmk_chip->clk);
878
879 return 0;
880 }
881
nmk_gpio_irq_set_type(struct irq_data * d,unsigned int type)882 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
883 {
884 bool enabled = !irqd_irq_disabled(d);
885 bool wake = irqd_is_wakeup_set(d);
886 struct nmk_gpio_chip *nmk_chip;
887 unsigned long flags;
888 u32 bitmask;
889
890 nmk_chip = irq_data_get_irq_chip_data(d);
891 bitmask = nmk_gpio_get_bitmask(d->hwirq);
892 if (!nmk_chip)
893 return -EINVAL;
894 if (type & IRQ_TYPE_LEVEL_HIGH)
895 return -EINVAL;
896 if (type & IRQ_TYPE_LEVEL_LOW)
897 return -EINVAL;
898
899 clk_enable(nmk_chip->clk);
900 spin_lock_irqsave(&nmk_chip->lock, flags);
901
902 if (enabled)
903 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
904
905 if (enabled || wake)
906 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
907
908 nmk_chip->edge_rising &= ~bitmask;
909 if (type & IRQ_TYPE_EDGE_RISING)
910 nmk_chip->edge_rising |= bitmask;
911
912 nmk_chip->edge_falling &= ~bitmask;
913 if (type & IRQ_TYPE_EDGE_FALLING)
914 nmk_chip->edge_falling |= bitmask;
915
916 if (enabled)
917 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
918
919 if (enabled || wake)
920 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
921
922 spin_unlock_irqrestore(&nmk_chip->lock, flags);
923 clk_disable(nmk_chip->clk);
924
925 return 0;
926 }
927
nmk_gpio_irq_startup(struct irq_data * d)928 static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
929 {
930 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
931
932 clk_enable(nmk_chip->clk);
933 nmk_gpio_irq_unmask(d);
934 return 0;
935 }
936
nmk_gpio_irq_shutdown(struct irq_data * d)937 static void nmk_gpio_irq_shutdown(struct irq_data *d)
938 {
939 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
940
941 nmk_gpio_irq_mask(d);
942 clk_disable(nmk_chip->clk);
943 }
944
945 static struct irq_chip nmk_gpio_irq_chip = {
946 .name = "Nomadik-GPIO",
947 .irq_ack = nmk_gpio_irq_ack,
948 .irq_mask = nmk_gpio_irq_mask,
949 .irq_unmask = nmk_gpio_irq_unmask,
950 .irq_set_type = nmk_gpio_irq_set_type,
951 .irq_set_wake = nmk_gpio_irq_set_wake,
952 .irq_startup = nmk_gpio_irq_startup,
953 .irq_shutdown = nmk_gpio_irq_shutdown,
954 .flags = IRQCHIP_MASK_ON_SUSPEND,
955 };
956
__nmk_gpio_irq_handler(unsigned int irq,struct irq_desc * desc,u32 status)957 static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
958 u32 status)
959 {
960 struct nmk_gpio_chip *nmk_chip;
961 struct irq_chip *host_chip = irq_get_chip(irq);
962
963 chained_irq_enter(host_chip, desc);
964
965 nmk_chip = irq_get_handler_data(irq);
966 while (status) {
967 int bit = __ffs(status);
968
969 generic_handle_irq(irq_find_mapping(nmk_chip->domain, bit));
970 status &= ~BIT(bit);
971 }
972
973 chained_irq_exit(host_chip, desc);
974 }
975
nmk_gpio_irq_handler(unsigned int irq,struct irq_desc * desc)976 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
977 {
978 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
979 u32 status;
980
981 clk_enable(nmk_chip->clk);
982 status = readl(nmk_chip->addr + NMK_GPIO_IS);
983 clk_disable(nmk_chip->clk);
984
985 __nmk_gpio_irq_handler(irq, desc, status);
986 }
987
nmk_gpio_secondary_irq_handler(unsigned int irq,struct irq_desc * desc)988 static void nmk_gpio_secondary_irq_handler(unsigned int irq,
989 struct irq_desc *desc)
990 {
991 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
992 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
993
994 __nmk_gpio_irq_handler(irq, desc, status);
995 }
996
nmk_gpio_init_irq(struct nmk_gpio_chip * nmk_chip)997 static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
998 {
999 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
1000 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
1001
1002 if (nmk_chip->secondary_parent_irq >= 0) {
1003 irq_set_chained_handler(nmk_chip->secondary_parent_irq,
1004 nmk_gpio_secondary_irq_handler);
1005 irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
1006 }
1007
1008 return 0;
1009 }
1010
1011 /* I/O Functions */
1012
nmk_gpio_request(struct gpio_chip * chip,unsigned offset)1013 static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset)
1014 {
1015 /*
1016 * Map back to global GPIO space and request muxing, the direction
1017 * parameter does not matter for this controller.
1018 */
1019 int gpio = chip->base + offset;
1020
1021 return pinctrl_request_gpio(gpio);
1022 }
1023
nmk_gpio_free(struct gpio_chip * chip,unsigned offset)1024 static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset)
1025 {
1026 int gpio = chip->base + offset;
1027
1028 pinctrl_free_gpio(gpio);
1029 }
1030
nmk_gpio_make_input(struct gpio_chip * chip,unsigned offset)1031 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
1032 {
1033 struct nmk_gpio_chip *nmk_chip =
1034 container_of(chip, struct nmk_gpio_chip, chip);
1035
1036 clk_enable(nmk_chip->clk);
1037
1038 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
1039
1040 clk_disable(nmk_chip->clk);
1041
1042 return 0;
1043 }
1044
nmk_gpio_get_input(struct gpio_chip * chip,unsigned offset)1045 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
1046 {
1047 struct nmk_gpio_chip *nmk_chip =
1048 container_of(chip, struct nmk_gpio_chip, chip);
1049 u32 bit = 1 << offset;
1050 int value;
1051
1052 clk_enable(nmk_chip->clk);
1053
1054 value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
1055
1056 clk_disable(nmk_chip->clk);
1057
1058 return value;
1059 }
1060
nmk_gpio_set_output(struct gpio_chip * chip,unsigned offset,int val)1061 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
1062 int val)
1063 {
1064 struct nmk_gpio_chip *nmk_chip =
1065 container_of(chip, struct nmk_gpio_chip, chip);
1066
1067 clk_enable(nmk_chip->clk);
1068
1069 __nmk_gpio_set_output(nmk_chip, offset, val);
1070
1071 clk_disable(nmk_chip->clk);
1072 }
1073
nmk_gpio_make_output(struct gpio_chip * chip,unsigned offset,int val)1074 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
1075 int val)
1076 {
1077 struct nmk_gpio_chip *nmk_chip =
1078 container_of(chip, struct nmk_gpio_chip, chip);
1079
1080 clk_enable(nmk_chip->clk);
1081
1082 __nmk_gpio_make_output(nmk_chip, offset, val);
1083
1084 clk_disable(nmk_chip->clk);
1085
1086 return 0;
1087 }
1088
nmk_gpio_to_irq(struct gpio_chip * chip,unsigned offset)1089 static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1090 {
1091 struct nmk_gpio_chip *nmk_chip =
1092 container_of(chip, struct nmk_gpio_chip, chip);
1093
1094 return irq_create_mapping(nmk_chip->domain, offset);
1095 }
1096
1097 #ifdef CONFIG_DEBUG_FS
1098
1099 #include <linux/seq_file.h>
1100
nmk_gpio_dbg_show_one(struct seq_file * s,struct pinctrl_dev * pctldev,struct gpio_chip * chip,unsigned offset,unsigned gpio)1101 static void nmk_gpio_dbg_show_one(struct seq_file *s,
1102 struct pinctrl_dev *pctldev, struct gpio_chip *chip,
1103 unsigned offset, unsigned gpio)
1104 {
1105 const char *label = gpiochip_is_requested(chip, offset);
1106 struct nmk_gpio_chip *nmk_chip =
1107 container_of(chip, struct nmk_gpio_chip, chip);
1108 int mode;
1109 bool is_out;
1110 bool pull;
1111 u32 bit = 1 << offset;
1112 const char *modes[] = {
1113 [NMK_GPIO_ALT_GPIO] = "gpio",
1114 [NMK_GPIO_ALT_A] = "altA",
1115 [NMK_GPIO_ALT_B] = "altB",
1116 [NMK_GPIO_ALT_C] = "altC",
1117 [NMK_GPIO_ALT_C+1] = "altC1",
1118 [NMK_GPIO_ALT_C+2] = "altC2",
1119 [NMK_GPIO_ALT_C+3] = "altC3",
1120 [NMK_GPIO_ALT_C+4] = "altC4",
1121 };
1122
1123 clk_enable(nmk_chip->clk);
1124 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
1125 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
1126 mode = nmk_gpio_get_mode(gpio);
1127 if ((mode == NMK_GPIO_ALT_C) && pctldev)
1128 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
1129
1130 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
1131 gpio, label ?: "(none)",
1132 is_out ? "out" : "in ",
1133 chip->get
1134 ? (chip->get(chip, offset) ? "hi" : "lo")
1135 : "? ",
1136 (mode < 0) ? "unknown" : modes[mode],
1137 pull ? "pull" : "none");
1138
1139 if (label && !is_out) {
1140 int irq = gpio_to_irq(gpio);
1141 struct irq_desc *desc = irq_to_desc(irq);
1142
1143 /* This races with request_irq(), set_irq_type(),
1144 * and set_irq_wake() ... but those are "rare".
1145 */
1146 if (irq >= 0 && desc->action) {
1147 char *trigger;
1148 u32 bitmask = nmk_gpio_get_bitmask(gpio);
1149
1150 if (nmk_chip->edge_rising & bitmask)
1151 trigger = "edge-rising";
1152 else if (nmk_chip->edge_falling & bitmask)
1153 trigger = "edge-falling";
1154 else
1155 trigger = "edge-undefined";
1156
1157 seq_printf(s, " irq-%d %s%s",
1158 irq, trigger,
1159 irqd_is_wakeup_set(&desc->irq_data)
1160 ? " wakeup" : "");
1161 }
1162 }
1163 clk_disable(nmk_chip->clk);
1164 }
1165
nmk_gpio_dbg_show(struct seq_file * s,struct gpio_chip * chip)1166 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1167 {
1168 unsigned i;
1169 unsigned gpio = chip->base;
1170
1171 for (i = 0; i < chip->ngpio; i++, gpio++) {
1172 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio);
1173 seq_printf(s, "\n");
1174 }
1175 }
1176
1177 #else
nmk_gpio_dbg_show_one(struct seq_file * s,struct pinctrl_dev * pctldev,struct gpio_chip * chip,unsigned offset,unsigned gpio)1178 static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1179 struct pinctrl_dev *pctldev,
1180 struct gpio_chip *chip,
1181 unsigned offset, unsigned gpio)
1182 {
1183 }
1184 #define nmk_gpio_dbg_show NULL
1185 #endif
1186
1187 /* This structure is replicated for each GPIO block allocated at probe time */
1188 static struct gpio_chip nmk_gpio_template = {
1189 .request = nmk_gpio_request,
1190 .free = nmk_gpio_free,
1191 .direction_input = nmk_gpio_make_input,
1192 .get = nmk_gpio_get_input,
1193 .direction_output = nmk_gpio_make_output,
1194 .set = nmk_gpio_set_output,
1195 .to_irq = nmk_gpio_to_irq,
1196 .dbg_show = nmk_gpio_dbg_show,
1197 .can_sleep = 0,
1198 };
1199
nmk_gpio_clocks_enable(void)1200 void nmk_gpio_clocks_enable(void)
1201 {
1202 int i;
1203
1204 for (i = 0; i < NUM_BANKS; i++) {
1205 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1206
1207 if (!chip)
1208 continue;
1209
1210 clk_enable(chip->clk);
1211 }
1212 }
1213
nmk_gpio_clocks_disable(void)1214 void nmk_gpio_clocks_disable(void)
1215 {
1216 int i;
1217
1218 for (i = 0; i < NUM_BANKS; i++) {
1219 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1220
1221 if (!chip)
1222 continue;
1223
1224 clk_disable(chip->clk);
1225 }
1226 }
1227
1228 /*
1229 * Called from the suspend/resume path to only keep the real wakeup interrupts
1230 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
1231 * and not the rest of the interrupts which we needed to have as wakeups for
1232 * cpuidle.
1233 *
1234 * PM ops are not used since this needs to be done at the end, after all the
1235 * other drivers are done with their suspend callbacks.
1236 */
nmk_gpio_wakeups_suspend(void)1237 void nmk_gpio_wakeups_suspend(void)
1238 {
1239 int i;
1240
1241 for (i = 0; i < NUM_BANKS; i++) {
1242 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1243
1244 if (!chip)
1245 break;
1246
1247 clk_enable(chip->clk);
1248
1249 writel(chip->rwimsc & chip->real_wake,
1250 chip->addr + NMK_GPIO_RWIMSC);
1251 writel(chip->fwimsc & chip->real_wake,
1252 chip->addr + NMK_GPIO_FWIMSC);
1253
1254 clk_disable(chip->clk);
1255 }
1256 }
1257
nmk_gpio_wakeups_resume(void)1258 void nmk_gpio_wakeups_resume(void)
1259 {
1260 int i;
1261
1262 for (i = 0; i < NUM_BANKS; i++) {
1263 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1264
1265 if (!chip)
1266 break;
1267
1268 clk_enable(chip->clk);
1269
1270 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
1271 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
1272
1273 clk_disable(chip->clk);
1274 }
1275 }
1276
1277 /*
1278 * Read the pull up/pull down status.
1279 * A bit set in 'pull_up' means that pull up
1280 * is selected if pull is enabled in PDIS register.
1281 * Note: only pull up/down set via this driver can
1282 * be detected due to HW limitations.
1283 */
nmk_gpio_read_pull(int gpio_bank,u32 * pull_up)1284 void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
1285 {
1286 if (gpio_bank < NUM_BANKS) {
1287 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
1288
1289 if (!chip)
1290 return;
1291
1292 *pull_up = chip->pull_up;
1293 }
1294 }
1295
nmk_gpio_irq_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)1296 static int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1297 irq_hw_number_t hwirq)
1298 {
1299 struct nmk_gpio_chip *nmk_chip = d->host_data;
1300
1301 if (!nmk_chip)
1302 return -EINVAL;
1303
1304 irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq);
1305 set_irq_flags(irq, IRQF_VALID);
1306 irq_set_chip_data(irq, nmk_chip);
1307 irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING);
1308
1309 return 0;
1310 }
1311
1312 const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
1313 .map = nmk_gpio_irq_map,
1314 .xlate = irq_domain_xlate_twocell,
1315 };
1316
nmk_gpio_probe(struct platform_device * dev)1317 static int nmk_gpio_probe(struct platform_device *dev)
1318 {
1319 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
1320 struct device_node *np = dev->dev.of_node;
1321 struct nmk_gpio_chip *nmk_chip;
1322 struct gpio_chip *chip;
1323 struct resource *res;
1324 struct clk *clk;
1325 int secondary_irq;
1326 void __iomem *base;
1327 int irq_start = 0;
1328 int irq;
1329 int ret;
1330
1331 if (!pdata && !np) {
1332 dev_err(&dev->dev, "No platform data or device tree found\n");
1333 return -ENODEV;
1334 }
1335
1336 if (np) {
1337 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
1338 if (!pdata)
1339 return -ENOMEM;
1340
1341 if (of_get_property(np, "st,supports-sleepmode", NULL))
1342 pdata->supports_sleepmode = true;
1343
1344 if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
1345 dev_err(&dev->dev, "gpio-bank property not found\n");
1346 return -EINVAL;
1347 }
1348
1349 pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
1350 pdata->num_gpio = NMK_GPIO_PER_CHIP;
1351 }
1352
1353 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1354 if (!res)
1355 return -ENOENT;
1356
1357 irq = platform_get_irq(dev, 0);
1358 if (irq < 0)
1359 return irq;
1360
1361 secondary_irq = platform_get_irq(dev, 1);
1362 if (secondary_irq >= 0 && !pdata->get_secondary_status)
1363 return -EINVAL;
1364
1365 base = devm_ioremap_resource(&dev->dev, res);
1366 if (IS_ERR(base))
1367 return PTR_ERR(base);
1368
1369 clk = devm_clk_get(&dev->dev, NULL);
1370 if (IS_ERR(clk))
1371 return PTR_ERR(clk);
1372 clk_prepare(clk);
1373
1374 nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1375 if (!nmk_chip)
1376 return -ENOMEM;
1377
1378 /*
1379 * The virt address in nmk_chip->addr is in the nomadik register space,
1380 * so we can simply convert the resource address, without remapping
1381 */
1382 nmk_chip->bank = dev->id;
1383 nmk_chip->clk = clk;
1384 nmk_chip->addr = base;
1385 nmk_chip->chip = nmk_gpio_template;
1386 nmk_chip->parent_irq = irq;
1387 nmk_chip->secondary_parent_irq = secondary_irq;
1388 nmk_chip->get_secondary_status = pdata->get_secondary_status;
1389 nmk_chip->set_ioforce = pdata->set_ioforce;
1390 nmk_chip->sleepmode = pdata->supports_sleepmode;
1391 spin_lock_init(&nmk_chip->lock);
1392
1393 chip = &nmk_chip->chip;
1394 chip->base = pdata->first_gpio;
1395 chip->ngpio = pdata->num_gpio;
1396 chip->label = pdata->name ?: dev_name(&dev->dev);
1397 chip->dev = &dev->dev;
1398 chip->owner = THIS_MODULE;
1399
1400 clk_enable(nmk_chip->clk);
1401 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1402 clk_disable(nmk_chip->clk);
1403
1404 #ifdef CONFIG_OF_GPIO
1405 chip->of_node = np;
1406 #endif
1407
1408 ret = gpiochip_add(&nmk_chip->chip);
1409 if (ret)
1410 return ret;
1411
1412 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1413
1414 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1415
1416 platform_set_drvdata(dev, nmk_chip);
1417
1418 if (!np)
1419 irq_start = pdata->first_irq;
1420 nmk_chip->domain = irq_domain_add_simple(np,
1421 NMK_GPIO_PER_CHIP, irq_start,
1422 &nmk_gpio_irq_simple_ops, nmk_chip);
1423 if (!nmk_chip->domain) {
1424 dev_err(&dev->dev, "failed to create irqdomain\n");
1425 /* Just do this, no matter if it fails */
1426 ret = gpiochip_remove(&nmk_chip->chip);
1427 return -ENOSYS;
1428 }
1429
1430 nmk_gpio_init_irq(nmk_chip);
1431
1432 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1433
1434 return 0;
1435 }
1436
nmk_get_groups_cnt(struct pinctrl_dev * pctldev)1437 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1438 {
1439 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1440
1441 return npct->soc->ngroups;
1442 }
1443
nmk_get_group_name(struct pinctrl_dev * pctldev,unsigned selector)1444 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1445 unsigned selector)
1446 {
1447 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1448
1449 return npct->soc->groups[selector].name;
1450 }
1451
nmk_get_group_pins(struct pinctrl_dev * pctldev,unsigned selector,const unsigned ** pins,unsigned * num_pins)1452 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1453 const unsigned **pins,
1454 unsigned *num_pins)
1455 {
1456 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1457
1458 *pins = npct->soc->groups[selector].pins;
1459 *num_pins = npct->soc->groups[selector].npins;
1460 return 0;
1461 }
1462
1463 static struct pinctrl_gpio_range *
nmk_match_gpio_range(struct pinctrl_dev * pctldev,unsigned offset)1464 nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset)
1465 {
1466 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1467 int i;
1468
1469 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1470 struct pinctrl_gpio_range *range;
1471
1472 range = &npct->soc->gpio_ranges[i];
1473 if (offset >= range->pin_base &&
1474 offset <= (range->pin_base + range->npins - 1))
1475 return range;
1476 }
1477 return NULL;
1478 }
1479
nmk_pin_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned offset)1480 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1481 unsigned offset)
1482 {
1483 struct pinctrl_gpio_range *range;
1484 struct gpio_chip *chip;
1485
1486 range = nmk_match_gpio_range(pctldev, offset);
1487 if (!range || !range->gc) {
1488 seq_printf(s, "invalid pin offset");
1489 return;
1490 }
1491 chip = range->gc;
1492 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
1493 }
1494
nmk_pinctrl_dt_free_map(struct pinctrl_dev * pctldev,struct pinctrl_map * map,unsigned num_maps)1495 static void nmk_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
1496 struct pinctrl_map *map, unsigned num_maps)
1497 {
1498 int i;
1499
1500 for (i = 0; i < num_maps; i++)
1501 if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
1502 kfree(map[i].data.configs.configs);
1503 kfree(map);
1504 }
1505
nmk_dt_reserve_map(struct pinctrl_map ** map,unsigned * reserved_maps,unsigned * num_maps,unsigned reserve)1506 static int nmk_dt_reserve_map(struct pinctrl_map **map, unsigned *reserved_maps,
1507 unsigned *num_maps, unsigned reserve)
1508 {
1509 unsigned old_num = *reserved_maps;
1510 unsigned new_num = *num_maps + reserve;
1511 struct pinctrl_map *new_map;
1512
1513 if (old_num >= new_num)
1514 return 0;
1515
1516 new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL);
1517 if (!new_map)
1518 return -ENOMEM;
1519
1520 memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map));
1521
1522 *map = new_map;
1523 *reserved_maps = new_num;
1524
1525 return 0;
1526 }
1527
nmk_dt_add_map_mux(struct pinctrl_map ** map,unsigned * reserved_maps,unsigned * num_maps,const char * group,const char * function)1528 static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
1529 unsigned *num_maps, const char *group,
1530 const char *function)
1531 {
1532 if (*num_maps == *reserved_maps)
1533 return -ENOSPC;
1534
1535 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
1536 (*map)[*num_maps].data.mux.group = group;
1537 (*map)[*num_maps].data.mux.function = function;
1538 (*num_maps)++;
1539
1540 return 0;
1541 }
1542
nmk_dt_add_map_configs(struct pinctrl_map ** map,unsigned * reserved_maps,unsigned * num_maps,const char * group,unsigned long * configs,unsigned num_configs)1543 static int nmk_dt_add_map_configs(struct pinctrl_map **map,
1544 unsigned *reserved_maps,
1545 unsigned *num_maps, const char *group,
1546 unsigned long *configs, unsigned num_configs)
1547 {
1548 unsigned long *dup_configs;
1549
1550 if (*num_maps == *reserved_maps)
1551 return -ENOSPC;
1552
1553 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
1554 GFP_KERNEL);
1555 if (!dup_configs)
1556 return -ENOMEM;
1557
1558 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
1559
1560 (*map)[*num_maps].data.configs.group_or_pin = group;
1561 (*map)[*num_maps].data.configs.configs = dup_configs;
1562 (*map)[*num_maps].data.configs.num_configs = num_configs;
1563 (*num_maps)++;
1564
1565 return 0;
1566 }
1567
1568 #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, }
1569 #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \
1570 .size = ARRAY_SIZE(y), }
1571
1572 static const unsigned long nmk_pin_input_modes[] = {
1573 PIN_INPUT_NOPULL,
1574 PIN_INPUT_PULLUP,
1575 PIN_INPUT_PULLDOWN,
1576 };
1577
1578 static const unsigned long nmk_pin_output_modes[] = {
1579 PIN_OUTPUT_LOW,
1580 PIN_OUTPUT_HIGH,
1581 PIN_DIR_OUTPUT,
1582 };
1583
1584 static const unsigned long nmk_pin_sleep_modes[] = {
1585 PIN_SLEEPMODE_DISABLED,
1586 PIN_SLEEPMODE_ENABLED,
1587 };
1588
1589 static const unsigned long nmk_pin_sleep_input_modes[] = {
1590 PIN_SLPM_INPUT_NOPULL,
1591 PIN_SLPM_INPUT_PULLUP,
1592 PIN_SLPM_INPUT_PULLDOWN,
1593 PIN_SLPM_DIR_INPUT,
1594 };
1595
1596 static const unsigned long nmk_pin_sleep_output_modes[] = {
1597 PIN_SLPM_OUTPUT_LOW,
1598 PIN_SLPM_OUTPUT_HIGH,
1599 PIN_SLPM_DIR_OUTPUT,
1600 };
1601
1602 static const unsigned long nmk_pin_sleep_wakeup_modes[] = {
1603 PIN_SLPM_WAKEUP_DISABLE,
1604 PIN_SLPM_WAKEUP_ENABLE,
1605 };
1606
1607 static const unsigned long nmk_pin_gpio_modes[] = {
1608 PIN_GPIOMODE_DISABLED,
1609 PIN_GPIOMODE_ENABLED,
1610 };
1611
1612 static const unsigned long nmk_pin_sleep_pdis_modes[] = {
1613 PIN_SLPM_PDIS_DISABLED,
1614 PIN_SLPM_PDIS_ENABLED,
1615 };
1616
1617 struct nmk_cfg_param {
1618 const char *property;
1619 unsigned long config;
1620 const unsigned long *choice;
1621 int size;
1622 };
1623
1624 static const struct nmk_cfg_param nmk_cfg_params[] = {
1625 NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes),
1626 NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes),
1627 NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes),
1628 NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes),
1629 NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes),
1630 NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes),
1631 NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes),
1632 NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes),
1633 };
1634
nmk_dt_pin_config(int index,int val,unsigned long * config)1635 static int nmk_dt_pin_config(int index, int val, unsigned long *config)
1636 {
1637 int ret = 0;
1638
1639 if (nmk_cfg_params[index].choice == NULL)
1640 *config = nmk_cfg_params[index].config;
1641 else {
1642 /* test if out of range */
1643 if (val < nmk_cfg_params[index].size) {
1644 *config = nmk_cfg_params[index].config |
1645 nmk_cfg_params[index].choice[val];
1646 }
1647 }
1648 return ret;
1649 }
1650
nmk_find_pin_name(struct pinctrl_dev * pctldev,const char * pin_name)1651 static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name)
1652 {
1653 int i, pin_number;
1654 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1655
1656 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
1657 for (i = 0; i < npct->soc->npins; i++)
1658 if (npct->soc->pins[i].number == pin_number)
1659 return npct->soc->pins[i].name;
1660 return NULL;
1661 }
1662
nmk_pinctrl_dt_get_config(struct device_node * np,unsigned long * configs)1663 static bool nmk_pinctrl_dt_get_config(struct device_node *np,
1664 unsigned long *configs)
1665 {
1666 bool has_config = 0;
1667 unsigned long cfg = 0;
1668 int i, val, ret;
1669
1670 for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) {
1671 ret = of_property_read_u32(np,
1672 nmk_cfg_params[i].property, &val);
1673 if (ret != -EINVAL) {
1674 if (nmk_dt_pin_config(i, val, &cfg) == 0) {
1675 *configs |= cfg;
1676 has_config = 1;
1677 }
1678 }
1679 }
1680
1681 return has_config;
1682 }
1683
nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned * reserved_maps,unsigned * num_maps)1684 int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
1685 struct device_node *np,
1686 struct pinctrl_map **map,
1687 unsigned *reserved_maps,
1688 unsigned *num_maps)
1689 {
1690 int ret;
1691 const char *function = NULL;
1692 unsigned long configs = 0;
1693 bool has_config = 0;
1694 unsigned reserve = 0;
1695 struct property *prop;
1696 const char *group, *gpio_name;
1697 struct device_node *np_config;
1698
1699 ret = of_property_read_string(np, "ste,function", &function);
1700 if (ret >= 0)
1701 reserve = 1;
1702
1703 has_config = nmk_pinctrl_dt_get_config(np, &configs);
1704
1705 np_config = of_parse_phandle(np, "ste,config", 0);
1706 if (np_config)
1707 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
1708
1709 ret = of_property_count_strings(np, "ste,pins");
1710 if (ret < 0)
1711 goto exit;
1712
1713 if (has_config)
1714 reserve++;
1715
1716 reserve *= ret;
1717
1718 ret = nmk_dt_reserve_map(map, reserved_maps, num_maps, reserve);
1719 if (ret < 0)
1720 goto exit;
1721
1722 of_property_for_each_string(np, "ste,pins", prop, group) {
1723 if (function) {
1724 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
1725 group, function);
1726 if (ret < 0)
1727 goto exit;
1728 }
1729 if (has_config) {
1730 gpio_name = nmk_find_pin_name(pctldev, group);
1731
1732 ret = nmk_dt_add_map_configs(map, reserved_maps, num_maps,
1733 gpio_name, &configs, 1);
1734 if (ret < 0)
1735 goto exit;
1736 }
1737
1738 }
1739 exit:
1740 return ret;
1741 }
1742
nmk_pinctrl_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np_config,struct pinctrl_map ** map,unsigned * num_maps)1743 int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
1744 struct device_node *np_config,
1745 struct pinctrl_map **map, unsigned *num_maps)
1746 {
1747 unsigned reserved_maps;
1748 struct device_node *np;
1749 int ret;
1750
1751 reserved_maps = 0;
1752 *map = NULL;
1753 *num_maps = 0;
1754
1755 for_each_child_of_node(np_config, np) {
1756 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
1757 &reserved_maps, num_maps);
1758 if (ret < 0) {
1759 nmk_pinctrl_dt_free_map(pctldev, *map, *num_maps);
1760 return ret;
1761 }
1762 }
1763
1764 return 0;
1765 }
1766
1767 static const struct pinctrl_ops nmk_pinctrl_ops = {
1768 .get_groups_count = nmk_get_groups_cnt,
1769 .get_group_name = nmk_get_group_name,
1770 .get_group_pins = nmk_get_group_pins,
1771 .pin_dbg_show = nmk_pin_dbg_show,
1772 .dt_node_to_map = nmk_pinctrl_dt_node_to_map,
1773 .dt_free_map = nmk_pinctrl_dt_free_map,
1774 };
1775
nmk_pmx_get_funcs_cnt(struct pinctrl_dev * pctldev)1776 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1777 {
1778 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1779
1780 return npct->soc->nfunctions;
1781 }
1782
nmk_pmx_get_func_name(struct pinctrl_dev * pctldev,unsigned function)1783 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1784 unsigned function)
1785 {
1786 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1787
1788 return npct->soc->functions[function].name;
1789 }
1790
nmk_pmx_get_func_groups(struct pinctrl_dev * pctldev,unsigned function,const char * const ** groups,unsigned * const num_groups)1791 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1792 unsigned function,
1793 const char * const **groups,
1794 unsigned * const num_groups)
1795 {
1796 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1797
1798 *groups = npct->soc->functions[function].groups;
1799 *num_groups = npct->soc->functions[function].ngroups;
1800
1801 return 0;
1802 }
1803
nmk_pmx_enable(struct pinctrl_dev * pctldev,unsigned function,unsigned group)1804 static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
1805 unsigned group)
1806 {
1807 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1808 const struct nmk_pingroup *g;
1809 static unsigned int slpm[NUM_BANKS];
1810 unsigned long flags;
1811 bool glitch;
1812 int ret = -EINVAL;
1813 int i;
1814
1815 g = &npct->soc->groups[group];
1816
1817 if (g->altsetting < 0)
1818 return -EINVAL;
1819
1820 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1821
1822 /*
1823 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
1824 * we may pass through an undesired state. In this case we take
1825 * some extra care.
1826 *
1827 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
1828 * - Save SLPM registers (since we have a shadow register in the
1829 * nmk_chip we're using that as backup)
1830 * - Set SLPM=0 for the IOs you want to switch and others to 1
1831 * - Configure the GPIO registers for the IOs that are being switched
1832 * - Set IOFORCE=1
1833 * - Modify the AFLSA/B registers for the IOs that are being switched
1834 * - Set IOFORCE=0
1835 * - Restore SLPM registers
1836 * - Any spurious wake up event during switch sequence to be ignored
1837 * and cleared
1838 *
1839 * We REALLY need to save ALL slpm registers, because the external
1840 * IOFORCE will switch *all* ports to their sleepmode setting to as
1841 * to avoid glitches. (Not just one port!)
1842 */
1843 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
1844
1845 if (glitch) {
1846 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1847
1848 /* Initially don't put any pins to sleep when switching */
1849 memset(slpm, 0xff, sizeof(slpm));
1850
1851 /*
1852 * Then mask the pins that need to be sleeping now when we're
1853 * switching to the ALT C function.
1854 */
1855 for (i = 0; i < g->npins; i++)
1856 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1857 nmk_gpio_glitch_slpm_init(slpm);
1858 }
1859
1860 for (i = 0; i < g->npins; i++) {
1861 struct pinctrl_gpio_range *range;
1862 struct nmk_gpio_chip *nmk_chip;
1863 struct gpio_chip *chip;
1864 unsigned bit;
1865
1866 range = nmk_match_gpio_range(pctldev, g->pins[i]);
1867 if (!range) {
1868 dev_err(npct->dev,
1869 "invalid pin offset %d in group %s at index %d\n",
1870 g->pins[i], g->name, i);
1871 goto out_glitch;
1872 }
1873 if (!range->gc) {
1874 dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n",
1875 g->pins[i], g->name, i);
1876 goto out_glitch;
1877 }
1878 chip = range->gc;
1879 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1880 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1881
1882 clk_enable(nmk_chip->clk);
1883 bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1884 /*
1885 * If the pin is switching to altfunc, and there was an
1886 * interrupt installed on it which has been lazy disabled,
1887 * actually mask the interrupt to prevent spurious interrupts
1888 * that would occur while the pin is under control of the
1889 * peripheral. Only SKE does this.
1890 */
1891 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1892
1893 __nmk_gpio_set_mode_safe(nmk_chip, bit,
1894 (g->altsetting & NMK_GPIO_ALT_C), glitch);
1895 clk_disable(nmk_chip->clk);
1896
1897 /*
1898 * Call PRCM GPIOCR config function in case ALTC
1899 * has been selected:
1900 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
1901 * must be set.
1902 * - If selection is pure ALTC and previous selection was ALTCx,
1903 * then some bits in PRCM GPIOCR registers must be cleared.
1904 */
1905 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
1906 nmk_prcm_altcx_set_mode(npct, g->pins[i],
1907 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
1908 }
1909
1910 /* When all pins are successfully reconfigured we get here */
1911 ret = 0;
1912
1913 out_glitch:
1914 if (glitch) {
1915 nmk_gpio_glitch_slpm_restore(slpm);
1916 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1917 }
1918
1919 return ret;
1920 }
1921
nmk_pmx_disable(struct pinctrl_dev * pctldev,unsigned function,unsigned group)1922 static void nmk_pmx_disable(struct pinctrl_dev *pctldev,
1923 unsigned function, unsigned group)
1924 {
1925 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1926 const struct nmk_pingroup *g;
1927
1928 g = &npct->soc->groups[group];
1929
1930 if (g->altsetting < 0)
1931 return;
1932
1933 /* Poke out the mux, set the pin to some default state? */
1934 dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins);
1935 }
1936
nmk_gpio_request_enable(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned offset)1937 static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1938 struct pinctrl_gpio_range *range,
1939 unsigned offset)
1940 {
1941 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1942 struct nmk_gpio_chip *nmk_chip;
1943 struct gpio_chip *chip;
1944 unsigned bit;
1945
1946 if (!range) {
1947 dev_err(npct->dev, "invalid range\n");
1948 return -EINVAL;
1949 }
1950 if (!range->gc) {
1951 dev_err(npct->dev, "missing GPIO chip in range\n");
1952 return -EINVAL;
1953 }
1954 chip = range->gc;
1955 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1956
1957 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1958
1959 clk_enable(nmk_chip->clk);
1960 bit = offset % NMK_GPIO_PER_CHIP;
1961 /* There is no glitch when converting any pin to GPIO */
1962 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1963 clk_disable(nmk_chip->clk);
1964
1965 return 0;
1966 }
1967
nmk_gpio_disable_free(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned offset)1968 static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1969 struct pinctrl_gpio_range *range,
1970 unsigned offset)
1971 {
1972 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1973
1974 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1975 /* Set the pin to some default state, GPIO is usually default */
1976 }
1977
1978 static const struct pinmux_ops nmk_pinmux_ops = {
1979 .get_functions_count = nmk_pmx_get_funcs_cnt,
1980 .get_function_name = nmk_pmx_get_func_name,
1981 .get_function_groups = nmk_pmx_get_func_groups,
1982 .enable = nmk_pmx_enable,
1983 .disable = nmk_pmx_disable,
1984 .gpio_request_enable = nmk_gpio_request_enable,
1985 .gpio_disable_free = nmk_gpio_disable_free,
1986 };
1987
nmk_pin_config_get(struct pinctrl_dev * pctldev,unsigned pin,unsigned long * config)1988 static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
1989 unsigned long *config)
1990 {
1991 /* Not implemented */
1992 return -EINVAL;
1993 }
1994
nmk_pin_config_set(struct pinctrl_dev * pctldev,unsigned pin,unsigned long config)1995 static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1996 unsigned long config)
1997 {
1998 static const char *pullnames[] = {
1999 [NMK_GPIO_PULL_NONE] = "none",
2000 [NMK_GPIO_PULL_UP] = "up",
2001 [NMK_GPIO_PULL_DOWN] = "down",
2002 [3] /* illegal */ = "??"
2003 };
2004 static const char *slpmnames[] = {
2005 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
2006 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
2007 };
2008 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
2009 struct nmk_gpio_chip *nmk_chip;
2010 struct pinctrl_gpio_range *range;
2011 struct gpio_chip *chip;
2012 unsigned bit;
2013
2014 /*
2015 * The pin config contains pin number and altfunction fields, here
2016 * we just ignore that part. It's being handled by the framework and
2017 * pinmux callback respectively.
2018 */
2019 pin_cfg_t cfg = (pin_cfg_t) config;
2020 int pull = PIN_PULL(cfg);
2021 int slpm = PIN_SLPM(cfg);
2022 int output = PIN_DIR(cfg);
2023 int val = PIN_VAL(cfg);
2024 bool lowemi = PIN_LOWEMI(cfg);
2025 bool gpiomode = PIN_GPIOMODE(cfg);
2026 bool sleep = PIN_SLEEPMODE(cfg);
2027
2028 range = nmk_match_gpio_range(pctldev, pin);
2029 if (!range) {
2030 dev_err(npct->dev, "invalid pin offset %d\n", pin);
2031 return -EINVAL;
2032 }
2033 if (!range->gc) {
2034 dev_err(npct->dev, "GPIO chip missing in range for pin %d\n",
2035 pin);
2036 return -EINVAL;
2037 }
2038 chip = range->gc;
2039 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
2040
2041 if (sleep) {
2042 int slpm_pull = PIN_SLPM_PULL(cfg);
2043 int slpm_output = PIN_SLPM_DIR(cfg);
2044 int slpm_val = PIN_SLPM_VAL(cfg);
2045
2046 /* All pins go into GPIO mode at sleep */
2047 gpiomode = true;
2048
2049 /*
2050 * The SLPM_* values are normal values + 1 to allow zero to
2051 * mean "same as normal".
2052 */
2053 if (slpm_pull)
2054 pull = slpm_pull - 1;
2055 if (slpm_output)
2056 output = slpm_output - 1;
2057 if (slpm_val)
2058 val = slpm_val - 1;
2059
2060 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
2061 pin,
2062 slpm_pull ? pullnames[pull] : "same",
2063 slpm_output ? (output ? "output" : "input") : "same",
2064 slpm_val ? (val ? "high" : "low") : "same");
2065 }
2066
2067 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
2068 pin, cfg, pullnames[pull], slpmnames[slpm],
2069 output ? "output " : "input",
2070 output ? (val ? "high" : "low") : "",
2071 lowemi ? "on" : "off");
2072
2073 clk_enable(nmk_chip->clk);
2074 bit = pin % NMK_GPIO_PER_CHIP;
2075 if (gpiomode)
2076 /* No glitch when going to GPIO mode */
2077 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
2078 if (output)
2079 __nmk_gpio_make_output(nmk_chip, bit, val);
2080 else {
2081 __nmk_gpio_make_input(nmk_chip, bit);
2082 __nmk_gpio_set_pull(nmk_chip, bit, pull);
2083 }
2084 /* TODO: isn't this only applicable on output pins? */
2085 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
2086
2087 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
2088 clk_disable(nmk_chip->clk);
2089 return 0;
2090 }
2091
2092 static const struct pinconf_ops nmk_pinconf_ops = {
2093 .pin_config_get = nmk_pin_config_get,
2094 .pin_config_set = nmk_pin_config_set,
2095 };
2096
2097 static struct pinctrl_desc nmk_pinctrl_desc = {
2098 .name = "pinctrl-nomadik",
2099 .pctlops = &nmk_pinctrl_ops,
2100 .pmxops = &nmk_pinmux_ops,
2101 .confops = &nmk_pinconf_ops,
2102 .owner = THIS_MODULE,
2103 };
2104
2105 static const struct of_device_id nmk_pinctrl_match[] = {
2106 {
2107 .compatible = "stericsson,nmk-pinctrl-stn8815",
2108 .data = (void *)PINCTRL_NMK_STN8815,
2109 },
2110 {
2111 .compatible = "stericsson,nmk-pinctrl",
2112 .data = (void *)PINCTRL_NMK_DB8500,
2113 },
2114 {
2115 .compatible = "stericsson,nmk-pinctrl-db8540",
2116 .data = (void *)PINCTRL_NMK_DB8540,
2117 },
2118 {},
2119 };
2120
nmk_pinctrl_suspend(struct platform_device * pdev,pm_message_t state)2121 static int nmk_pinctrl_suspend(struct platform_device *pdev, pm_message_t state)
2122 {
2123 struct nmk_pinctrl *npct;
2124
2125 npct = platform_get_drvdata(pdev);
2126 if (!npct)
2127 return -EINVAL;
2128
2129 return pinctrl_force_sleep(npct->pctl);
2130 }
2131
nmk_pinctrl_resume(struct platform_device * pdev)2132 static int nmk_pinctrl_resume(struct platform_device *pdev)
2133 {
2134 struct nmk_pinctrl *npct;
2135
2136 npct = platform_get_drvdata(pdev);
2137 if (!npct)
2138 return -EINVAL;
2139
2140 return pinctrl_force_default(npct->pctl);
2141 }
2142
nmk_pinctrl_probe(struct platform_device * pdev)2143 static int nmk_pinctrl_probe(struct platform_device *pdev)
2144 {
2145 const struct platform_device_id *platid = platform_get_device_id(pdev);
2146 struct device_node *np = pdev->dev.of_node;
2147 struct device_node *prcm_np;
2148 struct nmk_pinctrl *npct;
2149 struct resource *res;
2150 unsigned int version = 0;
2151 int i;
2152
2153 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
2154 if (!npct)
2155 return -ENOMEM;
2156
2157 if (platid)
2158 version = platid->driver_data;
2159 else if (np) {
2160 const struct of_device_id *match;
2161
2162 match = of_match_device(nmk_pinctrl_match, &pdev->dev);
2163 if (!match)
2164 return -ENODEV;
2165 version = (unsigned int) match->data;
2166 }
2167
2168 /* Poke in other ASIC variants here */
2169 if (version == PINCTRL_NMK_STN8815)
2170 nmk_pinctrl_stn8815_init(&npct->soc);
2171 if (version == PINCTRL_NMK_DB8500)
2172 nmk_pinctrl_db8500_init(&npct->soc);
2173 if (version == PINCTRL_NMK_DB8540)
2174 nmk_pinctrl_db8540_init(&npct->soc);
2175
2176 if (np) {
2177 prcm_np = of_parse_phandle(np, "prcm", 0);
2178 if (prcm_np)
2179 npct->prcm_base = of_iomap(prcm_np, 0);
2180 }
2181
2182 /* Allow platform passed information to over-write DT. */
2183 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2184 if (res)
2185 npct->prcm_base = devm_ioremap(&pdev->dev, res->start,
2186 resource_size(res));
2187 if (!npct->prcm_base) {
2188 if (version == PINCTRL_NMK_STN8815) {
2189 dev_info(&pdev->dev,
2190 "No PRCM base, "
2191 "assuming no ALT-Cx control is available\n");
2192 } else {
2193 dev_err(&pdev->dev, "missing PRCM base address\n");
2194 return -EINVAL;
2195 }
2196 }
2197
2198 /*
2199 * We need all the GPIO drivers to probe FIRST, or we will not be able
2200 * to obtain references to the struct gpio_chip * for them, and we
2201 * need this to proceed.
2202 */
2203 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
2204 if (!nmk_gpio_chips[npct->soc->gpio_ranges[i].id]) {
2205 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
2206 return -EPROBE_DEFER;
2207 }
2208 npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[npct->soc->gpio_ranges[i].id]->chip;
2209 }
2210
2211 nmk_pinctrl_desc.pins = npct->soc->pins;
2212 nmk_pinctrl_desc.npins = npct->soc->npins;
2213 npct->dev = &pdev->dev;
2214
2215 npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct);
2216 if (!npct->pctl) {
2217 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
2218 return -EINVAL;
2219 }
2220
2221 /* We will handle a range of GPIO pins */
2222 for (i = 0; i < npct->soc->gpio_num_ranges; i++)
2223 pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]);
2224
2225 platform_set_drvdata(pdev, npct);
2226 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
2227
2228 return 0;
2229 }
2230
2231 static const struct of_device_id nmk_gpio_match[] = {
2232 { .compatible = "st,nomadik-gpio", },
2233 {}
2234 };
2235
2236 static struct platform_driver nmk_gpio_driver = {
2237 .driver = {
2238 .owner = THIS_MODULE,
2239 .name = "gpio",
2240 .of_match_table = nmk_gpio_match,
2241 },
2242 .probe = nmk_gpio_probe,
2243 };
2244
2245 static const struct platform_device_id nmk_pinctrl_id[] = {
2246 { "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
2247 { "pinctrl-db8500", PINCTRL_NMK_DB8500 },
2248 { "pinctrl-db8540", PINCTRL_NMK_DB8540 },
2249 { }
2250 };
2251
2252 static struct platform_driver nmk_pinctrl_driver = {
2253 .driver = {
2254 .owner = THIS_MODULE,
2255 .name = "pinctrl-nomadik",
2256 .of_match_table = nmk_pinctrl_match,
2257 },
2258 .probe = nmk_pinctrl_probe,
2259 .id_table = nmk_pinctrl_id,
2260 #ifdef CONFIG_PM
2261 .suspend = nmk_pinctrl_suspend,
2262 .resume = nmk_pinctrl_resume,
2263 #endif
2264 };
2265
nmk_gpio_init(void)2266 static int __init nmk_gpio_init(void)
2267 {
2268 int ret;
2269
2270 ret = platform_driver_register(&nmk_gpio_driver);
2271 if (ret)
2272 return ret;
2273 return platform_driver_register(&nmk_pinctrl_driver);
2274 }
2275
2276 core_initcall(nmk_gpio_init);
2277
2278 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
2279 MODULE_DESCRIPTION("Nomadik GPIO Driver");
2280 MODULE_LICENSE("GPL");
2281