1 /*
2 * Pinctrl data and driver for the NVIDIA Tegra114 pinmux
3 *
4 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Arthur: Pritesh Raithatha <praithatha@nvidia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/platform_device.h>
24 #include <linux/pinctrl/pinctrl.h>
25 #include <linux/pinctrl/pinmux.h>
26
27 #include "pinctrl-tegra.h"
28
29 /*
30 * Most pins affected by the pinmux can also be GPIOs. Define these first.
31 * These must match how the GPIO driver names/numbers its pins.
32 */
33 #define _GPIO(offset) (offset)
34
35 #define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
36 #define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
37 #define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2)
38 #define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3)
39 #define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4)
40 #define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5)
41 #define TEGRA_PIN_SDMMC3_CLK_PA6 _GPIO(6)
42 #define TEGRA_PIN_SDMMC3_CMD_PA7 _GPIO(7)
43 #define TEGRA_PIN_GMI_A17_PB0 _GPIO(8)
44 #define TEGRA_PIN_GMI_A18_PB1 _GPIO(9)
45 #define TEGRA_PIN_SDMMC3_DAT3_PB4 _GPIO(12)
46 #define TEGRA_PIN_SDMMC3_DAT2_PB5 _GPIO(13)
47 #define TEGRA_PIN_SDMMC3_DAT1_PB6 _GPIO(14)
48 #define TEGRA_PIN_SDMMC3_DAT0_PB7 _GPIO(15)
49 #define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16)
50 #define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18)
51 #define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19)
52 #define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20)
53 #define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21)
54 #define TEGRA_PIN_GMI_WP_N_PC7 _GPIO(23)
55 #define TEGRA_PIN_GMI_AD0_PG0 _GPIO(48)
56 #define TEGRA_PIN_GMI_AD1_PG1 _GPIO(49)
57 #define TEGRA_PIN_GMI_AD2_PG2 _GPIO(50)
58 #define TEGRA_PIN_GMI_AD3_PG3 _GPIO(51)
59 #define TEGRA_PIN_GMI_AD4_PG4 _GPIO(52)
60 #define TEGRA_PIN_GMI_AD5_PG5 _GPIO(53)
61 #define TEGRA_PIN_GMI_AD6_PG6 _GPIO(54)
62 #define TEGRA_PIN_GMI_AD7_PG7 _GPIO(55)
63 #define TEGRA_PIN_GMI_AD8_PH0 _GPIO(56)
64 #define TEGRA_PIN_GMI_AD9_PH1 _GPIO(57)
65 #define TEGRA_PIN_GMI_AD10_PH2 _GPIO(58)
66 #define TEGRA_PIN_GMI_AD11_PH3 _GPIO(59)
67 #define TEGRA_PIN_GMI_AD12_PH4 _GPIO(60)
68 #define TEGRA_PIN_GMI_AD13_PH5 _GPIO(61)
69 #define TEGRA_PIN_GMI_AD14_PH6 _GPIO(62)
70 #define TEGRA_PIN_GMI_AD15_PH7 _GPIO(63)
71 #define TEGRA_PIN_GMI_WR_N_PI0 _GPIO(64)
72 #define TEGRA_PIN_GMI_OE_N_PI1 _GPIO(65)
73 #define TEGRA_PIN_GMI_CS6_N_PI3 _GPIO(67)
74 #define TEGRA_PIN_GMI_RST_N_PI4 _GPIO(68)
75 #define TEGRA_PIN_GMI_IORDY_PI5 _GPIO(69)
76 #define TEGRA_PIN_GMI_CS7_N_PI6 _GPIO(70)
77 #define TEGRA_PIN_GMI_WAIT_PI7 _GPIO(71)
78 #define TEGRA_PIN_GMI_CS0_N_PJ0 _GPIO(72)
79 #define TEGRA_PIN_GMI_CS1_N_PJ2 _GPIO(74)
80 #define TEGRA_PIN_GMI_DQS_P_PJ3 _GPIO(75)
81 #define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77)
82 #define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78)
83 #define TEGRA_PIN_GMI_A16_PJ7 _GPIO(79)
84 #define TEGRA_PIN_GMI_ADV_N_PK0 _GPIO(80)
85 #define TEGRA_PIN_GMI_CLK_PK1 _GPIO(81)
86 #define TEGRA_PIN_GMI_CS4_N_PK2 _GPIO(82)
87 #define TEGRA_PIN_GMI_CS2_N_PK3 _GPIO(83)
88 #define TEGRA_PIN_GMI_CS3_N_PK4 _GPIO(84)
89 #define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85)
90 #define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86)
91 #define TEGRA_PIN_GMI_A19_PK7 _GPIO(87)
92 #define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104)
93 #define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105)
94 #define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106)
95 #define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107)
96 #define TEGRA_PIN_USB_VBUS_EN0_PN4 _GPIO(108)
97 #define TEGRA_PIN_USB_VBUS_EN1_PN5 _GPIO(109)
98 #define TEGRA_PIN_HDMI_INT_PN7 _GPIO(111)
99 #define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112)
100 #define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113)
101 #define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114)
102 #define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115)
103 #define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116)
104 #define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117)
105 #define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118)
106 #define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119)
107 #define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120)
108 #define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121)
109 #define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122)
110 #define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123)
111 #define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124)
112 #define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125)
113 #define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126)
114 #define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127)
115 #define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128)
116 #define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129)
117 #define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130)
118 #define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131)
119 #define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132)
120 #define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133)
121 #define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134)
122 #define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135)
123 #define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136)
124 #define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137)
125 #define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138)
126 #define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139)
127 #define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140)
128 #define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141)
129 #define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142)
130 #define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143)
131 #define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144)
132 #define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145)
133 #define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146)
134 #define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157)
135 #define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158)
136 #define TEGRA_PIN_SDMMC4_CMD_PT7 _GPIO(159)
137 #define TEGRA_PIN_PU0 _GPIO(160)
138 #define TEGRA_PIN_PU1 _GPIO(161)
139 #define TEGRA_PIN_PU2 _GPIO(162)
140 #define TEGRA_PIN_PU3 _GPIO(163)
141 #define TEGRA_PIN_PU4 _GPIO(164)
142 #define TEGRA_PIN_PU5 _GPIO(165)
143 #define TEGRA_PIN_PU6 _GPIO(166)
144 #define TEGRA_PIN_PV0 _GPIO(168)
145 #define TEGRA_PIN_PV1 _GPIO(169)
146 #define TEGRA_PIN_SDMMC3_CD_N_PV2 _GPIO(170)
147 #define TEGRA_PIN_SDMMC1_WP_N_PV3 _GPIO(171)
148 #define TEGRA_PIN_DDC_SCL_PV4 _GPIO(172)
149 #define TEGRA_PIN_DDC_SDA_PV5 _GPIO(173)
150 #define TEGRA_PIN_GPIO_W2_AUD_PW2 _GPIO(178)
151 #define TEGRA_PIN_GPIO_W3_AUD_PW3 _GPIO(179)
152 #define TEGRA_PIN_CLK1_OUT_PW4 _GPIO(180)
153 #define TEGRA_PIN_CLK2_OUT_PW5 _GPIO(181)
154 #define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182)
155 #define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183)
156 #define TEGRA_PIN_DVFS_PWM_PX0 _GPIO(184)
157 #define TEGRA_PIN_GPIO_X1_AUD_PX1 _GPIO(185)
158 #define TEGRA_PIN_DVFS_CLK_PX2 _GPIO(186)
159 #define TEGRA_PIN_GPIO_X3_AUD_PX3 _GPIO(187)
160 #define TEGRA_PIN_GPIO_X4_AUD_PX4 _GPIO(188)
161 #define TEGRA_PIN_GPIO_X5_AUD_PX5 _GPIO(189)
162 #define TEGRA_PIN_GPIO_X6_AUD_PX6 _GPIO(190)
163 #define TEGRA_PIN_GPIO_X7_AUD_PX7 _GPIO(191)
164 #define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192)
165 #define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193)
166 #define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194)
167 #define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195)
168 #define TEGRA_PIN_SDMMC1_DAT3_PY4 _GPIO(196)
169 #define TEGRA_PIN_SDMMC1_DAT2_PY5 _GPIO(197)
170 #define TEGRA_PIN_SDMMC1_DAT1_PY6 _GPIO(198)
171 #define TEGRA_PIN_SDMMC1_DAT0_PY7 _GPIO(199)
172 #define TEGRA_PIN_SDMMC1_CLK_PZ0 _GPIO(200)
173 #define TEGRA_PIN_SDMMC1_CMD_PZ1 _GPIO(201)
174 #define TEGRA_PIN_SYS_CLK_REQ_PZ5 _GPIO(205)
175 #define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206)
176 #define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207)
177 #define TEGRA_PIN_SDMMC4_DAT0_PAA0 _GPIO(208)
178 #define TEGRA_PIN_SDMMC4_DAT1_PAA1 _GPIO(209)
179 #define TEGRA_PIN_SDMMC4_DAT2_PAA2 _GPIO(210)
180 #define TEGRA_PIN_SDMMC4_DAT3_PAA3 _GPIO(211)
181 #define TEGRA_PIN_SDMMC4_DAT4_PAA4 _GPIO(212)
182 #define TEGRA_PIN_SDMMC4_DAT5_PAA5 _GPIO(213)
183 #define TEGRA_PIN_SDMMC4_DAT6_PAA6 _GPIO(214)
184 #define TEGRA_PIN_SDMMC4_DAT7_PAA7 _GPIO(215)
185 #define TEGRA_PIN_PBB0 _GPIO(216)
186 #define TEGRA_PIN_CAM_I2C_SCL_PBB1 _GPIO(217)
187 #define TEGRA_PIN_CAM_I2C_SDA_PBB2 _GPIO(218)
188 #define TEGRA_PIN_PBB3 _GPIO(219)
189 #define TEGRA_PIN_PBB4 _GPIO(220)
190 #define TEGRA_PIN_PBB5 _GPIO(221)
191 #define TEGRA_PIN_PBB6 _GPIO(222)
192 #define TEGRA_PIN_PBB7 _GPIO(223)
193 #define TEGRA_PIN_CAM_MCLK_PCC0 _GPIO(224)
194 #define TEGRA_PIN_PCC1 _GPIO(225)
195 #define TEGRA_PIN_PCC2 _GPIO(226)
196 #define TEGRA_PIN_SDMMC4_CLK_PCC4 _GPIO(228)
197 #define TEGRA_PIN_CLK2_REQ_PCC5 _GPIO(229)
198 #define TEGRA_PIN_CLK3_OUT_PEE0 _GPIO(240)
199 #define TEGRA_PIN_CLK3_REQ_PEE1 _GPIO(241)
200 #define TEGRA_PIN_CLK1_REQ_PEE2 _GPIO(242)
201 #define TEGRA_PIN_HDMI_CEC_PEE3 _GPIO(243)
202 #define TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4 _GPIO(244)
203 #define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 _GPIO(245)
204
205 /* All non-GPIO pins follow */
206 #define NUM_GPIOS (TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 + 1)
207 #define _PIN(offset) (NUM_GPIOS + (offset))
208
209 /* Non-GPIO pins */
210 #define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
211 #define TEGRA_PIN_CPU_PWR_REQ _PIN(1)
212 #define TEGRA_PIN_PWR_INT_N _PIN(2)
213 #define TEGRA_PIN_RESET_OUT_N _PIN(3)
214 #define TEGRA_PIN_OWR _PIN(4)
215
216 static const struct pinctrl_pin_desc tegra114_pins[] = {
217 PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
218 PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
219 PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
220 PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
221 PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
222 PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
223 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
224 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
225 PINCTRL_PIN(TEGRA_PIN_GMI_A17_PB0, "GMI_A17 PB0"),
226 PINCTRL_PIN(TEGRA_PIN_GMI_A18_PB1, "GMI_A18 PB1"),
227 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
228 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
229 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
230 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
231 PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
232 PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
233 PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
234 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
235 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
236 PINCTRL_PIN(TEGRA_PIN_GMI_WP_N_PC7, "GMI_WP_N PC7"),
237 PINCTRL_PIN(TEGRA_PIN_GMI_AD0_PG0, "GMI_AD0 PG0"),
238 PINCTRL_PIN(TEGRA_PIN_GMI_AD1_PG1, "GMI_AD1 PG1"),
239 PINCTRL_PIN(TEGRA_PIN_GMI_AD2_PG2, "GMI_AD2 PG2"),
240 PINCTRL_PIN(TEGRA_PIN_GMI_AD3_PG3, "GMI_AD3 PG3"),
241 PINCTRL_PIN(TEGRA_PIN_GMI_AD4_PG4, "GMI_AD4 PG4"),
242 PINCTRL_PIN(TEGRA_PIN_GMI_AD5_PG5, "GMI_AD5 PG5"),
243 PINCTRL_PIN(TEGRA_PIN_GMI_AD6_PG6, "GMI_AD6 PG6"),
244 PINCTRL_PIN(TEGRA_PIN_GMI_AD7_PG7, "GMI_AD7 PG7"),
245 PINCTRL_PIN(TEGRA_PIN_GMI_AD8_PH0, "GMI_AD8 PH0"),
246 PINCTRL_PIN(TEGRA_PIN_GMI_AD9_PH1, "GMI_AD9 PH1"),
247 PINCTRL_PIN(TEGRA_PIN_GMI_AD10_PH2, "GMI_AD10 PH2"),
248 PINCTRL_PIN(TEGRA_PIN_GMI_AD11_PH3, "GMI_AD11 PH3"),
249 PINCTRL_PIN(TEGRA_PIN_GMI_AD12_PH4, "GMI_AD12 PH4"),
250 PINCTRL_PIN(TEGRA_PIN_GMI_AD13_PH5, "GMI_AD13 PH5"),
251 PINCTRL_PIN(TEGRA_PIN_GMI_AD14_PH6, "GMI_AD14 PH6"),
252 PINCTRL_PIN(TEGRA_PIN_GMI_AD15_PH7, "GMI_AD15 PH7"),
253 PINCTRL_PIN(TEGRA_PIN_GMI_WR_N_PI0, "GMI_WR_N PI0"),
254 PINCTRL_PIN(TEGRA_PIN_GMI_OE_N_PI1, "GMI_OE_N PI1"),
255 PINCTRL_PIN(TEGRA_PIN_GMI_CS6_N_PI3, "GMI_CS6_N PI3"),
256 PINCTRL_PIN(TEGRA_PIN_GMI_RST_N_PI4, "GMI_RST_N PI4"),
257 PINCTRL_PIN(TEGRA_PIN_GMI_IORDY_PI5, "GMI_IORDY PI5"),
258 PINCTRL_PIN(TEGRA_PIN_GMI_CS7_N_PI6, "GMI_CS7_N PI6"),
259 PINCTRL_PIN(TEGRA_PIN_GMI_WAIT_PI7, "GMI_WAIT PI7"),
260 PINCTRL_PIN(TEGRA_PIN_GMI_CS0_N_PJ0, "GMI_CS0_N PJ0"),
261 PINCTRL_PIN(TEGRA_PIN_GMI_CS1_N_PJ2, "GMI_CS1_N PJ2"),
262 PINCTRL_PIN(TEGRA_PIN_GMI_DQS_P_PJ3, "GMI_DQS_P PJ3"),
263 PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
264 PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
265 PINCTRL_PIN(TEGRA_PIN_GMI_A16_PJ7, "GMI_A16 PJ7"),
266 PINCTRL_PIN(TEGRA_PIN_GMI_ADV_N_PK0, "GMI_ADV_N PK0"),
267 PINCTRL_PIN(TEGRA_PIN_GMI_CLK_PK1, "GMI_CLK PK1"),
268 PINCTRL_PIN(TEGRA_PIN_GMI_CS4_N_PK2, "GMI_CS4_N PK2"),
269 PINCTRL_PIN(TEGRA_PIN_GMI_CS2_N_PK3, "GMI_CS2_N PK3"),
270 PINCTRL_PIN(TEGRA_PIN_GMI_CS3_N_PK4, "GMI_CS3_N PK4"),
271 PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
272 PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
273 PINCTRL_PIN(TEGRA_PIN_GMI_A19_PK7, "GMI_A19 PK7"),
274 PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
275 PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
276 PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
277 PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
278 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PN4, "USB_VBUS_EN0 PN4"),
279 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PN5, "USB_VBUS_EN1 PN5"),
280 PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
281 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
282 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
283 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
284 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
285 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
286 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
287 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
288 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
289 PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
290 PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
291 PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
292 PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
293 PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
294 PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
295 PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
296 PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
297 PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
298 PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
299 PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
300 PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
301 PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
302 PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
303 PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
304 PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
305 PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
306 PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
307 PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
308 PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
309 PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
310 PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
311 PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
312 PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
313 PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
314 PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
315 PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
316 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
317 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
318 PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
319 PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
320 PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
321 PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
322 PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
323 PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
324 PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
325 PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
326 PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
327 PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
328 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CD_N_PV2, "SDMMC3_CD_N PV2"),
329 PINCTRL_PIN(TEGRA_PIN_SDMMC1_WP_N_PV3, "SDMMC1_WP_N PV3"),
330 PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
331 PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
332 PINCTRL_PIN(TEGRA_PIN_GPIO_W2_AUD_PW2, "GPIO_W2_AUD PW2"),
333 PINCTRL_PIN(TEGRA_PIN_GPIO_W3_AUD_PW3, "GPIO_W3_AUD PW3"),
334 PINCTRL_PIN(TEGRA_PIN_CLK1_OUT_PW4, "CLK1_OUT PW4"),
335 PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
336 PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
337 PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
338 PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PX0, "DVFS_PWM PX0"),
339 PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PX1, "GPIO_X1_AUD PX1"),
340 PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PX2, "DVFS_CLK PX2"),
341 PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PX3, "GPIO_X3_AUD PX3"),
342 PINCTRL_PIN(TEGRA_PIN_GPIO_X4_AUD_PX4, "GPIO_X4_AUD PX4"),
343 PINCTRL_PIN(TEGRA_PIN_GPIO_X5_AUD_PX5, "GPIO_X5_AUD PX5"),
344 PINCTRL_PIN(TEGRA_PIN_GPIO_X6_AUD_PX6, "GPIO_X6_AUD PX6"),
345 PINCTRL_PIN(TEGRA_PIN_GPIO_X7_AUD_PX7, "GPIO_X7_AUD PX7"),
346 PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
347 PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
348 PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
349 PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
350 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
351 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
352 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
353 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
354 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
355 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
356 PINCTRL_PIN(TEGRA_PIN_SYS_CLK_REQ_PZ5, "SYS_CLK_REQ PZ5"),
357 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
358 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
359 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
360 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
361 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
362 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
363 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
364 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
365 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
366 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
367 PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
368 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
369 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
370 PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
371 PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
372 PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
373 PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
374 PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
375 PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
376 PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
377 PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
378 PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
379 PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
380 PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
381 PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
382 PINCTRL_PIN(TEGRA_PIN_CLK1_REQ_PEE2, "CLK1_REQ PEE2"),
383 PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
384 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"),
385 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"),
386 PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
387 PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
388 PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
389 PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
390 PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
391 };
392
393 static const unsigned clk_32k_out_pa0_pins[] = {
394 TEGRA_PIN_CLK_32K_OUT_PA0,
395 };
396
397 static const unsigned uart3_cts_n_pa1_pins[] = {
398 TEGRA_PIN_UART3_CTS_N_PA1,
399 };
400
401 static const unsigned dap2_fs_pa2_pins[] = {
402 TEGRA_PIN_DAP2_FS_PA2,
403 };
404
405 static const unsigned dap2_sclk_pa3_pins[] = {
406 TEGRA_PIN_DAP2_SCLK_PA3,
407 };
408
409 static const unsigned dap2_din_pa4_pins[] = {
410 TEGRA_PIN_DAP2_DIN_PA4,
411 };
412
413 static const unsigned dap2_dout_pa5_pins[] = {
414 TEGRA_PIN_DAP2_DOUT_PA5,
415 };
416
417 static const unsigned sdmmc3_clk_pa6_pins[] = {
418 TEGRA_PIN_SDMMC3_CLK_PA6,
419 };
420
421 static const unsigned sdmmc3_cmd_pa7_pins[] = {
422 TEGRA_PIN_SDMMC3_CMD_PA7,
423 };
424
425 static const unsigned gmi_a17_pb0_pins[] = {
426 TEGRA_PIN_GMI_A17_PB0,
427 };
428
429 static const unsigned gmi_a18_pb1_pins[] = {
430 TEGRA_PIN_GMI_A18_PB1,
431 };
432
433 static const unsigned sdmmc3_dat3_pb4_pins[] = {
434 TEGRA_PIN_SDMMC3_DAT3_PB4,
435 };
436
437 static const unsigned sdmmc3_dat2_pb5_pins[] = {
438 TEGRA_PIN_SDMMC3_DAT2_PB5,
439 };
440
441 static const unsigned sdmmc3_dat1_pb6_pins[] = {
442 TEGRA_PIN_SDMMC3_DAT1_PB6,
443 };
444
445 static const unsigned sdmmc3_dat0_pb7_pins[] = {
446 TEGRA_PIN_SDMMC3_DAT0_PB7,
447 };
448
449 static const unsigned uart3_rts_n_pc0_pins[] = {
450 TEGRA_PIN_UART3_RTS_N_PC0,
451 };
452
453 static const unsigned uart2_txd_pc2_pins[] = {
454 TEGRA_PIN_UART2_TXD_PC2,
455 };
456
457 static const unsigned uart2_rxd_pc3_pins[] = {
458 TEGRA_PIN_UART2_RXD_PC3,
459 };
460
461 static const unsigned gen1_i2c_scl_pc4_pins[] = {
462 TEGRA_PIN_GEN1_I2C_SCL_PC4,
463 };
464
465 static const unsigned gen1_i2c_sda_pc5_pins[] = {
466 TEGRA_PIN_GEN1_I2C_SDA_PC5,
467 };
468
469 static const unsigned gmi_wp_n_pc7_pins[] = {
470 TEGRA_PIN_GMI_WP_N_PC7,
471 };
472
473 static const unsigned gmi_ad0_pg0_pins[] = {
474 TEGRA_PIN_GMI_AD0_PG0,
475 };
476
477 static const unsigned gmi_ad1_pg1_pins[] = {
478 TEGRA_PIN_GMI_AD1_PG1,
479 };
480
481 static const unsigned gmi_ad2_pg2_pins[] = {
482 TEGRA_PIN_GMI_AD2_PG2,
483 };
484
485 static const unsigned gmi_ad3_pg3_pins[] = {
486 TEGRA_PIN_GMI_AD3_PG3,
487 };
488
489 static const unsigned gmi_ad4_pg4_pins[] = {
490 TEGRA_PIN_GMI_AD4_PG4,
491 };
492
493 static const unsigned gmi_ad5_pg5_pins[] = {
494 TEGRA_PIN_GMI_AD5_PG5,
495 };
496
497 static const unsigned gmi_ad6_pg6_pins[] = {
498 TEGRA_PIN_GMI_AD6_PG6,
499 };
500
501 static const unsigned gmi_ad7_pg7_pins[] = {
502 TEGRA_PIN_GMI_AD7_PG7,
503 };
504
505 static const unsigned gmi_ad8_ph0_pins[] = {
506 TEGRA_PIN_GMI_AD8_PH0,
507 };
508
509 static const unsigned gmi_ad9_ph1_pins[] = {
510 TEGRA_PIN_GMI_AD9_PH1,
511 };
512
513 static const unsigned gmi_ad10_ph2_pins[] = {
514 TEGRA_PIN_GMI_AD10_PH2,
515 };
516
517 static const unsigned gmi_ad11_ph3_pins[] = {
518 TEGRA_PIN_GMI_AD11_PH3,
519 };
520
521 static const unsigned gmi_ad12_ph4_pins[] = {
522 TEGRA_PIN_GMI_AD12_PH4,
523 };
524
525 static const unsigned gmi_ad13_ph5_pins[] = {
526 TEGRA_PIN_GMI_AD13_PH5,
527 };
528
529 static const unsigned gmi_ad14_ph6_pins[] = {
530 TEGRA_PIN_GMI_AD14_PH6,
531 };
532
533 static const unsigned gmi_ad15_ph7_pins[] = {
534 TEGRA_PIN_GMI_AD15_PH7,
535 };
536
537 static const unsigned gmi_wr_n_pi0_pins[] = {
538 TEGRA_PIN_GMI_WR_N_PI0,
539 };
540
541 static const unsigned gmi_oe_n_pi1_pins[] = {
542 TEGRA_PIN_GMI_OE_N_PI1,
543 };
544
545 static const unsigned gmi_cs6_n_pi3_pins[] = {
546 TEGRA_PIN_GMI_CS6_N_PI3,
547 };
548
549 static const unsigned gmi_rst_n_pi4_pins[] = {
550 TEGRA_PIN_GMI_RST_N_PI4,
551 };
552
553 static const unsigned gmi_iordy_pi5_pins[] = {
554 TEGRA_PIN_GMI_IORDY_PI5,
555 };
556
557 static const unsigned gmi_cs7_n_pi6_pins[] = {
558 TEGRA_PIN_GMI_CS7_N_PI6,
559 };
560
561 static const unsigned gmi_wait_pi7_pins[] = {
562 TEGRA_PIN_GMI_WAIT_PI7,
563 };
564
565 static const unsigned gmi_cs0_n_pj0_pins[] = {
566 TEGRA_PIN_GMI_CS0_N_PJ0,
567 };
568
569 static const unsigned gmi_cs1_n_pj2_pins[] = {
570 TEGRA_PIN_GMI_CS1_N_PJ2,
571 };
572
573 static const unsigned gmi_dqs_p_pj3_pins[] = {
574 TEGRA_PIN_GMI_DQS_P_PJ3,
575 };
576
577 static const unsigned uart2_cts_n_pj5_pins[] = {
578 TEGRA_PIN_UART2_CTS_N_PJ5,
579 };
580
581 static const unsigned uart2_rts_n_pj6_pins[] = {
582 TEGRA_PIN_UART2_RTS_N_PJ6,
583 };
584
585 static const unsigned gmi_a16_pj7_pins[] = {
586 TEGRA_PIN_GMI_A16_PJ7,
587 };
588
589 static const unsigned gmi_adv_n_pk0_pins[] = {
590 TEGRA_PIN_GMI_ADV_N_PK0,
591 };
592
593 static const unsigned gmi_clk_pk1_pins[] = {
594 TEGRA_PIN_GMI_CLK_PK1,
595 };
596
597 static const unsigned gmi_cs4_n_pk2_pins[] = {
598 TEGRA_PIN_GMI_CS4_N_PK2,
599 };
600
601 static const unsigned gmi_cs2_n_pk3_pins[] = {
602 TEGRA_PIN_GMI_CS2_N_PK3,
603 };
604
605 static const unsigned gmi_cs3_n_pk4_pins[] = {
606 TEGRA_PIN_GMI_CS3_N_PK4,
607 };
608
609 static const unsigned spdif_out_pk5_pins[] = {
610 TEGRA_PIN_SPDIF_OUT_PK5,
611 };
612
613 static const unsigned spdif_in_pk6_pins[] = {
614 TEGRA_PIN_SPDIF_IN_PK6,
615 };
616
617 static const unsigned gmi_a19_pk7_pins[] = {
618 TEGRA_PIN_GMI_A19_PK7,
619 };
620
621 static const unsigned dap1_fs_pn0_pins[] = {
622 TEGRA_PIN_DAP1_FS_PN0,
623 };
624
625 static const unsigned dap1_din_pn1_pins[] = {
626 TEGRA_PIN_DAP1_DIN_PN1,
627 };
628
629 static const unsigned dap1_dout_pn2_pins[] = {
630 TEGRA_PIN_DAP1_DOUT_PN2,
631 };
632
633 static const unsigned dap1_sclk_pn3_pins[] = {
634 TEGRA_PIN_DAP1_SCLK_PN3,
635 };
636
637 static const unsigned usb_vbus_en0_pn4_pins[] = {
638 TEGRA_PIN_USB_VBUS_EN0_PN4,
639 };
640
641 static const unsigned usb_vbus_en1_pn5_pins[] = {
642 TEGRA_PIN_USB_VBUS_EN1_PN5,
643 };
644
645 static const unsigned hdmi_int_pn7_pins[] = {
646 TEGRA_PIN_HDMI_INT_PN7,
647 };
648
649 static const unsigned ulpi_data7_po0_pins[] = {
650 TEGRA_PIN_ULPI_DATA7_PO0,
651 };
652
653 static const unsigned ulpi_data0_po1_pins[] = {
654 TEGRA_PIN_ULPI_DATA0_PO1,
655 };
656
657 static const unsigned ulpi_data1_po2_pins[] = {
658 TEGRA_PIN_ULPI_DATA1_PO2,
659 };
660
661 static const unsigned ulpi_data2_po3_pins[] = {
662 TEGRA_PIN_ULPI_DATA2_PO3,
663 };
664
665 static const unsigned ulpi_data3_po4_pins[] = {
666 TEGRA_PIN_ULPI_DATA3_PO4,
667 };
668
669 static const unsigned ulpi_data4_po5_pins[] = {
670 TEGRA_PIN_ULPI_DATA4_PO5,
671 };
672
673 static const unsigned ulpi_data5_po6_pins[] = {
674 TEGRA_PIN_ULPI_DATA5_PO6,
675 };
676
677 static const unsigned ulpi_data6_po7_pins[] = {
678 TEGRA_PIN_ULPI_DATA6_PO7,
679 };
680
681 static const unsigned dap3_fs_pp0_pins[] = {
682 TEGRA_PIN_DAP3_FS_PP0,
683 };
684
685 static const unsigned dap3_din_pp1_pins[] = {
686 TEGRA_PIN_DAP3_DIN_PP1,
687 };
688
689 static const unsigned dap3_dout_pp2_pins[] = {
690 TEGRA_PIN_DAP3_DOUT_PP2,
691 };
692
693 static const unsigned dap3_sclk_pp3_pins[] = {
694 TEGRA_PIN_DAP3_SCLK_PP3,
695 };
696
697 static const unsigned dap4_fs_pp4_pins[] = {
698 TEGRA_PIN_DAP4_FS_PP4,
699 };
700
701 static const unsigned dap4_din_pp5_pins[] = {
702 TEGRA_PIN_DAP4_DIN_PP5,
703 };
704
705 static const unsigned dap4_dout_pp6_pins[] = {
706 TEGRA_PIN_DAP4_DOUT_PP6,
707 };
708
709 static const unsigned dap4_sclk_pp7_pins[] = {
710 TEGRA_PIN_DAP4_SCLK_PP7,
711 };
712
713 static const unsigned kb_col0_pq0_pins[] = {
714 TEGRA_PIN_KB_COL0_PQ0,
715 };
716
717 static const unsigned kb_col1_pq1_pins[] = {
718 TEGRA_PIN_KB_COL1_PQ1,
719 };
720
721 static const unsigned kb_col2_pq2_pins[] = {
722 TEGRA_PIN_KB_COL2_PQ2,
723 };
724
725 static const unsigned kb_col3_pq3_pins[] = {
726 TEGRA_PIN_KB_COL3_PQ3,
727 };
728
729 static const unsigned kb_col4_pq4_pins[] = {
730 TEGRA_PIN_KB_COL4_PQ4,
731 };
732
733 static const unsigned kb_col5_pq5_pins[] = {
734 TEGRA_PIN_KB_COL5_PQ5,
735 };
736
737 static const unsigned kb_col6_pq6_pins[] = {
738 TEGRA_PIN_KB_COL6_PQ6,
739 };
740
741 static const unsigned kb_col7_pq7_pins[] = {
742 TEGRA_PIN_KB_COL7_PQ7,
743 };
744
745 static const unsigned kb_row0_pr0_pins[] = {
746 TEGRA_PIN_KB_ROW0_PR0,
747 };
748
749 static const unsigned kb_row1_pr1_pins[] = {
750 TEGRA_PIN_KB_ROW1_PR1,
751 };
752
753 static const unsigned kb_row2_pr2_pins[] = {
754 TEGRA_PIN_KB_ROW2_PR2,
755 };
756
757 static const unsigned kb_row3_pr3_pins[] = {
758 TEGRA_PIN_KB_ROW3_PR3,
759 };
760
761 static const unsigned kb_row4_pr4_pins[] = {
762 TEGRA_PIN_KB_ROW4_PR4,
763 };
764
765 static const unsigned kb_row5_pr5_pins[] = {
766 TEGRA_PIN_KB_ROW5_PR5,
767 };
768
769 static const unsigned kb_row6_pr6_pins[] = {
770 TEGRA_PIN_KB_ROW6_PR6,
771 };
772
773 static const unsigned kb_row7_pr7_pins[] = {
774 TEGRA_PIN_KB_ROW7_PR7,
775 };
776
777 static const unsigned kb_row8_ps0_pins[] = {
778 TEGRA_PIN_KB_ROW8_PS0,
779 };
780
781 static const unsigned kb_row9_ps1_pins[] = {
782 TEGRA_PIN_KB_ROW9_PS1,
783 };
784
785 static const unsigned kb_row10_ps2_pins[] = {
786 TEGRA_PIN_KB_ROW10_PS2,
787 };
788
789 static const unsigned gen2_i2c_scl_pt5_pins[] = {
790 TEGRA_PIN_GEN2_I2C_SCL_PT5,
791 };
792
793 static const unsigned gen2_i2c_sda_pt6_pins[] = {
794 TEGRA_PIN_GEN2_I2C_SDA_PT6,
795 };
796
797 static const unsigned sdmmc4_cmd_pt7_pins[] = {
798 TEGRA_PIN_SDMMC4_CMD_PT7,
799 };
800
801 static const unsigned pu0_pins[] = {
802 TEGRA_PIN_PU0,
803 };
804
805 static const unsigned pu1_pins[] = {
806 TEGRA_PIN_PU1,
807 };
808
809 static const unsigned pu2_pins[] = {
810 TEGRA_PIN_PU2,
811 };
812
813 static const unsigned pu3_pins[] = {
814 TEGRA_PIN_PU3,
815 };
816
817 static const unsigned pu4_pins[] = {
818 TEGRA_PIN_PU4,
819 };
820
821 static const unsigned pu5_pins[] = {
822 TEGRA_PIN_PU5,
823 };
824
825 static const unsigned pu6_pins[] = {
826 TEGRA_PIN_PU6,
827 };
828
829 static const unsigned pv0_pins[] = {
830 TEGRA_PIN_PV0,
831 };
832
833 static const unsigned pv1_pins[] = {
834 TEGRA_PIN_PV1,
835 };
836
837 static const unsigned sdmmc3_cd_n_pv2_pins[] = {
838 TEGRA_PIN_SDMMC3_CD_N_PV2,
839 };
840
841 static const unsigned sdmmc1_wp_n_pv3_pins[] = {
842 TEGRA_PIN_SDMMC1_WP_N_PV3,
843 };
844
845 static const unsigned ddc_scl_pv4_pins[] = {
846 TEGRA_PIN_DDC_SCL_PV4,
847 };
848
849 static const unsigned ddc_sda_pv5_pins[] = {
850 TEGRA_PIN_DDC_SDA_PV5,
851 };
852
853 static const unsigned gpio_w2_aud_pw2_pins[] = {
854 TEGRA_PIN_GPIO_W2_AUD_PW2,
855 };
856
857 static const unsigned gpio_w3_aud_pw3_pins[] = {
858 TEGRA_PIN_GPIO_W3_AUD_PW3,
859 };
860
861 static const unsigned clk1_out_pw4_pins[] = {
862 TEGRA_PIN_CLK1_OUT_PW4,
863 };
864
865 static const unsigned clk2_out_pw5_pins[] = {
866 TEGRA_PIN_CLK2_OUT_PW5,
867 };
868
869 static const unsigned uart3_txd_pw6_pins[] = {
870 TEGRA_PIN_UART3_TXD_PW6,
871 };
872
873 static const unsigned uart3_rxd_pw7_pins[] = {
874 TEGRA_PIN_UART3_RXD_PW7,
875 };
876
877 static const unsigned dvfs_pwm_px0_pins[] = {
878 TEGRA_PIN_DVFS_PWM_PX0,
879 };
880
881 static const unsigned gpio_x1_aud_px1_pins[] = {
882 TEGRA_PIN_GPIO_X1_AUD_PX1,
883 };
884
885 static const unsigned dvfs_clk_px2_pins[] = {
886 TEGRA_PIN_DVFS_CLK_PX2,
887 };
888
889 static const unsigned gpio_x3_aud_px3_pins[] = {
890 TEGRA_PIN_GPIO_X3_AUD_PX3,
891 };
892
893 static const unsigned gpio_x4_aud_px4_pins[] = {
894 TEGRA_PIN_GPIO_X4_AUD_PX4,
895 };
896
897 static const unsigned gpio_x5_aud_px5_pins[] = {
898 TEGRA_PIN_GPIO_X5_AUD_PX5,
899 };
900
901 static const unsigned gpio_x6_aud_px6_pins[] = {
902 TEGRA_PIN_GPIO_X6_AUD_PX6,
903 };
904
905 static const unsigned gpio_x7_aud_px7_pins[] = {
906 TEGRA_PIN_GPIO_X7_AUD_PX7,
907 };
908
909 static const unsigned ulpi_clk_py0_pins[] = {
910 TEGRA_PIN_ULPI_CLK_PY0,
911 };
912
913 static const unsigned ulpi_dir_py1_pins[] = {
914 TEGRA_PIN_ULPI_DIR_PY1,
915 };
916
917 static const unsigned ulpi_nxt_py2_pins[] = {
918 TEGRA_PIN_ULPI_NXT_PY2,
919 };
920
921 static const unsigned ulpi_stp_py3_pins[] = {
922 TEGRA_PIN_ULPI_STP_PY3,
923 };
924
925 static const unsigned sdmmc1_dat3_py4_pins[] = {
926 TEGRA_PIN_SDMMC1_DAT3_PY4,
927 };
928
929 static const unsigned sdmmc1_dat2_py5_pins[] = {
930 TEGRA_PIN_SDMMC1_DAT2_PY5,
931 };
932
933 static const unsigned sdmmc1_dat1_py6_pins[] = {
934 TEGRA_PIN_SDMMC1_DAT1_PY6,
935 };
936
937 static const unsigned sdmmc1_dat0_py7_pins[] = {
938 TEGRA_PIN_SDMMC1_DAT0_PY7,
939 };
940
941 static const unsigned sdmmc1_clk_pz0_pins[] = {
942 TEGRA_PIN_SDMMC1_CLK_PZ0,
943 };
944
945 static const unsigned sdmmc1_cmd_pz1_pins[] = {
946 TEGRA_PIN_SDMMC1_CMD_PZ1,
947 };
948
949 static const unsigned sys_clk_req_pz5_pins[] = {
950 TEGRA_PIN_SYS_CLK_REQ_PZ5,
951 };
952
953 static const unsigned pwr_i2c_scl_pz6_pins[] = {
954 TEGRA_PIN_PWR_I2C_SCL_PZ6,
955 };
956
957 static const unsigned pwr_i2c_sda_pz7_pins[] = {
958 TEGRA_PIN_PWR_I2C_SDA_PZ7,
959 };
960
961 static const unsigned sdmmc4_dat0_paa0_pins[] = {
962 TEGRA_PIN_SDMMC4_DAT0_PAA0,
963 };
964
965 static const unsigned sdmmc4_dat1_paa1_pins[] = {
966 TEGRA_PIN_SDMMC4_DAT1_PAA1,
967 };
968
969 static const unsigned sdmmc4_dat2_paa2_pins[] = {
970 TEGRA_PIN_SDMMC4_DAT2_PAA2,
971 };
972
973 static const unsigned sdmmc4_dat3_paa3_pins[] = {
974 TEGRA_PIN_SDMMC4_DAT3_PAA3,
975 };
976
977 static const unsigned sdmmc4_dat4_paa4_pins[] = {
978 TEGRA_PIN_SDMMC4_DAT4_PAA4,
979 };
980
981 static const unsigned sdmmc4_dat5_paa5_pins[] = {
982 TEGRA_PIN_SDMMC4_DAT5_PAA5,
983 };
984
985 static const unsigned sdmmc4_dat6_paa6_pins[] = {
986 TEGRA_PIN_SDMMC4_DAT6_PAA6,
987 };
988
989 static const unsigned sdmmc4_dat7_paa7_pins[] = {
990 TEGRA_PIN_SDMMC4_DAT7_PAA7,
991 };
992
993 static const unsigned pbb0_pins[] = {
994 TEGRA_PIN_PBB0,
995 };
996
997 static const unsigned cam_i2c_scl_pbb1_pins[] = {
998 TEGRA_PIN_CAM_I2C_SCL_PBB1,
999 };
1000
1001 static const unsigned cam_i2c_sda_pbb2_pins[] = {
1002 TEGRA_PIN_CAM_I2C_SDA_PBB2,
1003 };
1004
1005 static const unsigned pbb3_pins[] = {
1006 TEGRA_PIN_PBB3,
1007 };
1008
1009 static const unsigned pbb4_pins[] = {
1010 TEGRA_PIN_PBB4,
1011 };
1012
1013 static const unsigned pbb5_pins[] = {
1014 TEGRA_PIN_PBB5,
1015 };
1016
1017 static const unsigned pbb6_pins[] = {
1018 TEGRA_PIN_PBB6,
1019 };
1020
1021 static const unsigned pbb7_pins[] = {
1022 TEGRA_PIN_PBB7,
1023 };
1024
1025 static const unsigned cam_mclk_pcc0_pins[] = {
1026 TEGRA_PIN_CAM_MCLK_PCC0,
1027 };
1028
1029 static const unsigned pcc1_pins[] = {
1030 TEGRA_PIN_PCC1,
1031 };
1032
1033 static const unsigned pcc2_pins[] = {
1034 TEGRA_PIN_PCC2,
1035 };
1036
1037 static const unsigned sdmmc4_clk_pcc4_pins[] = {
1038 TEGRA_PIN_SDMMC4_CLK_PCC4,
1039 };
1040
1041 static const unsigned clk2_req_pcc5_pins[] = {
1042 TEGRA_PIN_CLK2_REQ_PCC5,
1043 };
1044
1045 static const unsigned clk3_out_pee0_pins[] = {
1046 TEGRA_PIN_CLK3_OUT_PEE0,
1047 };
1048
1049 static const unsigned clk3_req_pee1_pins[] = {
1050 TEGRA_PIN_CLK3_REQ_PEE1,
1051 };
1052
1053 static const unsigned clk1_req_pee2_pins[] = {
1054 TEGRA_PIN_CLK1_REQ_PEE2,
1055 };
1056
1057 static const unsigned hdmi_cec_pee3_pins[] = {
1058 TEGRA_PIN_HDMI_CEC_PEE3,
1059 };
1060
1061 static const unsigned sdmmc3_clk_lb_out_pee4_pins[] = {
1062 TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
1063 };
1064
1065 static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = {
1066 TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1067 };
1068
1069 static const unsigned core_pwr_req_pins[] = {
1070 TEGRA_PIN_CORE_PWR_REQ,
1071 };
1072
1073 static const unsigned cpu_pwr_req_pins[] = {
1074 TEGRA_PIN_CPU_PWR_REQ,
1075 };
1076
1077 static const unsigned owr_pins[] = {
1078 TEGRA_PIN_OWR,
1079 };
1080
1081 static const unsigned pwr_int_n_pins[] = {
1082 TEGRA_PIN_PWR_INT_N,
1083 };
1084
1085 static const unsigned reset_out_n_pins[] = {
1086 TEGRA_PIN_RESET_OUT_N,
1087 };
1088
1089 static const unsigned drive_ao1_pins[] = {
1090 TEGRA_PIN_KB_ROW0_PR0,
1091 TEGRA_PIN_KB_ROW1_PR1,
1092 TEGRA_PIN_KB_ROW2_PR2,
1093 TEGRA_PIN_KB_ROW3_PR3,
1094 TEGRA_PIN_KB_ROW4_PR4,
1095 TEGRA_PIN_KB_ROW5_PR5,
1096 TEGRA_PIN_KB_ROW6_PR6,
1097 TEGRA_PIN_KB_ROW7_PR7,
1098 TEGRA_PIN_PWR_I2C_SCL_PZ6,
1099 TEGRA_PIN_PWR_I2C_SDA_PZ7,
1100 };
1101
1102 static const unsigned drive_ao2_pins[] = {
1103 TEGRA_PIN_CLK_32K_OUT_PA0,
1104 TEGRA_PIN_KB_COL0_PQ0,
1105 TEGRA_PIN_KB_COL1_PQ1,
1106 TEGRA_PIN_KB_COL2_PQ2,
1107 TEGRA_PIN_KB_COL3_PQ3,
1108 TEGRA_PIN_KB_COL4_PQ4,
1109 TEGRA_PIN_KB_COL5_PQ5,
1110 TEGRA_PIN_KB_COL6_PQ6,
1111 TEGRA_PIN_KB_COL7_PQ7,
1112 TEGRA_PIN_KB_ROW8_PS0,
1113 TEGRA_PIN_KB_ROW9_PS1,
1114 TEGRA_PIN_KB_ROW10_PS2,
1115 TEGRA_PIN_SYS_CLK_REQ_PZ5,
1116 TEGRA_PIN_CORE_PWR_REQ,
1117 TEGRA_PIN_CPU_PWR_REQ,
1118 TEGRA_PIN_RESET_OUT_N,
1119 };
1120
1121 static const unsigned drive_at1_pins[] = {
1122 TEGRA_PIN_GMI_AD8_PH0,
1123 TEGRA_PIN_GMI_AD9_PH1,
1124 TEGRA_PIN_GMI_AD10_PH2,
1125 TEGRA_PIN_GMI_AD11_PH3,
1126 TEGRA_PIN_GMI_AD12_PH4,
1127 TEGRA_PIN_GMI_AD13_PH5,
1128 TEGRA_PIN_GMI_AD14_PH6,
1129 TEGRA_PIN_GMI_AD15_PH7,
1130
1131 TEGRA_PIN_GMI_IORDY_PI5,
1132 TEGRA_PIN_GMI_CS7_N_PI6,
1133 };
1134
1135 static const unsigned drive_at2_pins[] = {
1136 TEGRA_PIN_GMI_AD0_PG0,
1137 TEGRA_PIN_GMI_AD1_PG1,
1138 TEGRA_PIN_GMI_AD2_PG2,
1139 TEGRA_PIN_GMI_AD3_PG3,
1140 TEGRA_PIN_GMI_AD4_PG4,
1141 TEGRA_PIN_GMI_AD5_PG5,
1142 TEGRA_PIN_GMI_AD6_PG6,
1143 TEGRA_PIN_GMI_AD7_PG7,
1144
1145 TEGRA_PIN_GMI_WR_N_PI0,
1146 TEGRA_PIN_GMI_OE_N_PI1,
1147 TEGRA_PIN_GMI_CS6_N_PI3,
1148 TEGRA_PIN_GMI_RST_N_PI4,
1149 TEGRA_PIN_GMI_WAIT_PI7,
1150
1151 TEGRA_PIN_GMI_DQS_P_PJ3,
1152
1153 TEGRA_PIN_GMI_ADV_N_PK0,
1154 TEGRA_PIN_GMI_CLK_PK1,
1155 TEGRA_PIN_GMI_CS4_N_PK2,
1156 TEGRA_PIN_GMI_CS2_N_PK3,
1157 TEGRA_PIN_GMI_CS3_N_PK4,
1158 };
1159
1160 static const unsigned drive_at3_pins[] = {
1161 TEGRA_PIN_GMI_WP_N_PC7,
1162 TEGRA_PIN_GMI_CS0_N_PJ0,
1163 };
1164
1165 static const unsigned drive_at4_pins[] = {
1166 TEGRA_PIN_GMI_A17_PB0,
1167 TEGRA_PIN_GMI_A18_PB1,
1168 TEGRA_PIN_GMI_CS1_N_PJ2,
1169 TEGRA_PIN_GMI_A16_PJ7,
1170 TEGRA_PIN_GMI_A19_PK7,
1171 };
1172
1173 static const unsigned drive_at5_pins[] = {
1174 TEGRA_PIN_GEN2_I2C_SCL_PT5,
1175 TEGRA_PIN_GEN2_I2C_SDA_PT6,
1176 };
1177
1178 static const unsigned drive_cdev1_pins[] = {
1179 TEGRA_PIN_CLK1_OUT_PW4,
1180 TEGRA_PIN_CLK1_REQ_PEE2,
1181 };
1182
1183 static const unsigned drive_cdev2_pins[] = {
1184 TEGRA_PIN_CLK2_OUT_PW5,
1185 TEGRA_PIN_CLK2_REQ_PCC5,
1186 TEGRA_PIN_SDMMC1_WP_N_PV3,
1187 };
1188
1189 static const unsigned drive_dap1_pins[] = {
1190 TEGRA_PIN_DAP1_FS_PN0,
1191 TEGRA_PIN_DAP1_DIN_PN1,
1192 TEGRA_PIN_DAP1_DOUT_PN2,
1193 TEGRA_PIN_DAP1_SCLK_PN3,
1194 };
1195
1196 static const unsigned drive_dap2_pins[] = {
1197 TEGRA_PIN_DAP2_FS_PA2,
1198 TEGRA_PIN_DAP2_SCLK_PA3,
1199 TEGRA_PIN_DAP2_DIN_PA4,
1200 TEGRA_PIN_DAP2_DOUT_PA5,
1201 };
1202
1203 static const unsigned drive_dap3_pins[] = {
1204 TEGRA_PIN_DAP3_FS_PP0,
1205 TEGRA_PIN_DAP3_DIN_PP1,
1206 TEGRA_PIN_DAP3_DOUT_PP2,
1207 TEGRA_PIN_DAP3_SCLK_PP3,
1208 };
1209
1210 static const unsigned drive_dap4_pins[] = {
1211 TEGRA_PIN_DAP4_FS_PP4,
1212 TEGRA_PIN_DAP4_DIN_PP5,
1213 TEGRA_PIN_DAP4_DOUT_PP6,
1214 TEGRA_PIN_DAP4_SCLK_PP7,
1215 };
1216
1217 static const unsigned drive_dbg_pins[] = {
1218 TEGRA_PIN_GEN1_I2C_SCL_PC4,
1219 TEGRA_PIN_GEN1_I2C_SDA_PC5,
1220 TEGRA_PIN_PU0,
1221 TEGRA_PIN_PU1,
1222 TEGRA_PIN_PU2,
1223 TEGRA_PIN_PU3,
1224 TEGRA_PIN_PU4,
1225 TEGRA_PIN_PU5,
1226 TEGRA_PIN_PU6,
1227 };
1228
1229 static const unsigned drive_sdio3_pins[] = {
1230 TEGRA_PIN_SDMMC3_CLK_PA6,
1231 TEGRA_PIN_SDMMC3_CMD_PA7,
1232 TEGRA_PIN_SDMMC3_DAT3_PB4,
1233 TEGRA_PIN_SDMMC3_DAT2_PB5,
1234 TEGRA_PIN_SDMMC3_DAT1_PB6,
1235 TEGRA_PIN_SDMMC3_DAT0_PB7,
1236 TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
1237 TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1238 };
1239
1240 static const unsigned drive_spi_pins[] = {
1241 TEGRA_PIN_DVFS_PWM_PX0,
1242 TEGRA_PIN_GPIO_X1_AUD_PX1,
1243 TEGRA_PIN_DVFS_CLK_PX2,
1244 TEGRA_PIN_GPIO_X3_AUD_PX3,
1245 TEGRA_PIN_GPIO_X4_AUD_PX4,
1246 TEGRA_PIN_GPIO_X5_AUD_PX5,
1247 TEGRA_PIN_GPIO_X6_AUD_PX6,
1248 TEGRA_PIN_GPIO_X7_AUD_PX7,
1249 TEGRA_PIN_GPIO_W2_AUD_PW2,
1250 TEGRA_PIN_GPIO_W3_AUD_PW3,
1251 };
1252
1253 static const unsigned drive_uaa_pins[] = {
1254 TEGRA_PIN_ULPI_DATA0_PO1,
1255 TEGRA_PIN_ULPI_DATA1_PO2,
1256 TEGRA_PIN_ULPI_DATA2_PO3,
1257 TEGRA_PIN_ULPI_DATA3_PO4,
1258 };
1259
1260 static const unsigned drive_uab_pins[] = {
1261 TEGRA_PIN_ULPI_DATA7_PO0,
1262 TEGRA_PIN_ULPI_DATA4_PO5,
1263 TEGRA_PIN_ULPI_DATA5_PO6,
1264 TEGRA_PIN_ULPI_DATA6_PO7,
1265 TEGRA_PIN_PV0,
1266 TEGRA_PIN_PV1,
1267 };
1268
1269 static const unsigned drive_uart2_pins[] = {
1270 TEGRA_PIN_UART2_TXD_PC2,
1271 TEGRA_PIN_UART2_RXD_PC3,
1272 TEGRA_PIN_UART2_CTS_N_PJ5,
1273 TEGRA_PIN_UART2_RTS_N_PJ6,
1274 };
1275
1276 static const unsigned drive_uart3_pins[] = {
1277 TEGRA_PIN_UART3_CTS_N_PA1,
1278 TEGRA_PIN_UART3_RTS_N_PC0,
1279 TEGRA_PIN_UART3_TXD_PW6,
1280 TEGRA_PIN_UART3_RXD_PW7,
1281 };
1282
1283 static const unsigned drive_sdio1_pins[] = {
1284 TEGRA_PIN_SDMMC1_DAT3_PY4,
1285 TEGRA_PIN_SDMMC1_DAT2_PY5,
1286 TEGRA_PIN_SDMMC1_DAT1_PY6,
1287 TEGRA_PIN_SDMMC1_DAT0_PY7,
1288 TEGRA_PIN_SDMMC1_CLK_PZ0,
1289 TEGRA_PIN_SDMMC1_CMD_PZ1,
1290 };
1291
1292 static const unsigned drive_ddc_pins[] = {
1293 TEGRA_PIN_DDC_SCL_PV4,
1294 TEGRA_PIN_DDC_SDA_PV5,
1295 };
1296
1297 static const unsigned drive_gma_pins[] = {
1298 TEGRA_PIN_SDMMC4_CLK_PCC4,
1299 TEGRA_PIN_SDMMC4_CMD_PT7,
1300 TEGRA_PIN_SDMMC4_DAT0_PAA0,
1301 TEGRA_PIN_SDMMC4_DAT1_PAA1,
1302 TEGRA_PIN_SDMMC4_DAT2_PAA2,
1303 TEGRA_PIN_SDMMC4_DAT3_PAA3,
1304 TEGRA_PIN_SDMMC4_DAT4_PAA4,
1305 TEGRA_PIN_SDMMC4_DAT5_PAA5,
1306 TEGRA_PIN_SDMMC4_DAT6_PAA6,
1307 TEGRA_PIN_SDMMC4_DAT7_PAA7,
1308 };
1309
1310 static const unsigned drive_gme_pins[] = {
1311 TEGRA_PIN_PBB0,
1312 TEGRA_PIN_CAM_I2C_SCL_PBB1,
1313 TEGRA_PIN_CAM_I2C_SDA_PBB2,
1314 TEGRA_PIN_PBB3,
1315 TEGRA_PIN_PCC2,
1316 };
1317
1318 static const unsigned drive_gmf_pins[] = {
1319 TEGRA_PIN_PBB4,
1320 TEGRA_PIN_PBB5,
1321 TEGRA_PIN_PBB6,
1322 TEGRA_PIN_PBB7,
1323 };
1324
1325 static const unsigned drive_gmg_pins[] = {
1326 TEGRA_PIN_CAM_MCLK_PCC0,
1327 };
1328
1329 static const unsigned drive_gmh_pins[] = {
1330 TEGRA_PIN_PCC1,
1331 };
1332
1333 static const unsigned drive_owr_pins[] = {
1334 TEGRA_PIN_SDMMC3_CD_N_PV2,
1335 };
1336
1337 static const unsigned drive_uda_pins[] = {
1338 TEGRA_PIN_ULPI_CLK_PY0,
1339 TEGRA_PIN_ULPI_DIR_PY1,
1340 TEGRA_PIN_ULPI_NXT_PY2,
1341 TEGRA_PIN_ULPI_STP_PY3,
1342 };
1343
1344 static const unsigned drive_dev3_pins[] = {
1345 TEGRA_PIN_CLK3_OUT_PEE0,
1346 TEGRA_PIN_CLK3_REQ_PEE1,
1347 };
1348
1349 enum tegra_mux {
1350 TEGRA_MUX_BLINK,
1351 TEGRA_MUX_CEC,
1352 TEGRA_MUX_CLDVFS,
1353 TEGRA_MUX_CLK12,
1354 TEGRA_MUX_CPU,
1355 TEGRA_MUX_DAP,
1356 TEGRA_MUX_DAP1,
1357 TEGRA_MUX_DAP2,
1358 TEGRA_MUX_DEV3,
1359 TEGRA_MUX_DISPLAYA,
1360 TEGRA_MUX_DISPLAYA_ALT,
1361 TEGRA_MUX_DISPLAYB,
1362 TEGRA_MUX_DTV,
1363 TEGRA_MUX_EMC_DLL,
1364 TEGRA_MUX_EXTPERIPH1,
1365 TEGRA_MUX_EXTPERIPH2,
1366 TEGRA_MUX_EXTPERIPH3,
1367 TEGRA_MUX_GMI,
1368 TEGRA_MUX_GMI_ALT,
1369 TEGRA_MUX_HDA,
1370 TEGRA_MUX_HSI,
1371 TEGRA_MUX_I2C1,
1372 TEGRA_MUX_I2C2,
1373 TEGRA_MUX_I2C3,
1374 TEGRA_MUX_I2C4,
1375 TEGRA_MUX_I2CPWR,
1376 TEGRA_MUX_I2S0,
1377 TEGRA_MUX_I2S1,
1378 TEGRA_MUX_I2S2,
1379 TEGRA_MUX_I2S3,
1380 TEGRA_MUX_I2S4,
1381 TEGRA_MUX_IRDA,
1382 TEGRA_MUX_KBC,
1383 TEGRA_MUX_NAND,
1384 TEGRA_MUX_NAND_ALT,
1385 TEGRA_MUX_OWR,
1386 TEGRA_MUX_PMI,
1387 TEGRA_MUX_PWM0,
1388 TEGRA_MUX_PWM1,
1389 TEGRA_MUX_PWM2,
1390 TEGRA_MUX_PWM3,
1391 TEGRA_MUX_PWRON,
1392 TEGRA_MUX_RESET_OUT_N,
1393 TEGRA_MUX_RSVD1,
1394 TEGRA_MUX_RSVD2,
1395 TEGRA_MUX_RSVD3,
1396 TEGRA_MUX_RSVD4,
1397 TEGRA_MUX_SDMMC1,
1398 TEGRA_MUX_SDMMC2,
1399 TEGRA_MUX_SDMMC3,
1400 TEGRA_MUX_SDMMC4,
1401 TEGRA_MUX_SOC,
1402 TEGRA_MUX_SPDIF,
1403 TEGRA_MUX_SPI1,
1404 TEGRA_MUX_SPI2,
1405 TEGRA_MUX_SPI3,
1406 TEGRA_MUX_SPI4,
1407 TEGRA_MUX_SPI5,
1408 TEGRA_MUX_SPI6,
1409 TEGRA_MUX_SYSCLK,
1410 TEGRA_MUX_TRACE,
1411 TEGRA_MUX_UARTA,
1412 TEGRA_MUX_UARTB,
1413 TEGRA_MUX_UARTC,
1414 TEGRA_MUX_UARTD,
1415 TEGRA_MUX_ULPI,
1416 TEGRA_MUX_USB,
1417 TEGRA_MUX_VGP1,
1418 TEGRA_MUX_VGP2,
1419 TEGRA_MUX_VGP3,
1420 TEGRA_MUX_VGP4,
1421 TEGRA_MUX_VGP5,
1422 TEGRA_MUX_VGP6,
1423 TEGRA_MUX_VI,
1424 TEGRA_MUX_VI_ALT1,
1425 TEGRA_MUX_VI_ALT3,
1426 };
1427
1428 static const char * const blink_groups[] = {
1429 "clk_32k_out_pa0",
1430 };
1431
1432 static const char * const cec_groups[] = {
1433 "hdmi_cec_pee3",
1434 };
1435
1436 static const char * const cldvfs_groups[] = {
1437 "gmi_ad9_ph1",
1438 "gmi_ad10_ph2",
1439 "kb_row7_pr7",
1440 "kb_row8_ps0",
1441 "dvfs_pwm_px0",
1442 "dvfs_clk_px2",
1443 };
1444
1445 static const char * const clk12_groups[] = {
1446 "sdmmc1_wp_n_pv3",
1447 "sdmmc1_clk_pz0",
1448 };
1449
1450 static const char * const cpu_groups[] = {
1451 "cpu_pwr_req",
1452 };
1453
1454 static const char * const dap_groups[] = {
1455 "clk1_req_pee2",
1456 "clk2_req_pcc5",
1457 };
1458
1459 static const char * const dap1_groups[] = {
1460 "clk1_req_pee2",
1461 };
1462
1463 static const char * const dap2_groups[] = {
1464 "clk1_out_pw4",
1465 "gpio_x4_aud_px4",
1466 };
1467
1468 static const char * const dev3_groups[] = {
1469 "clk3_req_pee1",
1470 };
1471
1472 static const char * const displaya_groups[] = {
1473 "dap3_fs_pp0",
1474 "dap3_din_pp1",
1475 "dap3_dout_pp2",
1476 "dap3_sclk_pp3",
1477 "uart3_rts_n_pc0",
1478 "pu3",
1479 "pu4",
1480 "pu5",
1481 "pbb3",
1482 "pbb4",
1483 "pbb5",
1484 "pbb6",
1485 "kb_row3_pr3",
1486 "kb_row4_pr4",
1487 "kb_row5_pr5",
1488 "kb_row6_pr6",
1489 "kb_col3_pq3",
1490 "sdmmc3_dat2_pb5",
1491 };
1492
1493 static const char * const displaya_alt_groups[] = {
1494 "kb_row6_pr6",
1495 };
1496
1497 static const char * const displayb_groups[] = {
1498 "dap3_fs_pp0",
1499 "dap3_din_pp1",
1500 "dap3_dout_pp2",
1501 "dap3_sclk_pp3",
1502 "pu3",
1503 "pu4",
1504 "pu5",
1505 "pu6",
1506 "pbb3",
1507 "pbb4",
1508 "pbb5",
1509 "pbb6",
1510 "kb_row3_pr3",
1511 "kb_row4_pr4",
1512 "kb_row5_pr5",
1513 "kb_row6_pr6",
1514 "sdmmc3_dat3_pb4",
1515 };
1516
1517 static const char * const dtv_groups[] = {
1518 "uart3_cts_n_pa1",
1519 "uart3_rts_n_pc0",
1520 "dap4_fs_pp4",
1521 "dap4_dout_pp6",
1522 "gmi_wait_pi7",
1523 "gmi_ad8_ph0",
1524 "gmi_ad14_ph6",
1525 "gmi_ad15_ph7",
1526 };
1527
1528 static const char * const emc_dll_groups[] = {
1529 "kb_col0_pq0",
1530 "kb_col1_pq1",
1531 };
1532
1533 static const char * const extperiph1_groups[] = {
1534 "clk1_out_pw4",
1535 };
1536
1537 static const char * const extperiph2_groups[] = {
1538 "clk2_out_pw5",
1539 };
1540
1541 static const char * const extperiph3_groups[] = {
1542 "clk3_out_pee0",
1543 };
1544
1545 static const char * const gmi_groups[] = {
1546 "gmi_wp_n_pc7",
1547
1548 "gmi_ad0_pg0",
1549 "gmi_ad1_pg1",
1550 "gmi_ad2_pg2",
1551 "gmi_ad3_pg3",
1552 "gmi_ad4_pg4",
1553 "gmi_ad5_pg5",
1554 "gmi_ad6_pg6",
1555 "gmi_ad7_pg7",
1556 "gmi_ad8_ph0",
1557 "gmi_ad9_ph1",
1558 "gmi_ad10_ph2",
1559 "gmi_ad11_ph3",
1560 "gmi_ad12_ph4",
1561 "gmi_ad13_ph5",
1562 "gmi_ad14_ph6",
1563 "gmi_ad15_ph7",
1564 "gmi_wr_n_pi0",
1565 "gmi_oe_n_pi1",
1566 "gmi_cs6_n_pi3",
1567 "gmi_rst_n_pi4",
1568 "gmi_iordy_pi5",
1569 "gmi_cs7_n_pi6",
1570 "gmi_wait_pi7",
1571 "gmi_cs0_n_pj0",
1572 "gmi_cs1_n_pj2",
1573 "gmi_dqs_p_pj3",
1574 "gmi_adv_n_pk0",
1575 "gmi_clk_pk1",
1576 "gmi_cs4_n_pk2",
1577 "gmi_cs2_n_pk3",
1578 "gmi_cs3_n_pk4",
1579 "gmi_a16_pj7",
1580 "gmi_a17_pb0",
1581 "gmi_a18_pb1",
1582 "gmi_a19_pk7",
1583 "gen2_i2c_scl_pt5",
1584 "gen2_i2c_sda_pt6",
1585 "sdmmc4_dat0_paa0",
1586 "sdmmc4_dat1_paa1",
1587 "sdmmc4_dat2_paa2",
1588 "sdmmc4_dat3_paa3",
1589 "sdmmc4_dat4_paa4",
1590 "sdmmc4_dat5_paa5",
1591 "sdmmc4_dat6_paa6",
1592 "sdmmc4_dat7_paa7",
1593 "sdmmc4_clk_pcc4",
1594 "sdmmc4_cmd_pt7",
1595 "dap1_fs_pn0",
1596 "dap1_din_pn1",
1597 "dap1_dout_pn2",
1598 "dap1_sclk_pn3",
1599 };
1600
1601 static const char * const gmi_alt_groups[] = {
1602 "gmi_wp_n_pc7",
1603 "gmi_cs3_n_pk4",
1604 "gmi_a16_pj7",
1605 };
1606
1607 static const char * const hda_groups[] = {
1608 "dap1_fs_pn0",
1609 "dap1_din_pn1",
1610 "dap1_dout_pn2",
1611 "dap1_sclk_pn3",
1612 "dap2_fs_pa2",
1613 "dap2_sclk_pa3",
1614 "dap2_din_pa4",
1615 "dap2_dout_pa5",
1616 };
1617
1618 static const char * const hsi_groups[] = {
1619 "ulpi_data0_po1",
1620 "ulpi_data1_po2",
1621 "ulpi_data2_po3",
1622 "ulpi_data3_po4",
1623 "ulpi_data4_po5",
1624 "ulpi_data5_po6",
1625 "ulpi_data6_po7",
1626 "ulpi_data7_po0",
1627 };
1628
1629 static const char * const i2c1_groups[] = {
1630 "gen1_i2c_scl_pc4",
1631 "gen1_i2c_sda_pc5",
1632 "gpio_w2_aud_pw2",
1633 "gpio_w3_aud_pw3",
1634 };
1635
1636 static const char * const i2c2_groups[] = {
1637 "gen2_i2c_scl_pt5",
1638 "gen2_i2c_sda_pt6",
1639 };
1640
1641 static const char * const i2c3_groups[] = {
1642 "cam_i2c_scl_pbb1",
1643 "cam_i2c_sda_pbb2",
1644 };
1645
1646 static const char * const i2c4_groups[] = {
1647 "ddc_scl_pv4",
1648 "ddc_sda_pv5",
1649 };
1650
1651 static const char * const i2cpwr_groups[] = {
1652 "pwr_i2c_scl_pz6",
1653 "pwr_i2c_sda_pz7",
1654 };
1655
1656 static const char * const i2s0_groups[] = {
1657 "dap1_fs_pn0",
1658 "dap1_din_pn1",
1659 "dap1_dout_pn2",
1660 "dap1_sclk_pn3",
1661 };
1662
1663 static const char * const i2s1_groups[] = {
1664 "dap2_fs_pa2",
1665 "dap2_sclk_pa3",
1666 "dap2_din_pa4",
1667 "dap2_dout_pa5",
1668 };
1669
1670 static const char * const i2s2_groups[] = {
1671 "dap3_fs_pp0",
1672 "dap3_din_pp1",
1673 "dap3_dout_pp2",
1674 "dap3_sclk_pp3",
1675 };
1676
1677 static const char * const i2s3_groups[] = {
1678 "dap4_fs_pp4",
1679 "dap4_din_pp5",
1680 "dap4_dout_pp6",
1681 "dap4_sclk_pp7",
1682 };
1683
1684 static const char * const i2s4_groups[] = {
1685 "pcc1",
1686 "pbb0",
1687 "pbb7",
1688 "pcc2",
1689 };
1690
1691 static const char * const irda_groups[] = {
1692 "uart2_rxd_pc3",
1693 "uart2_txd_pc2",
1694 };
1695
1696 static const char * const kbc_groups[] = {
1697 "kb_row0_pr0",
1698 "kb_row1_pr1",
1699 "kb_row2_pr2",
1700 "kb_row3_pr3",
1701 "kb_row4_pr4",
1702 "kb_row5_pr5",
1703 "kb_row6_pr6",
1704 "kb_row7_pr7",
1705 "kb_row8_ps0",
1706 "kb_row9_ps1",
1707 "kb_row10_ps2",
1708 "kb_col0_pq0",
1709 "kb_col1_pq1",
1710 "kb_col2_pq2",
1711 "kb_col3_pq3",
1712 "kb_col4_pq4",
1713 "kb_col5_pq5",
1714 "kb_col6_pq6",
1715 "kb_col7_pq7",
1716 };
1717
1718 static const char * const nand_groups[] = {
1719 "gmi_wp_n_pc7",
1720 "gmi_wait_pi7",
1721 "gmi_adv_n_pk0",
1722 "gmi_clk_pk1",
1723 "gmi_cs0_n_pj0",
1724 "gmi_cs1_n_pj2",
1725 "gmi_cs2_n_pk3",
1726 "gmi_cs3_n_pk4",
1727 "gmi_cs4_n_pk2",
1728 "gmi_cs6_n_pi3",
1729 "gmi_cs7_n_pi6",
1730 "gmi_ad0_pg0",
1731 "gmi_ad1_pg1",
1732 "gmi_ad2_pg2",
1733 "gmi_ad3_pg3",
1734 "gmi_ad4_pg4",
1735 "gmi_ad5_pg5",
1736 "gmi_ad6_pg6",
1737 "gmi_ad7_pg7",
1738 "gmi_ad8_ph0",
1739 "gmi_ad9_ph1",
1740 "gmi_ad10_ph2",
1741 "gmi_ad11_ph3",
1742 "gmi_ad12_ph4",
1743 "gmi_ad13_ph5",
1744 "gmi_ad14_ph6",
1745 "gmi_ad15_ph7",
1746 "gmi_wr_n_pi0",
1747 "gmi_oe_n_pi1",
1748 "gmi_dqs_p_pj3",
1749 "gmi_rst_n_pi4",
1750 };
1751
1752 static const char * const nand_alt_groups[] = {
1753 "gmi_cs6_n_pi3",
1754 "gmi_cs7_n_pi6",
1755 "gmi_rst_n_pi4",
1756 };
1757
1758 static const char * const owr_groups[] = {
1759 "pu0",
1760 "kb_col4_pq4",
1761 "owr",
1762 "sdmmc3_cd_n_pv2",
1763 };
1764
1765 static const char * const pmi_groups[] = {
1766 "pwr_int_n",
1767 };
1768
1769 static const char * const pwm0_groups[] = {
1770 "sdmmc1_dat2_py5",
1771 "uart3_rts_n_pc0",
1772 "pu3",
1773 "gmi_ad8_ph0",
1774 "sdmmc3_dat3_pb4",
1775 };
1776
1777 static const char * const pwm1_groups[] = {
1778 "sdmmc1_dat1_py6",
1779 "pu4",
1780 "gmi_ad9_ph1",
1781 "sdmmc3_dat2_pb5",
1782 };
1783
1784 static const char * const pwm2_groups[] = {
1785 "pu5",
1786 "gmi_ad10_ph2",
1787 "kb_col3_pq3",
1788 "sdmmc3_dat1_pb6",
1789 };
1790
1791 static const char * const pwm3_groups[] = {
1792 "pu6",
1793 "gmi_ad11_ph3",
1794 "sdmmc3_cmd_pa7",
1795 };
1796
1797 static const char * const pwron_groups[] = {
1798 "core_pwr_req",
1799 };
1800
1801 static const char * const reset_out_n_groups[] = {
1802 "reset_out_n",
1803 };
1804
1805 static const char * const rsvd1_groups[] = {
1806 "pv1",
1807 "hdmi_int_pn7",
1808 "pu1",
1809 "pu2",
1810 "gmi_wp_n_pc7",
1811 "gmi_adv_n_pk0",
1812 "gmi_cs0_n_pj0",
1813 "gmi_cs1_n_pj2",
1814 "gmi_ad0_pg0",
1815 "gmi_ad1_pg1",
1816 "gmi_ad2_pg2",
1817 "gmi_ad3_pg3",
1818 "gmi_ad4_pg4",
1819 "gmi_ad5_pg5",
1820 "gmi_ad6_pg6",
1821 "gmi_ad7_pg7",
1822 "gmi_wr_n_pi0",
1823 "gmi_oe_n_pi1",
1824 "gpio_x4_aud_px4",
1825 "gpio_x5_aud_px5",
1826 "gpio_x7_aud_px7",
1827
1828 "reset_out_n",
1829 };
1830
1831 static const char * const rsvd2_groups[] = {
1832 "pv0",
1833 "pv1",
1834 "sdmmc1_dat0_py7",
1835 "clk2_out_pw5",
1836 "clk2_req_pcc5",
1837 "hdmi_int_pn7",
1838 "ddc_scl_pv4",
1839 "ddc_sda_pv5",
1840 "uart3_txd_pw6",
1841 "uart3_rxd_pw7",
1842 "gen1_i2c_scl_pc4",
1843 "gen1_i2c_sda_pc5",
1844 "dap4_fs_pp4",
1845 "dap4_din_pp5",
1846 "dap4_dout_pp6",
1847 "dap4_sclk_pp7",
1848 "clk3_out_pee0",
1849 "clk3_req_pee1",
1850 "gmi_iordy_pi5",
1851 "gmi_a17_pb0",
1852 "gmi_a18_pb1",
1853 "gen2_i2c_scl_pt5",
1854 "gen2_i2c_sda_pt6",
1855 "sdmmc4_clk_pcc4",
1856 "sdmmc4_cmd_pt7",
1857 "sdmmc4_dat7_paa7",
1858 "pcc1",
1859 "pbb7",
1860 "pcc2",
1861 "pwr_i2c_scl_pz6",
1862 "pwr_i2c_sda_pz7",
1863 "kb_row0_pr0",
1864 "kb_row1_pr1",
1865 "kb_row2_pr2",
1866 "kb_row7_pr7",
1867 "kb_row8_ps0",
1868 "kb_row9_ps1",
1869 "kb_row10_ps2",
1870 "kb_col1_pq1",
1871 "kb_col2_pq2",
1872 "kb_col5_pq5",
1873 "kb_col6_pq6",
1874 "kb_col7_pq7",
1875 "sys_clk_req_pz5",
1876 "core_pwr_req",
1877 "cpu_pwr_req",
1878 "pwr_int_n",
1879 "owr",
1880 "spdif_out_pk5",
1881 "gpio_x1_aud_px1",
1882 "sdmmc3_clk_pa6",
1883 "sdmmc3_dat0_pb7",
1884 "gpio_w2_aud_pw2",
1885 "usb_vbus_en0_pn4",
1886 "usb_vbus_en1_pn5",
1887 "sdmmc3_clk_lb_out_pee4",
1888 "sdmmc3_clk_lb_in_pee5",
1889 "reset_out_n",
1890 };
1891
1892 static const char * const rsvd3_groups[] = {
1893 "pv0",
1894 "pv1",
1895 "sdmmc1_clk_pz0",
1896 "clk2_out_pw5",
1897 "clk2_req_pcc5",
1898 "hdmi_int_pn7",
1899 "ddc_scl_pv4",
1900 "ddc_sda_pv5",
1901 "uart2_rts_n_pj6",
1902 "uart2_cts_n_pj5",
1903 "uart3_txd_pw6",
1904 "uart3_rxd_pw7",
1905 "pu0",
1906 "pu1",
1907 "pu2",
1908 "gen1_i2c_scl_pc4",
1909 "gen1_i2c_sda_pc5",
1910 "dap4_din_pp5",
1911 "dap4_sclk_pp7",
1912 "clk3_out_pee0",
1913 "clk3_req_pee1",
1914 "pcc1",
1915 "cam_i2c_scl_pbb1",
1916 "cam_i2c_sda_pbb2",
1917 "pbb7",
1918 "pcc2",
1919 "pwr_i2c_scl_pz6",
1920 "pwr_i2c_sda_pz7",
1921 "kb_row0_pr0",
1922 "kb_row1_pr1",
1923 "kb_row2_pr2",
1924 "kb_row3_pr3",
1925 "kb_row9_ps1",
1926 "kb_row10_ps2",
1927 "clk_32k_out_pa0",
1928 "sys_clk_req_pz5",
1929 "core_pwr_req",
1930 "cpu_pwr_req",
1931 "pwr_int_n",
1932 "owr",
1933 "clk1_req_pee2",
1934 "clk1_out_pw4",
1935 "spdif_out_pk5",
1936 "spdif_in_pk6",
1937 "dap2_fs_pa2",
1938 "dap2_sclk_pa3",
1939 "dap2_din_pa4",
1940 "dap2_dout_pa5",
1941 "dvfs_pwm_px0",
1942 "gpio_x1_aud_px1",
1943 "gpio_x3_aud_px3",
1944 "dvfs_clk_px2",
1945 "sdmmc3_clk_pa6",
1946 "sdmmc3_dat0_pb7",
1947 "hdmi_cec_pee3",
1948 "sdmmc3_cd_n_pv2",
1949 "usb_vbus_en0_pn4",
1950 "usb_vbus_en1_pn5",
1951 "sdmmc3_clk_lb_out_pee4",
1952 "sdmmc3_clk_lb_in_pee5",
1953 "reset_out_n",
1954 };
1955
1956 static const char * const rsvd4_groups[] = {
1957 "pv0",
1958 "pv1",
1959 "sdmmc1_clk_pz0",
1960 "clk2_out_pw5",
1961 "clk2_req_pcc5",
1962 "hdmi_int_pn7",
1963 "ddc_scl_pv4",
1964 "ddc_sda_pv5",
1965 "pu0",
1966 "pu1",
1967 "pu2",
1968 "gen1_i2c_scl_pc4",
1969 "gen1_i2c_sda_pc5",
1970 "dap4_fs_pp4",
1971 "dap4_din_pp5",
1972 "dap4_dout_pp6",
1973 "dap4_sclk_pp7",
1974 "clk3_out_pee0",
1975 "clk3_req_pee1",
1976 "gmi_ad0_pg0",
1977 "gmi_ad1_pg1",
1978 "gmi_ad2_pg2",
1979 "gmi_ad3_pg3",
1980 "gmi_ad4_pg4",
1981 "gmi_ad12_ph4",
1982 "gmi_ad13_ph5",
1983 "gmi_rst_n_pi4",
1984 "gen2_i2c_scl_pt5",
1985 "gen2_i2c_sda_pt6",
1986 "sdmmc4_clk_pcc4",
1987 "sdmmc4_cmd_pt7",
1988 "sdmmc4_dat0_paa0",
1989 "sdmmc4_dat1_paa1",
1990 "sdmmc4_dat2_paa2",
1991 "sdmmc4_dat3_paa3",
1992 "sdmmc4_dat4_paa4",
1993 "sdmmc4_dat5_paa5",
1994 "sdmmc4_dat6_paa6",
1995 "sdmmc4_dat7_paa7",
1996 "cam_mclk_pcc0",
1997 "pcc1",
1998 "cam_i2c_scl_pbb1",
1999 "cam_i2c_sda_pbb2",
2000 "pbb3",
2001 "pbb4",
2002 "pbb5",
2003 "pbb6",
2004 "pbb7",
2005 "pcc2",
2006 "pwr_i2c_scl_pz6",
2007 "pwr_i2c_sda_pz7",
2008 "kb_row0_pr0",
2009 "kb_row1_pr1",
2010 "kb_row2_pr2",
2011 "kb_col2_pq2",
2012 "kb_col5_pq5",
2013 "kb_col6_pq6",
2014 "kb_col7_pq7",
2015 "clk_32k_out_pa0",
2016 "sys_clk_req_pz5",
2017 "core_pwr_req",
2018 "cpu_pwr_req",
2019 "pwr_int_n",
2020 "owr",
2021 "dap1_fs_pn0",
2022 "dap1_din_pn1",
2023 "dap1_dout_pn2",
2024 "dap1_sclk_pn3",
2025 "clk1_req_pee2",
2026 "clk1_out_pw4",
2027 "spdif_in_pk6",
2028 "spdif_out_pk5",
2029 "dap2_fs_pa2",
2030 "dap2_sclk_pa3",
2031 "dap2_din_pa4",
2032 "dap2_dout_pa5",
2033 "dvfs_pwm_px0",
2034 "gpio_x1_aud_px1",
2035 "gpio_x3_aud_px3",
2036 "dvfs_clk_px2",
2037 "gpio_x5_aud_px5",
2038 "gpio_x6_aud_px6",
2039 "gpio_x7_aud_px7",
2040 "sdmmc3_cd_n_pv2",
2041 "usb_vbus_en0_pn4",
2042 "usb_vbus_en1_pn5",
2043 "sdmmc3_clk_lb_in_pee5",
2044 "sdmmc3_clk_lb_out_pee4",
2045 };
2046
2047 static const char * const sdmmc1_groups[] = {
2048
2049 "sdmmc1_clk_pz0",
2050 "sdmmc1_cmd_pz1",
2051 "sdmmc1_dat3_py4",
2052 "sdmmc1_dat2_py5",
2053 "sdmmc1_dat1_py6",
2054 "sdmmc1_dat0_py7",
2055 "uart3_cts_n_pa1",
2056 "kb_col5_pq5",
2057 "sdmmc1_wp_n_pv3",
2058 };
2059
2060 static const char * const sdmmc2_groups[] = {
2061 "gmi_iordy_pi5",
2062 "gmi_clk_pk1",
2063 "gmi_cs2_n_pk3",
2064 "gmi_cs3_n_pk4",
2065 "gmi_cs7_n_pi6",
2066 "gmi_ad12_ph4",
2067 "gmi_ad13_ph5",
2068 "gmi_ad14_ph6",
2069 "gmi_ad15_ph7",
2070 "gmi_dqs_p_pj3",
2071 };
2072
2073 static const char * const sdmmc3_groups[] = {
2074 "kb_col4_pq4",
2075 "sdmmc3_clk_pa6",
2076 "sdmmc3_cmd_pa7",
2077 "sdmmc3_dat0_pb7",
2078 "sdmmc3_dat1_pb6",
2079 "sdmmc3_dat2_pb5",
2080 "sdmmc3_dat3_pb4",
2081 "hdmi_cec_pee3",
2082 "sdmmc3_cd_n_pv2",
2083 "sdmmc3_clk_lb_in_pee5",
2084 "sdmmc3_clk_lb_out_pee4",
2085 };
2086
2087 static const char * const sdmmc4_groups[] = {
2088 "sdmmc4_clk_pcc4",
2089 "sdmmc4_cmd_pt7",
2090 "sdmmc4_dat0_paa0",
2091 "sdmmc4_dat1_paa1",
2092 "sdmmc4_dat2_paa2",
2093 "sdmmc4_dat3_paa3",
2094 "sdmmc4_dat4_paa4",
2095 "sdmmc4_dat5_paa5",
2096 "sdmmc4_dat6_paa6",
2097 "sdmmc4_dat7_paa7",
2098 };
2099
2100 static const char * const soc_groups[] = {
2101 "gmi_cs1_n_pj2",
2102 "gmi_oe_n_pi1",
2103 "clk_32k_out_pa0",
2104 "hdmi_cec_pee3",
2105 };
2106
2107 static const char * const spdif_groups[] = {
2108 "sdmmc1_cmd_pz1",
2109 "sdmmc1_dat3_py4",
2110 "uart2_rxd_pc3",
2111 "uart2_txd_pc2",
2112 "spdif_in_pk6",
2113 "spdif_out_pk5",
2114 };
2115
2116 static const char * const spi1_groups[] = {
2117 "ulpi_clk_py0",
2118 "ulpi_dir_py1",
2119 "ulpi_nxt_py2",
2120 "ulpi_stp_py3",
2121 "gpio_x3_aud_px3",
2122 "gpio_x4_aud_px4",
2123 "gpio_x5_aud_px5",
2124 "gpio_x6_aud_px6",
2125 "gpio_x7_aud_px7",
2126 "gpio_w3_aud_pw3",
2127 };
2128
2129 static const char * const spi2_groups[] = {
2130 "ulpi_data4_po5",
2131 "ulpi_data5_po6",
2132 "ulpi_data6_po7",
2133 "ulpi_data7_po0",
2134 "kb_row4_pr4",
2135 "kb_row5_pr5",
2136 "kb_col0_pq0",
2137 "kb_col1_pq1",
2138 "kb_col2_pq2",
2139 "kb_col6_pq6",
2140 "kb_col7_pq7",
2141 "gpio_x4_aud_px4",
2142 "gpio_x5_aud_px5",
2143 "gpio_x6_aud_px6",
2144 "gpio_x7_aud_px7",
2145 "gpio_w2_aud_pw2",
2146 "gpio_w3_aud_pw3",
2147 };
2148
2149 static const char * const spi3_groups[] = {
2150 "ulpi_data0_po1",
2151 "ulpi_data1_po2",
2152 "ulpi_data2_po3",
2153 "ulpi_data3_po4",
2154 "sdmmc4_dat0_paa0",
2155 "sdmmc4_dat1_paa1",
2156 "sdmmc4_dat2_paa2",
2157 "sdmmc4_dat3_paa3",
2158 "sdmmc4_dat4_paa4",
2159 "sdmmc4_dat5_paa5",
2160 "sdmmc4_dat6_paa6",
2161 "sdmmc3_clk_pa6",
2162 "sdmmc3_cmd_pa7",
2163 "sdmmc3_dat0_pb7",
2164 "sdmmc3_dat1_pb6",
2165 "sdmmc3_dat2_pb5",
2166 "sdmmc3_dat3_pb4",
2167 };
2168
2169 static const char * const spi4_groups[] = {
2170 "sdmmc1_cmd_pz1",
2171 "sdmmc1_dat3_py4",
2172 "sdmmc1_dat2_py5",
2173 "sdmmc1_dat1_py6",
2174 "sdmmc1_dat0_py7",
2175 "uart2_rxd_pc3",
2176 "uart2_txd_pc2",
2177 "uart2_rts_n_pj6",
2178 "uart2_cts_n_pj5",
2179 "uart3_txd_pw6",
2180 "uart3_rxd_pw7",
2181 "uart3_cts_n_pa1",
2182 "gmi_wait_pi7",
2183 "gmi_cs6_n_pi3",
2184 "gmi_ad5_pg5",
2185 "gmi_ad6_pg6",
2186 "gmi_ad7_pg7",
2187 "gmi_a19_pk7",
2188 "gmi_wr_n_pi0",
2189 "sdmmc1_wp_n_pv3",
2190 };
2191
2192 static const char * const spi5_groups[] = {
2193 "ulpi_clk_py0",
2194 "ulpi_dir_py1",
2195 "ulpi_nxt_py2",
2196 "ulpi_stp_py3",
2197 "dap3_fs_pp0",
2198 "dap3_din_pp1",
2199 "dap3_dout_pp2",
2200 "dap3_sclk_pp3",
2201 };
2202
2203 static const char * const spi6_groups[] = {
2204 "dvfs_pwm_px0",
2205 "gpio_x1_aud_px1",
2206 "gpio_x3_aud_px3",
2207 "dvfs_clk_px2",
2208 "gpio_x6_aud_px6",
2209 "gpio_w2_aud_pw2",
2210 "gpio_w3_aud_pw3",
2211 };
2212
2213 static const char * const sysclk_groups[] = {
2214 "sys_clk_req_pz5",
2215 };
2216
2217 static const char * const trace_groups[] = {
2218 "gmi_iordy_pi5",
2219 "gmi_adv_n_pk0",
2220 "gmi_clk_pk1",
2221 "gmi_cs2_n_pk3",
2222 "gmi_cs4_n_pk2",
2223 "gmi_a16_pj7",
2224 "gmi_a17_pb0",
2225 "gmi_a18_pb1",
2226 "gmi_a19_pk7",
2227 "gmi_dqs_p_pj3",
2228 };
2229
2230 static const char * const uarta_groups[] = {
2231 "ulpi_data0_po1",
2232 "ulpi_data1_po2",
2233 "ulpi_data2_po3",
2234 "ulpi_data3_po4",
2235 "ulpi_data4_po5",
2236 "ulpi_data5_po6",
2237 "ulpi_data6_po7",
2238 "ulpi_data7_po0",
2239 "sdmmc1_cmd_pz1",
2240 "sdmmc1_dat3_py4",
2241 "sdmmc1_dat2_py5",
2242 "sdmmc1_dat1_py6",
2243 "sdmmc1_dat0_py7",
2244 "uart2_rxd_pc3",
2245 "uart2_txd_pc2",
2246 "uart2_rts_n_pj6",
2247 "uart2_cts_n_pj5",
2248 "pu0",
2249 "pu1",
2250 "pu2",
2251 "pu3",
2252 "pu4",
2253 "pu5",
2254 "pu6",
2255 "kb_row7_pr7",
2256 "kb_row8_ps0",
2257 "kb_row9_ps1",
2258 "kb_row10_ps2",
2259 "kb_col3_pq3",
2260 "kb_col4_pq4",
2261 "sdmmc3_cmd_pa7",
2262 "sdmmc3_dat1_pb6",
2263 "sdmmc1_wp_n_pv3",
2264 };
2265
2266 static const char * const uartb_groups[] = {
2267 "uart2_rts_n_pj6",
2268 "uart2_cts_n_pj5",
2269 };
2270
2271 static const char * const uartc_groups[] = {
2272 "uart3_txd_pw6",
2273 "uart3_rxd_pw7",
2274 "uart3_cts_n_pa1",
2275 "uart3_rts_n_pc0",
2276 };
2277
2278 static const char * const uartd_groups[] = {
2279 "ulpi_clk_py0",
2280 "ulpi_dir_py1",
2281 "ulpi_nxt_py2",
2282 "ulpi_stp_py3",
2283 "gmi_a16_pj7",
2284 "gmi_a17_pb0",
2285 "gmi_a18_pb1",
2286 "gmi_a19_pk7",
2287 };
2288
2289 static const char * const ulpi_groups[] = {
2290 "ulpi_data0_po1",
2291 "ulpi_data1_po2",
2292 "ulpi_data2_po3",
2293 "ulpi_data3_po4",
2294 "ulpi_data4_po5",
2295 "ulpi_data5_po6",
2296 "ulpi_data6_po7",
2297 "ulpi_data7_po0",
2298 "ulpi_clk_py0",
2299 "ulpi_dir_py1",
2300 "ulpi_nxt_py2",
2301 "ulpi_stp_py3",
2302 };
2303
2304 static const char * const usb_groups[] = {
2305 "pv0",
2306 "pu6",
2307 "gmi_cs0_n_pj0",
2308 "gmi_cs4_n_pk2",
2309 "gmi_ad11_ph3",
2310 "kb_col0_pq0",
2311 "spdif_in_pk6",
2312 "usb_vbus_en0_pn4",
2313 "usb_vbus_en1_pn5",
2314 };
2315
2316 static const char * const vgp1_groups[] = {
2317 "cam_i2c_scl_pbb1",
2318 };
2319
2320 static const char * const vgp2_groups[] = {
2321 "cam_i2c_sda_pbb2",
2322 };
2323
2324 static const char * const vgp3_groups[] = {
2325 "pbb3",
2326 };
2327
2328 static const char * const vgp4_groups[] = {
2329 "pbb4",
2330 };
2331
2332 static const char * const vgp5_groups[] = {
2333 "pbb5",
2334 };
2335
2336 static const char * const vgp6_groups[] = {
2337 "pbb6",
2338 };
2339
2340 static const char * const vi_groups[] = {
2341 "cam_mclk_pcc0",
2342 "pbb0",
2343 };
2344
2345 static const char * const vi_alt1_groups[] = {
2346 "cam_mclk_pcc0",
2347 "pbb0",
2348 };
2349
2350 static const char * const vi_alt3_groups[] = {
2351 "cam_mclk_pcc0",
2352 "pbb0",
2353 };
2354
2355 #define FUNCTION(fname) \
2356 { \
2357 .name = #fname, \
2358 .groups = fname##_groups, \
2359 .ngroups = ARRAY_SIZE(fname##_groups), \
2360 }
2361
2362 static const struct tegra_function tegra114_functions[] = {
2363 FUNCTION(blink),
2364 FUNCTION(cec),
2365 FUNCTION(cldvfs),
2366 FUNCTION(clk12),
2367 FUNCTION(cpu),
2368 FUNCTION(dap),
2369 FUNCTION(dap1),
2370 FUNCTION(dap2),
2371 FUNCTION(dev3),
2372 FUNCTION(displaya),
2373 FUNCTION(displaya_alt),
2374 FUNCTION(displayb),
2375 FUNCTION(dtv),
2376 FUNCTION(emc_dll),
2377 FUNCTION(extperiph1),
2378 FUNCTION(extperiph2),
2379 FUNCTION(extperiph3),
2380 FUNCTION(gmi),
2381 FUNCTION(gmi_alt),
2382 FUNCTION(hda),
2383 FUNCTION(hsi),
2384 FUNCTION(i2c1),
2385 FUNCTION(i2c2),
2386 FUNCTION(i2c3),
2387 FUNCTION(i2c4),
2388 FUNCTION(i2cpwr),
2389 FUNCTION(i2s0),
2390 FUNCTION(i2s1),
2391 FUNCTION(i2s2),
2392 FUNCTION(i2s3),
2393 FUNCTION(i2s4),
2394 FUNCTION(irda),
2395 FUNCTION(kbc),
2396 FUNCTION(nand),
2397 FUNCTION(nand_alt),
2398 FUNCTION(owr),
2399 FUNCTION(pmi),
2400 FUNCTION(pwm0),
2401 FUNCTION(pwm1),
2402 FUNCTION(pwm2),
2403 FUNCTION(pwm3),
2404 FUNCTION(pwron),
2405 FUNCTION(reset_out_n),
2406 FUNCTION(rsvd1),
2407 FUNCTION(rsvd2),
2408 FUNCTION(rsvd3),
2409 FUNCTION(rsvd4),
2410 FUNCTION(sdmmc1),
2411 FUNCTION(sdmmc2),
2412 FUNCTION(sdmmc3),
2413 FUNCTION(sdmmc4),
2414 FUNCTION(soc),
2415 FUNCTION(spdif),
2416 FUNCTION(spi1),
2417 FUNCTION(spi2),
2418 FUNCTION(spi3),
2419 FUNCTION(spi4),
2420 FUNCTION(spi5),
2421 FUNCTION(spi6),
2422 FUNCTION(sysclk),
2423 FUNCTION(trace),
2424 FUNCTION(uarta),
2425 FUNCTION(uartb),
2426 FUNCTION(uartc),
2427 FUNCTION(uartd),
2428 FUNCTION(ulpi),
2429 FUNCTION(usb),
2430 FUNCTION(vgp1),
2431 FUNCTION(vgp2),
2432 FUNCTION(vgp3),
2433 FUNCTION(vgp4),
2434 FUNCTION(vgp5),
2435 FUNCTION(vgp6),
2436 FUNCTION(vi),
2437 FUNCTION(vi_alt1),
2438 FUNCTION(vi_alt3),
2439 };
2440
2441 #define DRV_PINGROUP_REG_START 0x868 /* bank 0 */
2442 #define PINGROUP_REG_START 0x3000 /* bank 1 */
2443
2444 #define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_START)
2445 #define PINGROUP_REG_N(r) -1
2446
2447 #define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior, rcv_sel) \
2448 { \
2449 .name = #pg_name, \
2450 .pins = pg_name##_pins, \
2451 .npins = ARRAY_SIZE(pg_name##_pins), \
2452 .funcs = { \
2453 TEGRA_MUX_##f0, \
2454 TEGRA_MUX_##f1, \
2455 TEGRA_MUX_##f2, \
2456 TEGRA_MUX_##f3, \
2457 }, \
2458 .func_safe = TEGRA_MUX_##f_safe, \
2459 .mux_reg = PINGROUP_REG_Y(r), \
2460 .mux_bank = 1, \
2461 .mux_bit = 0, \
2462 .pupd_reg = PINGROUP_REG_Y(r), \
2463 .pupd_bank = 1, \
2464 .pupd_bit = 2, \
2465 .tri_reg = PINGROUP_REG_Y(r), \
2466 .tri_bank = 1, \
2467 .tri_bit = 4, \
2468 .einput_reg = PINGROUP_REG_Y(r), \
2469 .einput_bank = 1, \
2470 .einput_bit = 5, \
2471 .odrain_reg = PINGROUP_REG_##od(r), \
2472 .odrain_bank = 1, \
2473 .odrain_bit = 6, \
2474 .lock_reg = PINGROUP_REG_Y(r), \
2475 .lock_bank = 1, \
2476 .lock_bit = 7, \
2477 .ioreset_reg = PINGROUP_REG_##ior(r), \
2478 .ioreset_bank = 1, \
2479 .ioreset_bit = 8, \
2480 .rcv_sel_reg = PINGROUP_REG_##rcv_sel(r), \
2481 .rcv_sel_bank = 1, \
2482 .rcv_sel_bit = 9, \
2483 .drv_reg = -1, \
2484 .drvtype_reg = -1, \
2485 }
2486
2487 #define DRV_PINGROUP_DVRTYPE_Y(r) ((r) - DRV_PINGROUP_REG_START)
2488 #define DRV_PINGROUP_DVRTYPE_N(r) -1
2489
2490 #define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
2491 drvdn_b, drvdn_w, drvup_b, drvup_w, \
2492 slwr_b, slwr_w, slwf_b, slwf_w, \
2493 drvtype) \
2494 { \
2495 .name = "drive_" #pg_name, \
2496 .pins = drive_##pg_name##_pins, \
2497 .npins = ARRAY_SIZE(drive_##pg_name##_pins), \
2498 .mux_reg = -1, \
2499 .pupd_reg = -1, \
2500 .tri_reg = -1, \
2501 .einput_reg = -1, \
2502 .odrain_reg = -1, \
2503 .lock_reg = -1, \
2504 .ioreset_reg = -1, \
2505 .rcv_sel_reg = -1, \
2506 .drv_reg = DRV_PINGROUP_DVRTYPE_Y(r), \
2507 .drv_bank = 0, \
2508 .hsm_bit = hsm_b, \
2509 .schmitt_bit = schmitt_b, \
2510 .lpmd_bit = lpmd_b, \
2511 .drvdn_bit = drvdn_b, \
2512 .drvdn_width = drvdn_w, \
2513 .drvup_bit = drvup_b, \
2514 .drvup_width = drvup_w, \
2515 .slwr_bit = slwr_b, \
2516 .slwr_width = slwr_w, \
2517 .slwf_bit = slwf_b, \
2518 .slwf_width = slwf_w, \
2519 .drvtype_reg = DRV_PINGROUP_DVRTYPE_##drvtype(r), \
2520 .drvtype_bank = 0, \
2521 .drvtype_bit = 6, \
2522 }
2523
2524 static const struct tegra_pingroup tegra114_groups[] = {
2525 /* pg_name, f0, f1, f2, f3, safe, r, od, ior, rcv_sel */
2526 /* FIXME: Fill in correct data in safe column */
2527 PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, ULPI, 0x3000, N, N, N),
2528 PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, ULPI, 0x3004, N, N, N),
2529 PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, ULPI, 0x3008, N, N, N),
2530 PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, ULPI, 0x300c, N, N, N),
2531 PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, ULPI, 0x3010, N, N, N),
2532 PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, ULPI, 0x3014, N, N, N),
2533 PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, ULPI, 0x3018, N, N, N),
2534 PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, ULPI, 0x301c, N, N, N),
2535 PINGROUP(ulpi_clk_py0, SPI1, SPI5, UARTD, ULPI, ULPI, 0x3020, N, N, N),
2536 PINGROUP(ulpi_dir_py1, SPI1, SPI5, UARTD, ULPI, ULPI, 0x3024, N, N, N),
2537 PINGROUP(ulpi_nxt_py2, SPI1, SPI5, UARTD, ULPI, ULPI, 0x3028, N, N, N),
2538 PINGROUP(ulpi_stp_py3, SPI1, SPI5, UARTD, ULPI, ULPI, 0x302c, N, N, N),
2539 PINGROUP(dap3_fs_pp0, I2S2, SPI5, DISPLAYA, DISPLAYB, I2S2, 0x3030, N, N, N),
2540 PINGROUP(dap3_din_pp1, I2S2, SPI5, DISPLAYA, DISPLAYB, I2S2, 0x3034, N, N, N),
2541 PINGROUP(dap3_dout_pp2, I2S2, SPI5, DISPLAYA, DISPLAYB, I2S2, 0x3038, N, N, N),
2542 PINGROUP(dap3_sclk_pp3, I2S2, SPI5, DISPLAYA, DISPLAYB, I2S2, 0x303c, N, N, N),
2543 PINGROUP(pv0, USB, RSVD2, RSVD3, RSVD4, RSVD4, 0x3040, N, N, N),
2544 PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, RSVD4, 0x3044, N, N, N),
2545 PINGROUP(sdmmc1_clk_pz0, SDMMC1, CLK12, RSVD3, RSVD4, RSVD4, 0x3048, N, N, N),
2546 PINGROUP(sdmmc1_cmd_pz1, SDMMC1, SPDIF, SPI4, UARTA, SDMMC1, 0x304c, N, N, N),
2547 PINGROUP(sdmmc1_dat3_py4, SDMMC1, SPDIF, SPI4, UARTA, SDMMC1, 0x3050, N, N, N),
2548 PINGROUP(sdmmc1_dat2_py5, SDMMC1, PWM0, SPI4, UARTA, SDMMC1, 0x3054, N, N, N),
2549 PINGROUP(sdmmc1_dat1_py6, SDMMC1, PWM1, SPI4, UARTA, SDMMC1, 0x3058, N, N, N),
2550 PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, SPI4, UARTA, RSVD2, 0x305c, N, N, N),
2551 PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, RSVD4, 0x3068, N, N, N),
2552 PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, RSVD4, 0x306c, N, N, N),
2553 PINGROUP(hdmi_int_pn7, RSVD1, RSVD2, RSVD3, RSVD4, RSVD4, 0x3110, N, N, Y),
2554 PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, RSVD4, 0x3114, N, N, Y),
2555 PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, RSVD4, 0x3118, N, N, Y),
2556 PINGROUP(uart2_rxd_pc3, IRDA, SPDIF, UARTA, SPI4, IRDA, 0x3164, N, N, N),
2557 PINGROUP(uart2_txd_pc2, IRDA, SPDIF, UARTA, SPI4, IRDA, 0x3168, N, N, N),
2558 PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, RSVD3, SPI4, RSVD3, 0x316c, N, N, N),
2559 PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, RSVD3, SPI4, RSVD3, 0x3170, N, N, N),
2560 PINGROUP(uart3_txd_pw6, UARTC, RSVD2, RSVD3, SPI4, RSVD3, 0x3174, N, N, N),
2561 PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, RSVD3, SPI4, RSVD3, 0x3178, N, N, N),
2562 PINGROUP(uart3_cts_n_pa1, UARTC, SDMMC1, DTV, SPI4, UARTC, 0x317c, N, N, N),
2563 PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, DTV, DISPLAYA, UARTC, 0x3180, N, N, N),
2564 PINGROUP(pu0, OWR, UARTA, RSVD3, RSVD4, RSVD4, 0x3184, N, N, N),
2565 PINGROUP(pu1, RSVD1, UARTA, RSVD3, RSVD4, RSVD4, 0x3188, N, N, N),
2566 PINGROUP(pu2, RSVD1, UARTA, RSVD3, RSVD4, RSVD4, 0x318c, N, N, N),
2567 PINGROUP(pu3, PWM0, UARTA, DISPLAYA, DISPLAYB, PWM0, 0x3190, N, N, N),
2568 PINGROUP(pu4, PWM1, UARTA, DISPLAYA, DISPLAYB, PWM1, 0x3194, N, N, N),
2569 PINGROUP(pu5, PWM2, UARTA, DISPLAYA, DISPLAYB, PWM2, 0x3198, N, N, N),
2570 PINGROUP(pu6, PWM3, UARTA, USB, DISPLAYB, PWM3, 0x319c, N, N, N),
2571 PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, RSVD4, 0x31a0, Y, N, N),
2572 PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, RSVD4, 0x31a4, Y, N, N),
2573 PINGROUP(dap4_fs_pp4, I2S3, RSVD2, DTV, RSVD4, RSVD4, 0x31a8, N, N, N),
2574 PINGROUP(dap4_din_pp5, I2S3, RSVD2, RSVD3, RSVD4, RSVD4, 0x31ac, N, N, N),
2575 PINGROUP(dap4_dout_pp6, I2S3, RSVD2, DTV, RSVD4, RSVD4, 0x31b0, N, N, N),
2576 PINGROUP(dap4_sclk_pp7, I2S3, RSVD2, RSVD3, RSVD4, RSVD4, 0x31b4, N, N, N),
2577 PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, RSVD4, 0x31b8, N, N, N),
2578 PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, RSVD4, 0x31bc, N, N, N),
2579 PINGROUP(gmi_wp_n_pc7, RSVD1, NAND, GMI, GMI_ALT, RSVD1, 0x31c0, N, N, N),
2580 PINGROUP(gmi_iordy_pi5, SDMMC2, RSVD2, GMI, TRACE, RSVD2, 0x31c4, N, N, N),
2581 PINGROUP(gmi_wait_pi7, SPI4, NAND, GMI, DTV, NAND, 0x31c8, N, N, N),
2582 PINGROUP(gmi_adv_n_pk0, RSVD1, NAND, GMI, TRACE, RSVD1, 0x31cc, N, N, N),
2583 PINGROUP(gmi_clk_pk1, SDMMC2, NAND, GMI, TRACE, GMI, 0x31d0, N, N, N),
2584 PINGROUP(gmi_cs0_n_pj0, RSVD1, NAND, GMI, USB, RSVD1, 0x31d4, N, N, N),
2585 PINGROUP(gmi_cs1_n_pj2, RSVD1, NAND, GMI, SOC, RSVD1, 0x31d8, N, N, N),
2586 PINGROUP(gmi_cs2_n_pk3, SDMMC2, NAND, GMI, TRACE, GMI, 0x31dc, N, N, N),
2587 PINGROUP(gmi_cs3_n_pk4, SDMMC2, NAND, GMI, GMI_ALT, GMI, 0x31e0, N, N, N),
2588 PINGROUP(gmi_cs4_n_pk2, USB, NAND, GMI, TRACE, GMI, 0x31e4, N, N, N),
2589 PINGROUP(gmi_cs6_n_pi3, NAND, NAND_ALT, GMI, SPI4, NAND, 0x31e8, N, N, N),
2590 PINGROUP(gmi_cs7_n_pi6, NAND, NAND_ALT, GMI, SDMMC2, NAND, 0x31ec, N, N, N),
2591 PINGROUP(gmi_ad0_pg0, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31f0, N, N, N),
2592 PINGROUP(gmi_ad1_pg1, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31f4, N, N, N),
2593 PINGROUP(gmi_ad2_pg2, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31f8, N, N, N),
2594 PINGROUP(gmi_ad3_pg3, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x31fc, N, N, N),
2595 PINGROUP(gmi_ad4_pg4, RSVD1, NAND, GMI, RSVD4, RSVD4, 0x3200, N, N, N),
2596 PINGROUP(gmi_ad5_pg5, RSVD1, NAND, GMI, SPI4, RSVD1, 0x3204, N, N, N),
2597 PINGROUP(gmi_ad6_pg6, RSVD1, NAND, GMI, SPI4, RSVD1, 0x3208, N, N, N),
2598 PINGROUP(gmi_ad7_pg7, RSVD1, NAND, GMI, SPI4, RSVD1, 0x320c, N, N, N),
2599 PINGROUP(gmi_ad8_ph0, PWM0, NAND, GMI, DTV, GMI, 0x3210, N, N, N),
2600 PINGROUP(gmi_ad9_ph1, PWM1, NAND, GMI, CLDVFS, GMI, 0x3214, N, N, N),
2601 PINGROUP(gmi_ad10_ph2, PWM2, NAND, GMI, CLDVFS, GMI, 0x3218, N, N, N),
2602 PINGROUP(gmi_ad11_ph3, PWM3, NAND, GMI, USB, GMI, 0x321c, N, N, N),
2603 PINGROUP(gmi_ad12_ph4, SDMMC2, NAND, GMI, RSVD4, RSVD4, 0x3220, N, N, N),
2604 PINGROUP(gmi_ad13_ph5, SDMMC2, NAND, GMI, RSVD4, RSVD4, 0x3224, N, N, N),
2605 PINGROUP(gmi_ad14_ph6, SDMMC2, NAND, GMI, DTV, GMI, 0x3228, N, N, N),
2606 PINGROUP(gmi_ad15_ph7, SDMMC2, NAND, GMI, DTV, GMI, 0x322c, N, N, N),
2607 PINGROUP(gmi_a16_pj7, UARTD, TRACE, GMI, GMI_ALT, GMI, 0x3230, N, N, N),
2608 PINGROUP(gmi_a17_pb0, UARTD, RSVD2, GMI, TRACE, RSVD2, 0x3234, N, N, N),
2609 PINGROUP(gmi_a18_pb1, UARTD, RSVD2, GMI, TRACE, RSVD2, 0x3238, N, N, N),
2610 PINGROUP(gmi_a19_pk7, UARTD, SPI4, GMI, TRACE, GMI, 0x323c, N, N, N),
2611 PINGROUP(gmi_wr_n_pi0, RSVD1, NAND, GMI, SPI4, RSVD1, 0x3240, N, N, N),
2612 PINGROUP(gmi_oe_n_pi1, RSVD1, NAND, GMI, SOC, RSVD1, 0x3244, N, N, N),
2613 PINGROUP(gmi_dqs_p_pj3, SDMMC2, NAND, GMI, TRACE, NAND, 0x3248, N, N, N),
2614 PINGROUP(gmi_rst_n_pi4, NAND, NAND_ALT, GMI, RSVD4, RSVD4, 0x324c, N, N, N),
2615 PINGROUP(gen2_i2c_scl_pt5, I2C2, RSVD2, GMI, RSVD4, RSVD4, 0x3250, Y, N, N),
2616 PINGROUP(gen2_i2c_sda_pt6, I2C2, RSVD2, GMI, RSVD4, RSVD4, 0x3254, Y, N, N),
2617 PINGROUP(sdmmc4_clk_pcc4, SDMMC4, RSVD2, GMI, RSVD4, RSVD4, 0x3258, N, Y, N),
2618 PINGROUP(sdmmc4_cmd_pt7, SDMMC4, RSVD2, GMI, RSVD4, RSVD4, 0x325c, N, Y, N),
2619 PINGROUP(sdmmc4_dat0_paa0, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x3260, N, Y, N),
2620 PINGROUP(sdmmc4_dat1_paa1, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x3264, N, Y, N),
2621 PINGROUP(sdmmc4_dat2_paa2, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x3268, N, Y, N),
2622 PINGROUP(sdmmc4_dat3_paa3, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x326c, N, Y, N),
2623 PINGROUP(sdmmc4_dat4_paa4, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x3270, N, Y, N),
2624 PINGROUP(sdmmc4_dat5_paa5, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x3274, N, Y, N),
2625 PINGROUP(sdmmc4_dat6_paa6, SDMMC4, SPI3, GMI, RSVD4, RSVD4, 0x3278, N, Y, N),
2626 PINGROUP(sdmmc4_dat7_paa7, SDMMC4, RSVD2, GMI, RSVD4, RSVD4, 0x327c, N, Y, N),
2627 PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, RSVD4, RSVD4, 0x3284, N, N, N),
2628 PINGROUP(pcc1, I2S4, RSVD2, RSVD3, RSVD4, RSVD4, 0x3288, N, N, N),
2629 PINGROUP(pbb0, I2S4, VI, VI_ALT1, VI_ALT3, I2S4, 0x328c, N, N, N),
2630 PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, RSVD4, RSVD4, 0x3290, Y, N, N),
2631 PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, RSVD4, RSVD4, 0x3294, Y, N, N),
2632 PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, RSVD4, RSVD4, 0x3298, N, N, N),
2633 PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, RSVD4, RSVD4, 0x329c, N, N, N),
2634 PINGROUP(pbb5, VGP5, DISPLAYA, DISPLAYB, RSVD4, RSVD4, 0x32a0, N, N, N),
2635 PINGROUP(pbb6, VGP6, DISPLAYA, DISPLAYB, RSVD4, RSVD4, 0x32a4, N, N, N),
2636 PINGROUP(pbb7, I2S4, RSVD2, RSVD3, RSVD4, RSVD4, 0x32a8, N, N, N),
2637 PINGROUP(pcc2, I2S4, RSVD2, RSVD3, RSVD4, RSVD4, 0x32ac, N, N, N),
2638 PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x32b4, Y, N, N),
2639 PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x32b8, Y, N, N),
2640 PINGROUP(kb_row0_pr0, KBC, RSVD2, RSVD3, RSVD4, RSVD4, 0x32bc, N, N, N),
2641 PINGROUP(kb_row1_pr1, KBC, RSVD2, RSVD3, RSVD4, RSVD4, 0x32c0, N, N, N),
2642 PINGROUP(kb_row2_pr2, KBC, RSVD2, RSVD3, RSVD4, RSVD4, 0x32c4, N, N, N),
2643 PINGROUP(kb_row3_pr3, KBC, DISPLAYA, RSVD3, DISPLAYB, RSVD3, 0x32c8, N, N, N),
2644 PINGROUP(kb_row4_pr4, KBC, DISPLAYA, SPI2, DISPLAYB, KBC, 0x32cc, N, N, N),
2645 PINGROUP(kb_row5_pr5, KBC, DISPLAYA, SPI2, DISPLAYB, KBC, 0x32d0, N, N, N),
2646 PINGROUP(kb_row6_pr6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB, KBC, 0x32d4, N, N, N),
2647 PINGROUP(kb_row7_pr7, KBC, RSVD2, CLDVFS, UARTA, RSVD2, 0x32d8, N, N, N),
2648 PINGROUP(kb_row8_ps0, KBC, RSVD2, CLDVFS, UARTA, RSVD2, 0x32dc, N, N, N),
2649 PINGROUP(kb_row9_ps1, KBC, RSVD2, RSVD3, UARTA, RSVD3, 0x32e0, N, N, N),
2650 PINGROUP(kb_row10_ps2, KBC, RSVD2, RSVD3, UARTA, RSVD3, 0x32e4, N, N, N),
2651 PINGROUP(kb_col0_pq0, KBC, USB, SPI2, EMC_DLL, KBC, 0x32fc, N, N, N),
2652 PINGROUP(kb_col1_pq1, KBC, RSVD2, SPI2, EMC_DLL, RSVD2, 0x3300, N, N, N),
2653 PINGROUP(kb_col2_pq2, KBC, RSVD2, SPI2, RSVD4, RSVD2, 0x3304, N, N, N),
2654 PINGROUP(kb_col3_pq3, KBC, DISPLAYA, PWM2, UARTA, KBC, 0x3308, N, N, N),
2655 PINGROUP(kb_col4_pq4, KBC, OWR, SDMMC3, UARTA, KBC, 0x330c, N, N, N),
2656 PINGROUP(kb_col5_pq5, KBC, RSVD2, SDMMC1, RSVD4, RSVD4, 0x3310, N, N, N),
2657 PINGROUP(kb_col6_pq6, KBC, RSVD2, SPI2, RSVD4, RSVD4, 0x3314, N, N, N),
2658 PINGROUP(kb_col7_pq7, KBC, RSVD2, SPI2, RSVD4, RSVD4, 0x3318, N, N, N),
2659 PINGROUP(clk_32k_out_pa0, BLINK, SOC, RSVD3, RSVD4, RSVD4, 0x331c, N, N, N),
2660 PINGROUP(sys_clk_req_pz5, SYSCLK, RSVD2, RSVD3, RSVD4, RSVD4, 0x3320, N, N, N),
2661 PINGROUP(core_pwr_req, PWRON, RSVD2, RSVD3, RSVD4, RSVD4, 0x3324, N, N, N),
2662 PINGROUP(cpu_pwr_req, CPU, RSVD2, RSVD3, RSVD4, RSVD4, 0x3328, N, N, N),
2663 PINGROUP(pwr_int_n, PMI, RSVD2, RSVD3, RSVD4, RSVD4, 0x332c, N, N, N),
2664 PINGROUP(owr, OWR, RSVD2, RSVD3, RSVD4, RSVD4, 0x3334, N, N, Y),
2665 PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, RSVD4, RSVD4, 0x3338, N, N, N),
2666 PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, RSVD4, RSVD4, 0x333c, N, N, N),
2667 PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, RSVD4, RSVD4, 0x3340, N, N, N),
2668 PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, RSVD4, RSVD4, 0x3344, N, N, N),
2669 PINGROUP(clk1_req_pee2, DAP, DAP1, RSVD3, RSVD4, RSVD4, 0x3348, N, N, N),
2670 PINGROUP(clk1_out_pw4, EXTPERIPH1, DAP2, RSVD3, RSVD4, RSVD4, 0x334c, N, N, N),
2671 PINGROUP(spdif_in_pk6, SPDIF, USB, RSVD3, RSVD4, RSVD4, 0x3350, N, N, N),
2672 PINGROUP(spdif_out_pk5, SPDIF, RSVD2, RSVD3, RSVD4, RSVD4, 0x3354, N, N, N),
2673 PINGROUP(dap2_fs_pa2, I2S1, HDA, RSVD3, RSVD4, RSVD4, 0x3358, N, N, N),
2674 PINGROUP(dap2_din_pa4, I2S1, HDA, RSVD3, RSVD4, RSVD4, 0x335c, N, N, N),
2675 PINGROUP(dap2_dout_pa5, I2S1, HDA, RSVD3, RSVD4, RSVD4, 0x3360, N, N, N),
2676 PINGROUP(dap2_sclk_pa3, I2S1, HDA, RSVD3, RSVD4, RSVD4, 0x3364, N, N, N),
2677 PINGROUP(dvfs_pwm_px0, SPI6, CLDVFS, RSVD3, RSVD4, RSVD4, 0x3368, N, N, N),
2678 PINGROUP(gpio_x1_aud_px1, SPI6, RSVD2, RSVD3, RSVD4, RSVD4, 0x336c, N, N, N),
2679 PINGROUP(gpio_x3_aud_px3, SPI6, SPI1, RSVD3, RSVD4, RSVD4, 0x3370, N, N, N),
2680 PINGROUP(dvfs_clk_px2, SPI6, CLDVFS, RSVD3, RSVD4, RSVD4, 0x3374, N, N, N),
2681 PINGROUP(gpio_x4_aud_px4, RSVD1, SPI1, SPI2, DAP2, RSVD1, 0x3378, N, N, N),
2682 PINGROUP(gpio_x5_aud_px5, RSVD1, SPI1, SPI2, RSVD4, RSVD1, 0x337c, N, N, N),
2683 PINGROUP(gpio_x6_aud_px6, SPI6, SPI1, SPI2, RSVD4, RSVD4, 0x3380, N, N, N),
2684 PINGROUP(gpio_x7_aud_px7, RSVD1, SPI1, SPI2, RSVD4, RSVD4, 0x3384, N, N, N),
2685 PINGROUP(sdmmc3_clk_pa6, SDMMC3, RSVD2, RSVD3, SPI3, RSVD3, 0x3390, N, N, N),
2686 PINGROUP(sdmmc3_cmd_pa7, SDMMC3, PWM3, UARTA, SPI3, SDMMC3, 0x3394, N, N, N),
2687 PINGROUP(sdmmc3_dat0_pb7, SDMMC3, RSVD2, RSVD3, SPI3, RSVD3, 0x3398, N, N, N),
2688 PINGROUP(sdmmc3_dat1_pb6, SDMMC3, PWM2, UARTA, SPI3, SDMMC3, 0x339c, N, N, N),
2689 PINGROUP(sdmmc3_dat2_pb5, SDMMC3, PWM1, DISPLAYA, SPI3, SDMMC3, 0x33a0, N, N, N),
2690 PINGROUP(sdmmc3_dat3_pb4, SDMMC3, PWM0, DISPLAYB, SPI3, SDMMC3, 0x33a4, N, N, N),
2691 PINGROUP(hdmi_cec_pee3, CEC, SDMMC3, RSVD3, SOC, RSVD3, 0x33e0, Y, N, N),
2692 PINGROUP(sdmmc1_wp_n_pv3, SDMMC1, CLK12, SPI4, UARTA, SDMMC1, 0x33e4, N, N, N),
2693 PINGROUP(sdmmc3_cd_n_pv2, SDMMC3, OWR, RSVD3, RSVD4, RSVD4, 0x33e8, N, N, N),
2694 PINGROUP(gpio_w2_aud_pw2, SPI6, RSVD2, SPI2, I2C1, RSVD2, 0x33ec, N, N, N),
2695 PINGROUP(gpio_w3_aud_pw3, SPI6, SPI1, SPI2, I2C1, SPI6, 0x33f0, N, N, N),
2696 PINGROUP(usb_vbus_en0_pn4, USB, RSVD2, RSVD3, RSVD4, RSVD4, 0x33f4, Y, N, N),
2697 PINGROUP(usb_vbus_en1_pn5, USB, RSVD2, RSVD3, RSVD4, RSVD4, 0x33f8, Y, N, N),
2698 PINGROUP(sdmmc3_clk_lb_in_pee5, SDMMC3, RSVD2, RSVD3, RSVD4, RSVD4, 0x33fc, N, N, N),
2699 PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3, RSVD2, RSVD3, RSVD4, RSVD4, 0x3400, N, N, N),
2700 PINGROUP(reset_out_n, RSVD1, RSVD2, RSVD3, RESET_OUT_N, RSVD3, 0x3408, N, N, N),
2701
2702 /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */
2703 DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2704 DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2705 DRV_PINGROUP(at1, 0x870, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
2706 DRV_PINGROUP(at2, 0x874, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
2707 DRV_PINGROUP(at3, 0x878, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
2708 DRV_PINGROUP(at4, 0x87c, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
2709 DRV_PINGROUP(at5, 0x880, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
2710 DRV_PINGROUP(cdev1, 0x884, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2711 DRV_PINGROUP(cdev2, 0x888, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2712 DRV_PINGROUP(dap1, 0x890, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2713 DRV_PINGROUP(dap2, 0x894, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2714 DRV_PINGROUP(dap3, 0x898, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2715 DRV_PINGROUP(dap4, 0x89c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2716 DRV_PINGROUP(dbg, 0x8a0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2717 DRV_PINGROUP(sdio3, 0x8b0, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
2718 DRV_PINGROUP(spi, 0x8b4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2719 DRV_PINGROUP(uaa, 0x8b8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2720 DRV_PINGROUP(uab, 0x8bc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2721 DRV_PINGROUP(uart2, 0x8c0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2722 DRV_PINGROUP(uart3, 0x8c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2723 DRV_PINGROUP(sdio1, 0x8ec, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
2724 DRV_PINGROUP(ddc, 0x8fc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2725 DRV_PINGROUP(gma, 0x900, 2, 3, 4, 14, 5, 20, 5, 28, 2, 30, 2, Y),
2726 DRV_PINGROUP(gme, 0x910, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
2727 DRV_PINGROUP(gmf, 0x914, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
2728 DRV_PINGROUP(gmg, 0x918, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
2729 DRV_PINGROUP(gmh, 0x91c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
2730 DRV_PINGROUP(owr, 0x920, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2731 DRV_PINGROUP(uda, 0x924, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2732 };
2733
2734 static const struct tegra_pinctrl_soc_data tegra114_pinctrl = {
2735 .ngpios = NUM_GPIOS,
2736 .pins = tegra114_pins,
2737 .npins = ARRAY_SIZE(tegra114_pins),
2738 .functions = tegra114_functions,
2739 .nfunctions = ARRAY_SIZE(tegra114_functions),
2740 .groups = tegra114_groups,
2741 .ngroups = ARRAY_SIZE(tegra114_groups),
2742 };
2743
tegra114_pinctrl_probe(struct platform_device * pdev)2744 static int tegra114_pinctrl_probe(struct platform_device *pdev)
2745 {
2746 return tegra_pinctrl_probe(pdev, &tegra114_pinctrl);
2747 }
2748
2749 static struct of_device_id tegra114_pinctrl_of_match[] = {
2750 { .compatible = "nvidia,tegra114-pinmux", },
2751 { },
2752 };
2753 MODULE_DEVICE_TABLE(of, tegra114_pinctrl_of_match);
2754
2755 static struct platform_driver tegra114_pinctrl_driver = {
2756 .driver = {
2757 .name = "tegra114-pinctrl",
2758 .owner = THIS_MODULE,
2759 .of_match_table = tegra114_pinctrl_of_match,
2760 },
2761 .probe = tegra114_pinctrl_probe,
2762 .remove = tegra_pinctrl_remove,
2763 };
2764 module_platform_driver(tegra114_pinctrl_driver);
2765
2766 MODULE_ALIAS("platform:tegra114-pinctrl");
2767 MODULE_AUTHOR("Pritesh Raithatha <praithatha@nvidia.com>");
2768 MODULE_DESCRIPTION("NVIDIA Tegra114 pincontrol driver");
2769 MODULE_LICENSE("GPL v2");
2770