1 /*
2 * sh73a0 processor support - PFC hardware block
3 *
4 * Copyright (C) 2010 Renesas Solutions Corp.
5 * Copyright (C) 2010 NISHIMOTO Hiroki
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of the
10 * License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21 #include <linux/io.h>
22 #include <linux/kernel.h>
23 #include <linux/pinctrl/pinconf-generic.h>
24
25 #include <mach/sh73a0.h>
26 #include <mach/irqs.h>
27
28 #include "core.h"
29 #include "sh_pfc.h"
30
31 #define CPU_ALL_PORT(fn, pfx, sfx) \
32 PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
33 PORT_10(fn, pfx##10, sfx), \
34 PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \
35 PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \
36 PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx), \
37 PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx), \
38 PORT_1(fn, pfx##118, sfx), \
39 PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \
40 PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx), \
41 PORT_10(fn, pfx##15, sfx), \
42 PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx), \
43 PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx), \
44 PORT_1(fn, pfx##164, sfx), \
45 PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \
46 PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \
47 PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \
48 PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \
49 PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \
50 PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \
51 PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \
52 PORT_10(fn, pfx##26, sfx), PORT_10(fn, pfx##27, sfx), \
53 PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \
54 PORT_1(fn, pfx##282, sfx), \
55 PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \
56 PORT_10(fn, pfx##29, sfx), PORT_10(fn, pfx##30, sfx)
57
58 enum {
59 PINMUX_RESERVED = 0,
60
61 PINMUX_DATA_BEGIN,
62 PORT_ALL(DATA), /* PORT0_DATA -> PORT309_DATA */
63 PINMUX_DATA_END,
64
65 PINMUX_INPUT_BEGIN,
66 PORT_ALL(IN), /* PORT0_IN -> PORT309_IN */
67 PINMUX_INPUT_END,
68
69 PINMUX_OUTPUT_BEGIN,
70 PORT_ALL(OUT), /* PORT0_OUT -> PORT309_OUT */
71 PINMUX_OUTPUT_END,
72
73 PINMUX_FUNCTION_BEGIN,
74 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT309_FN_IN */
75 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT309_FN_OUT */
76 PORT_ALL(FN0), /* PORT0_FN0 -> PORT309_FN0 */
77 PORT_ALL(FN1), /* PORT0_FN1 -> PORT309_FN1 */
78 PORT_ALL(FN2), /* PORT0_FN2 -> PORT309_FN2 */
79 PORT_ALL(FN3), /* PORT0_FN3 -> PORT309_FN3 */
80 PORT_ALL(FN4), /* PORT0_FN4 -> PORT309_FN4 */
81 PORT_ALL(FN5), /* PORT0_FN5 -> PORT309_FN5 */
82 PORT_ALL(FN6), /* PORT0_FN6 -> PORT309_FN6 */
83 PORT_ALL(FN7), /* PORT0_FN7 -> PORT309_FN7 */
84
85 MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
86 MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
87 MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
88 MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
89 MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
90 MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
91 MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
92 MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
93 MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
94 MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
95 MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
96 MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
97 MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
98 MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
99 MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
100 MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
101 MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
102 MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
103 MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
104 MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
105 MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
106 MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
107 MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
108 MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
109 MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
110 MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
111 MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
112 MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
113 MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
114 MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
115 MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
116 MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
117 MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
118 MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
119 MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
120 MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
121 MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
122 MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
123 MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
124 MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
125 MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
126 MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
127 PINMUX_FUNCTION_END,
128
129 PINMUX_MARK_BEGIN,
130 /* Hardware manual Table 25-1 (Function 0-7) */
131 VBUS_0_MARK,
132 GPI0_MARK,
133 GPI1_MARK,
134 GPI2_MARK,
135 GPI3_MARK,
136 GPI4_MARK,
137 GPI5_MARK,
138 GPI6_MARK,
139 GPI7_MARK,
140 SCIFA7_RXD_MARK,
141 SCIFA7_CTS__MARK,
142 GPO7_MARK, MFG0_OUT2_MARK,
143 GPO6_MARK, MFG1_OUT2_MARK,
144 GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK,
145 SCIFA0_TXD_MARK,
146 SCIFA7_TXD_MARK,
147 SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK,
148 GPO0_MARK,
149 GPO1_MARK,
150 GPO2_MARK, STATUS0_MARK,
151 GPO3_MARK, STATUS1_MARK,
152 GPO4_MARK, STATUS2_MARK,
153 VINT_MARK,
154 TCKON_MARK,
155 XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \
156 MFG0_OUT1_MARK, PORT27_IROUT_MARK,
157 XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \
158 PORT28_TPU1TO1_MARK,
159 SIM_RST_MARK, PORT29_TPU1TO1_MARK,
160 SIM_CLK_MARK, PORT30_VIO_CKOR_MARK,
161 SIM_D_MARK, PORT31_IROUT_MARK,
162 SCIFA4_TXD_MARK,
163 SCIFA4_RXD_MARK, XWUP_MARK,
164 SCIFA4_RTS__MARK,
165 SCIFA4_CTS__MARK,
166 FSIBOBT_MARK, FSIBIBT_MARK,
167 FSIBOLR_MARK, FSIBILR_MARK,
168 FSIBOSLD_MARK,
169 FSIBISLD_MARK,
170 VACK_MARK,
171 XTAL1L_MARK,
172 SCIFA0_RTS__MARK, FSICOSLDT2_MARK,
173 SCIFA0_RXD_MARK,
174 SCIFA0_CTS__MARK, FSICOSLDT1_MARK,
175 FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK,
176 FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK,
177 FSICOSLD_MARK, PORT47_FSICSPDIF_MARK,
178 FSICISLD_MARK, FSIDISLD_MARK,
179 FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK,
180 FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK,
181
182 FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK,
183 FSIAOSLD_MARK, BBIF2_TXD2_MARK,
184 FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \
185 PORT53_FSICSPDIF_MARK,
186 FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \
187 FSICCK_MARK, FSICOMC_MARK,
188 FSIAISLD_MARK, TPU0TO0_MARK,
189 A0_MARK, BS__MARK,
190 A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK,
191 A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK,
192 A14_MARK, KEYOUT5_MARK,
193 A15_MARK, KEYOUT4_MARK,
194 A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK,
195 A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
196 A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK,
197 A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK,
198 A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK,
199 A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK,
200 A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK,
201 A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK,
202 A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK,
203 A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK,
204 A26_MARK, KEYIN6_MARK,
205 KEYIN7_MARK,
206 D0_NAF0_MARK,
207 D1_NAF1_MARK,
208 D2_NAF2_MARK,
209 D3_NAF3_MARK,
210 D4_NAF4_MARK,
211 D5_NAF5_MARK,
212 D6_NAF6_MARK,
213 D7_NAF7_MARK,
214 D8_NAF8_MARK,
215 D9_NAF9_MARK,
216 D10_NAF10_MARK,
217 D11_NAF11_MARK,
218 D12_NAF12_MARK,
219 D13_NAF13_MARK,
220 D14_NAF14_MARK,
221 D15_NAF15_MARK,
222 CS4__MARK,
223 CS5A__MARK, PORT91_RDWR_MARK,
224 CS5B__MARK, FCE1__MARK,
225 CS6B__MARK, DACK0_MARK,
226 FCE0__MARK, CS6A__MARK,
227 WAIT__MARK, DREQ0_MARK,
228 RD__FSC_MARK,
229 WE0__FWE_MARK, RDWR_FWE_MARK,
230 WE1__MARK,
231 FRB_MARK,
232 CKO_MARK,
233 NBRSTOUT__MARK,
234 NBRST__MARK,
235 BBIF2_TXD_MARK,
236 BBIF2_RXD_MARK,
237 BBIF2_SYNC_MARK,
238 BBIF2_SCK_MARK,
239 SCIFA3_CTS__MARK, MFG3_IN2_MARK,
240 SCIFA3_RXD_MARK, MFG3_IN1_MARK,
241 BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK,
242 SCIFA3_TXD_MARK,
243 HSI_RX_DATA_MARK, BBIF1_RXD_MARK,
244 HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK,
245 HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK,
246 HSI_TX_READY_MARK, BBIF1_TXD_MARK,
247 HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \
248 PORT115_I2C_SCL3_MARK,
249 HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \
250 PORT116_I2C_SDA3_MARK,
251 HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK,
252 HSI_TX_FLAG_MARK,
253 VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK,
254
255 VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \
256 VIO2_HD_MARK, LCD2D1_MARK,
257 VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK,
258 VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \
259 PORT131_KEYOUT11_MARK, LCD2D11_MARK,
260 VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \
261 PORT132_KEYOUT10_MARK, LCD2D12_MARK,
262 VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK,
263 VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK,
264 VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK,
265 VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK,
266 VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK,
267 VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK,
268 VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK,
269 VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK,
270 VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK,
271 VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK,
272 VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \
273 VIO2_D5_MARK, LCD2D3_MARK,
274 VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK,
275 VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \
276 PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK,
277 VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \
278 LCD2D18_MARK,
279 VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK,
280 VIO_CKO_MARK,
281 A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK,
282 MFG0_IN2_MARK,
283 TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
284 TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
285 TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
286 SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
287 SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
288 SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK,
289 SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK,
290 DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
291 PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
292 PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK,
293 PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK,
294 PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK,
295 PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK,
296 LCDD0_MARK,
297 LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK,
298 LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK,
299 LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK,
300 LCDD4_MARK, PORT196_SCIFA5_TXD_MARK,
301 LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK,
302 LCDD6_MARK,
303 LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK,
304 LCDD8_MARK, D16_MARK,
305 LCDD9_MARK, D17_MARK,
306 LCDD10_MARK, D18_MARK,
307 LCDD11_MARK, D19_MARK,
308 LCDD12_MARK, D20_MARK,
309 LCDD13_MARK, D21_MARK,
310 LCDD14_MARK, D22_MARK,
311 LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK,
312 LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK,
313 LCDD17_MARK, D25_MARK,
314 LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK,
315 LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK,
316 LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK,
317 LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK,
318 LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK,
319 LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK,
320 LCDDCK_MARK, LCDWR__MARK,
321 LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \
322 VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK,
323 LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \
324 PORT218_VIO_CKOR_MARK,
325 LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \
326 MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK,
327 LCDVSYN_MARK, LCDVSYN2_MARK,
328 LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \
329 MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK,
330 LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \
331 VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK,
332
333 SCIFA1_TXD_MARK, OVCN2_MARK,
334 EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK,
335 SCIFA1_RTS__MARK, IDIN_MARK,
336 SCIFA1_RXD_MARK,
337 SCIFA1_CTS__MARK, MFG1_IN1_MARK,
338 MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK,
339 MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK,
340 MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK,
341 MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK,
342 MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK,
343 MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK,
344 MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK,
345 MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK,
346 MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK,
347 MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK,
348 SCIFA6_TXD_MARK,
349 PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK,
350 PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
351 PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
352 PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \
353 MSIOF2R_RXD_MARK,
354 PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \
355 MSIOF2R_TXD_MARK,
356 PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \
357 TPU1TO0_MARK,
358 PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \
359 TPU3TO1_MARK,
360 PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \
361 TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK,
362 PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \
363 MSIOF2R_TSYNC_MARK,
364 SDHICLK0_MARK,
365 SDHICD0_MARK,
366 SDHID0_0_MARK,
367 SDHID0_1_MARK,
368 SDHID0_2_MARK,
369 SDHID0_3_MARK,
370 SDHICMD0_MARK,
371 SDHIWP0_MARK,
372 SDHICLK1_MARK,
373 SDHID1_0_MARK, TS_SPSYNC2_MARK,
374 SDHID1_1_MARK, TS_SDAT2_MARK,
375 SDHID1_2_MARK, TS_SDEN2_MARK,
376 SDHID1_3_MARK, TS_SCK2_MARK,
377 SDHICMD1_MARK,
378 SDHICLK2_MARK,
379 SDHID2_0_MARK, TS_SPSYNC4_MARK,
380 SDHID2_1_MARK, TS_SDAT4_MARK,
381 SDHID2_2_MARK, TS_SDEN4_MARK,
382 SDHID2_3_MARK, TS_SCK4_MARK,
383 SDHICMD2_MARK,
384 MMCCLK0_MARK,
385 MMCD0_0_MARK,
386 MMCD0_1_MARK,
387 MMCD0_2_MARK,
388 MMCD0_3_MARK,
389 MMCD0_4_MARK, TS_SPSYNC5_MARK,
390 MMCD0_5_MARK, TS_SDAT5_MARK,
391 MMCD0_6_MARK, TS_SDEN5_MARK,
392 MMCD0_7_MARK, TS_SCK5_MARK,
393 MMCCMD0_MARK,
394 RESETOUTS__MARK, EXTAL2OUT_MARK,
395 MCP_WAIT__MCP_FRB_MARK,
396 MCP_CKO_MARK, MMCCLK1_MARK,
397 MCP_D15_MCP_NAF15_MARK,
398 MCP_D14_MCP_NAF14_MARK,
399 MCP_D13_MCP_NAF13_MARK,
400 MCP_D12_MCP_NAF12_MARK,
401 MCP_D11_MCP_NAF11_MARK,
402 MCP_D10_MCP_NAF10_MARK,
403 MCP_D9_MCP_NAF9_MARK,
404 MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK,
405 MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK,
406
407 MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK,
408 MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK,
409 MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK,
410 MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK,
411 MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK,
412 MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK,
413 MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK,
414 MCP_NBRSTOUT__MARK,
415 MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK,
416
417 /* MSEL2 special cases */
418 TSIF2_TS_XX1_MARK,
419 TSIF2_TS_XX2_MARK,
420 TSIF2_TS_XX3_MARK,
421 TSIF2_TS_XX4_MARK,
422 TSIF2_TS_XX5_MARK,
423 TSIF1_TS_XX1_MARK,
424 TSIF1_TS_XX2_MARK,
425 TSIF1_TS_XX3_MARK,
426 TSIF1_TS_XX4_MARK,
427 TSIF1_TS_XX5_MARK,
428 TSIF0_TS_XX1_MARK,
429 TSIF0_TS_XX2_MARK,
430 TSIF0_TS_XX3_MARK,
431 TSIF0_TS_XX4_MARK,
432 TSIF0_TS_XX5_MARK,
433 MST1_TS_XX1_MARK,
434 MST1_TS_XX2_MARK,
435 MST1_TS_XX3_MARK,
436 MST1_TS_XX4_MARK,
437 MST1_TS_XX5_MARK,
438 MST0_TS_XX1_MARK,
439 MST0_TS_XX2_MARK,
440 MST0_TS_XX3_MARK,
441 MST0_TS_XX4_MARK,
442 MST0_TS_XX5_MARK,
443
444 /* MSEL3 special cases */
445 SDHI0_VCCQ_MC0_ON_MARK,
446 SDHI0_VCCQ_MC0_OFF_MARK,
447 DEBUG_MON_VIO_MARK,
448 DEBUG_MON_LCDD_MARK,
449 LCDC_LCDC0_MARK,
450 LCDC_LCDC1_MARK,
451
452 /* MSEL4 special cases */
453 IRQ9_MEM_INT_MARK,
454 IRQ9_MCP_INT_MARK,
455 A11_MARK,
456 KEYOUT8_MARK,
457 TPU4TO3_MARK,
458 RESETA_N_PU_ON_MARK,
459 RESETA_N_PU_OFF_MARK,
460 EDBGREQ_PD_MARK,
461 EDBGREQ_PU_MARK,
462
463 PINMUX_MARK_END,
464 };
465
466 #define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx)
467 #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
468
469 static const pinmux_enum_t pinmux_data[] = {
470 /* specify valid pin states for each pin in GPIO mode */
471 PINMUX_DATA_GP_ALL(),
472
473 /* Table 25-1 (Function 0-7) */
474 PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
475 PINMUX_DATA(GPI0_MARK, PORT1_FN1),
476 PINMUX_DATA(GPI1_MARK, PORT2_FN1),
477 PINMUX_DATA(GPI2_MARK, PORT3_FN1),
478 PINMUX_DATA(GPI3_MARK, PORT4_FN1),
479 PINMUX_DATA(GPI4_MARK, PORT5_FN1),
480 PINMUX_DATA(GPI5_MARK, PORT6_FN1),
481 PINMUX_DATA(GPI6_MARK, PORT7_FN1),
482 PINMUX_DATA(GPI7_MARK, PORT8_FN1),
483 PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2),
484 PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2),
485 PINMUX_DATA(GPO7_MARK, PORT14_FN1), \
486 PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4),
487 PINMUX_DATA(GPO6_MARK, PORT15_FN1), \
488 PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4),
489 PINMUX_DATA(GPO5_MARK, PORT16_FN1), \
490 PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \
491 PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \
492 PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4),
493 PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
494 PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2),
495 PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \
496 PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
497 PINMUX_DATA(GPO0_MARK, PORT20_FN1),
498 PINMUX_DATA(GPO1_MARK, PORT21_FN1),
499 PINMUX_DATA(GPO2_MARK, PORT22_FN1), \
500 PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
501 PINMUX_DATA(GPO3_MARK, PORT23_FN1), \
502 PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
503 PINMUX_DATA(GPO4_MARK, PORT24_FN1), \
504 PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
505 PINMUX_DATA(VINT_MARK, PORT25_FN1),
506 PINMUX_DATA(TCKON_MARK, PORT26_FN1),
507 PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \
508 PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0,
509 MSEL2CR_MSEL16_1), \
510 PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0,
511 MSEL2CR_MSEL18_1), \
512 PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \
513 PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7),
514 PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \
515 PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0,
516 MSEL2CR_MSEL16_1), \
517 PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0,
518 MSEL2CR_MSEL18_1), \
519 PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7),
520 PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \
521 PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4),
522 PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \
523 PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4),
524 PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \
525 PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4),
526 PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
527 PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \
528 PINMUX_DATA(XWUP_MARK, PORT33_FN3),
529 PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2),
530 PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2),
531 PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \
532 PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2),
533 PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \
534 PINMUX_DATA(FSIBILR_MARK, PORT37_FN2),
535 PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1),
536 PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1),
537 PINMUX_DATA(VACK_MARK, PORT40_FN1),
538 PINMUX_DATA(XTAL1L_MARK, PORT41_FN1),
539 PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \
540 PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3),
541 PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
542 PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \
543 PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3),
544 PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \
545 PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \
546 PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \
547 PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4),
548 PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \
549 PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \
550 PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \
551 PINMUX_DATA(FSIDILR_MARK, PORT46_FN4),
552 PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \
553 PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2),
554 PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \
555 PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3),
556 PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \
557 PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \
558 PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \
559 PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5),
560 PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \
561 PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \
562 PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \
563 PINMUX_DATA(FSIAILR_MARK, PORT50_FN5),
564
565 PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \
566 PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \
567 PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \
568 PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5),
569 PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \
570 PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
571 PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \
572 PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \
573 PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \
574 PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \
575 PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6),
576 PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \
577 PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \
578 PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \
579 PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \
580 PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \
581 PINMUX_DATA(FSICOMC_MARK, PORT54_FN7),
582 PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \
583 PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
584 PINMUX_DATA(A0_MARK, PORT57_FN1), \
585 PINMUX_DATA(BS__MARK, PORT57_FN2),
586 PINMUX_DATA(A12_MARK, PORT58_FN1), \
587 PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \
588 PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4),
589 PINMUX_DATA(A13_MARK, PORT59_FN1), \
590 PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \
591 PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
592 PINMUX_DATA(A14_MARK, PORT60_FN1), \
593 PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2),
594 PINMUX_DATA(A15_MARK, PORT61_FN1), \
595 PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2),
596 PINMUX_DATA(A16_MARK, PORT62_FN1), \
597 PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \
598 PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0),
599 PINMUX_DATA(A17_MARK, PORT63_FN1), \
600 PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \
601 PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0),
602 PINMUX_DATA(A18_MARK, PORT64_FN1), \
603 PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \
604 PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0),
605 PINMUX_DATA(A19_MARK, PORT65_FN1), \
606 PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \
607 PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0),
608 PINMUX_DATA(A20_MARK, PORT66_FN1), \
609 PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \
610 PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0),
611 PINMUX_DATA(A21_MARK, PORT67_FN1), \
612 PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \
613 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0),
614 PINMUX_DATA(A22_MARK, PORT68_FN1), \
615 PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \
616 PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0),
617 PINMUX_DATA(A23_MARK, PORT69_FN1), \
618 PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \
619 PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0),
620 PINMUX_DATA(A24_MARK, PORT70_FN1), \
621 PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \
622 PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0),
623 PINMUX_DATA(A25_MARK, PORT71_FN1), \
624 PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \
625 PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0),
626 PINMUX_DATA(A26_MARK, PORT72_FN1), \
627 PINMUX_DATA(KEYIN6_MARK, PORT72_FN2),
628 PINMUX_DATA(KEYIN7_MARK, PORT73_FN2),
629 PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1),
630 PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1),
631 PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1),
632 PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1),
633 PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1),
634 PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1),
635 PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1),
636 PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1),
637 PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1),
638 PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1),
639 PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1),
640 PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1),
641 PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1),
642 PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1),
643 PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1),
644 PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1),
645 PINMUX_DATA(CS4__MARK, PORT90_FN1),
646 PINMUX_DATA(CS5A__MARK, PORT91_FN1), \
647 PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2),
648 PINMUX_DATA(CS5B__MARK, PORT92_FN1), \
649 PINMUX_DATA(FCE1__MARK, PORT92_FN2),
650 PINMUX_DATA(CS6B__MARK, PORT93_FN1), \
651 PINMUX_DATA(DACK0_MARK, PORT93_FN4),
652 PINMUX_DATA(FCE0__MARK, PORT94_FN1), \
653 PINMUX_DATA(CS6A__MARK, PORT94_FN2),
654 PINMUX_DATA(WAIT__MARK, PORT95_FN1), \
655 PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
656 PINMUX_DATA(RD__FSC_MARK, PORT96_FN1),
657 PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \
658 PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2),
659 PINMUX_DATA(WE1__MARK, PORT98_FN1),
660 PINMUX_DATA(FRB_MARK, PORT99_FN1),
661 PINMUX_DATA(CKO_MARK, PORT100_FN1),
662 PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1),
663 PINMUX_DATA(NBRST__MARK, PORT102_FN1),
664 PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3),
665 PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3),
666 PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3),
667 PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3),
668 PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \
669 PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4),
670 PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \
671 PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4),
672 PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \
673 PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \
674 PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4),
675 PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3),
676 PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \
677 PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3),
678 PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \
679 PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3),
680 PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \
681 PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3),
682 PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \
683 PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3),
684 PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \
685 PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \
686 PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \
687 PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1),
688 PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \
689 PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \
690 PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \
691 PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1),
692 PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \
693 PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \
694 PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3),
695 PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1),
696 PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \
697 PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \
698 PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \
699 PINMUX_DATA(LCD2D0_MARK, PORT128_FN7),
700
701 PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \
702 PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \
703 PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \
704 PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \
705 PINMUX_DATA(LCD2D1_MARK, PORT129_FN7),
706 PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \
707 PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0,
708 MSEL4CR_MSEL10_1), \
709 PINMUX_DATA(LCD2D10_MARK, PORT130_FN7),
710 PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \
711 PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \
712 PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \
713 PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \
714 PINMUX_DATA(LCD2D11_MARK, PORT131_FN7),
715 PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \
716 PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \
717 PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \
718 PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \
719 PINMUX_DATA(LCD2D12_MARK, PORT132_FN7),
720 PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \
721 PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \
722 PINMUX_DATA(LCD2D13_MARK, PORT133_FN7),
723 PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \
724 PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \
725 PINMUX_DATA(LCD2D14_MARK, PORT134_FN7),
726 PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \
727 PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \
728 PINMUX_DATA(LCD2D15_MARK, PORT135_FN7),
729 PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \
730 PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \
731 PINMUX_DATA(LCD2D16_MARK, PORT136_FN7),
732 PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \
733 PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \
734 PINMUX_DATA(LCD2D17_MARK, PORT137_FN7),
735 PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \
736 PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \
737 PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \
738 PINMUX_DATA(LCD2D6_MARK, PORT138_FN7),
739 PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \
740 PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \
741 PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \
742 PINMUX_DATA(LCD2D7_MARK, PORT139_FN7),
743 PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \
744 PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \
745 PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \
746 PINMUX_DATA(LCD2D8_MARK, PORT140_FN7),
747 PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \
748 PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \
749 PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \
750 PINMUX_DATA(LCD2D9_MARK, PORT141_FN7),
751 PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \
752 PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \
753 PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \
754 PINMUX_DATA(LCD2D2_MARK, PORT142_FN7),
755 PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \
756 PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \
757 PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \
758 PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \
759 PINMUX_DATA(LCD2D3_MARK, PORT143_FN7),
760 PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \
761 PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \
762 PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \
763 PINMUX_DATA(LCD2D4_MARK, PORT144_FN7),
764 PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \
765 PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \
766 PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \
767 PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \
768 PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \
769 PINMUX_DATA(LCD2D5_MARK, PORT145_FN7),
770 PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \
771 PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \
772 PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \
773 PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \
774 PINMUX_DATA(LCD2D18_MARK, PORT146_FN7),
775 PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \
776 PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \
777 PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \
778 PINMUX_DATA(LCD2D19_MARK, PORT147_FN7),
779 PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
780 PINMUX_DATA(A27_MARK, PORT149_FN1), \
781 PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \
782 PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \
783 PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4),
784 PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3),
785 PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \
786 PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5),
787 PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \
788 PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5),
789 PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \
790 PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \
791 PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5),
792 PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \
793 PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5),
794 PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \
795 PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5),
796 PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \
797 PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5),
798 PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \
799 PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0,
800 MSEL4CR_MSEL10_0),
801 PINMUX_DATA(DINT__MARK, PORT158_FN1), \
802 PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \
803 PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4),
804 PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \
805 PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \
806 PINMUX_DATA(NMI_MARK, PORT159_FN3),
807 PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \
808 PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1),
809 PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \
810 PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1),
811 PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \
812 PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1),
813 PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \
814 PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \
815 PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
816 PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
817 PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \
818 PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0,
819 MSEL4CR_MSEL20_1), \
820 PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5),
821 PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \
822 PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0,
823 MSEL4CR_MSEL20_1), \
824 PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5),
825 PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \
826 PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0,
827 MSEL4CR_MSEL20_1), \
828 PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5),
829 PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \
830 PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0,
831 MSEL4CR_MSEL20_1),
832 PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \
833 PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0,
834 MSEL4CR_MSEL20_1), \
835 PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \
836 PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7),
837 PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
838 PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \
839 PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \
840 PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5),
841 PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \
842 PINMUX_DATA(D16_MARK, PORT200_FN6),
843 PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \
844 PINMUX_DATA(D17_MARK, PORT201_FN6),
845 PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \
846 PINMUX_DATA(D18_MARK, PORT202_FN6),
847 PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \
848 PINMUX_DATA(D19_MARK, PORT203_FN6),
849 PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \
850 PINMUX_DATA(D20_MARK, PORT204_FN6),
851 PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \
852 PINMUX_DATA(D21_MARK, PORT205_FN6),
853 PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \
854 PINMUX_DATA(D22_MARK, PORT206_FN6),
855 PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \
856 PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \
857 PINMUX_DATA(D23_MARK, PORT207_FN6),
858 PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \
859 PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \
860 PINMUX_DATA(D24_MARK, PORT208_FN6),
861 PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \
862 PINMUX_DATA(D25_MARK, PORT209_FN6),
863 PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \
864 PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \
865 PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \
866 PINMUX_DATA(D26_MARK, PORT210_FN6),
867 PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \
868 PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \
869 PINMUX_DATA(D27_MARK, PORT211_FN6),
870 PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \
871 PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \
872 PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \
873 PINMUX_DATA(D28_MARK, PORT212_FN6),
874 PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \
875 PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \
876 PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \
877 PINMUX_DATA(D29_MARK, PORT213_FN6),
878 PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \
879 PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \
880 PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \
881 PINMUX_DATA(D30_MARK, PORT214_FN6),
882 PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \
883 PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \
884 PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \
885 PINMUX_DATA(D31_MARK, PORT215_FN6),
886 PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \
887 PINMUX_DATA(LCDWR__MARK, PORT216_FN2),
888 PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \
889 PINMUX_DATA(DACK2_MARK, PORT217_FN2), \
890 PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \
891 PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \
892 PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1,
893 MSEL4CR_MSEL26_1), \
894 PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7),
895 PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \
896 PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \
897 PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \
898 PINMUX_DATA(DACK3_MARK, PORT218_FN4), \
899 PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
900 PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \
901 PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \
902 PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \
903 PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \
904 PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \
905 PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1,
906 MSEL4CR_MSEL26_1), \
907 PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7),
908 PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \
909 PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
910 PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \
911 PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \
912 PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \
913 PINMUX_DATA(PWEN_MARK, PORT221_FN4), \
914 PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \
915 PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1,
916 MSEL4CR_MSEL26_1), \
917 PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7),
918 PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \
919 PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \
920 PINMUX_DATA(DACK1_MARK, PORT222_FN3), \
921 PINMUX_DATA(OVCN_MARK, PORT222_FN4), \
922 PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \
923 PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1,
924 MSEL4CR_MSEL26_1), \
925 PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1),
926
927 PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \
928 PINMUX_DATA(OVCN2_MARK, PORT225_FN4),
929 PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \
930 PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \
931 PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5),
932 PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \
933 PINMUX_DATA(IDIN_MARK, PORT227_FN4),
934 PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2),
935 PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \
936 PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3),
937 PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \
938 PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1),
939 PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \
940 PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1),
941 PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \
942 PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1),
943 PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \
944 PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1),
945 PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \
946 PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \
947 PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1,
948 MSEL4CR_MSEL26_0), \
949 PINMUX_DATA(LCD2D20_MARK, PORT234_FN7),
950 PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \
951 PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \
952 PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1,
953 MSEL4CR_MSEL26_0), \
954 PINMUX_DATA(LCD2D21_MARK, PORT235_FN7),
955 PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \
956 PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0,
957 MSEL2CR_MSEL16_0),
958 PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \
959 PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0,
960 MSEL2CR_MSEL16_0),
961 PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \
962 PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1,
963 MSEL4CR_MSEL26_0), \
964 PINMUX_DATA(LCD2D22_MARK, PORT238_FN7),
965 PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \
966 PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1,
967 MSEL4CR_MSEL26_0), \
968 PINMUX_DATA(LCD2D23_MARK, PORT239_FN7),
969 PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
970 PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \
971 PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \
972 PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \
973 PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
974 PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \
975 PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3),
976 PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \
977 PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
978 PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0,
979 MSEL4CR_MSEL20_0), \
980 PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \
981 PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \
982 PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1),
983 PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0,
984 MSEL4CR_MSEL20_0), \
985 PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \
986 PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \
987 PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1),
988 PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0,
989 MSEL4CR_MSEL20_0), \
990 PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \
991 PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \
992 PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
993 PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0,
994 MSEL4CR_MSEL20_0), \
995 PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \
996 PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \
997 PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
998 PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0,
999 MSEL4CR_MSEL20_0), \
1000 PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \
1001 PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \
1002 PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \
1003 PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0,
1004 MSEL2CR_MSEL18_0), \
1005 PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1),
1006 PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \
1007 PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \
1008 PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0,
1009 MSEL2CR_MSEL18_0), \
1010 PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1),
1011 PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
1012 PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
1013 PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
1014 PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
1015 PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
1016 PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
1017 PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
1018 PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
1019 PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
1020 PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \
1021 PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
1022 PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \
1023 PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
1024 PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \
1025 PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
1026 PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \
1027 PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
1028 PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
1029 PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1),
1030 PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \
1031 PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3),
1032 PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \
1033 PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3),
1034 PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \
1035 PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3),
1036 PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \
1037 PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
1038 PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
1039 PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
1040 PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0),
1041 PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0),
1042 PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0),
1043 PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0),
1044 PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0),
1045 PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
1046 PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0),
1047 PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
1048 PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0),
1049 PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
1050 PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0),
1051 PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
1052 PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0),
1053 PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
1054 PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
1055 PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
1056 PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \
1057 PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1),
1058 PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1),
1059 PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1),
1060 PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1),
1061 PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1),
1062 PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1),
1063 PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1),
1064 PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1),
1065 PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \
1066 PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1),
1067 PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \
1068 PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1),
1069
1070 PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \
1071 PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1),
1072 PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \
1073 PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1),
1074 PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \
1075 PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1),
1076 PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \
1077 PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1),
1078 PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \
1079 PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1),
1080 PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \
1081 PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1),
1082 PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \
1083 PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1),
1084 PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1),
1085 PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \
1086 PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2),
1087
1088 /* MSEL2 special cases */
1089 PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
1090 MSEL2CR_MSEL12_0),
1091 PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
1092 MSEL2CR_MSEL12_1),
1093 PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
1094 MSEL2CR_MSEL12_0),
1095 PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
1096 MSEL2CR_MSEL12_1),
1097 PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0,
1098 MSEL2CR_MSEL12_0),
1099 PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
1100 MSEL2CR_MSEL9_0),
1101 PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
1102 MSEL2CR_MSEL9_1),
1103 PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
1104 MSEL2CR_MSEL9_0),
1105 PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
1106 MSEL2CR_MSEL9_1),
1107 PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0,
1108 MSEL2CR_MSEL9_0),
1109 PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
1110 MSEL2CR_MSEL6_0),
1111 PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
1112 MSEL2CR_MSEL6_1),
1113 PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
1114 MSEL2CR_MSEL6_0),
1115 PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
1116 MSEL2CR_MSEL6_1),
1117 PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0,
1118 MSEL2CR_MSEL6_0),
1119 PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
1120 MSEL2CR_MSEL3_0),
1121 PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
1122 MSEL2CR_MSEL3_1),
1123 PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
1124 MSEL2CR_MSEL3_0),
1125 PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
1126 MSEL2CR_MSEL3_1),
1127 PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0,
1128 MSEL2CR_MSEL3_0),
1129 PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
1130 MSEL2CR_MSEL0_0),
1131 PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
1132 MSEL2CR_MSEL0_1),
1133 PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
1134 MSEL2CR_MSEL0_0),
1135 PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
1136 MSEL2CR_MSEL0_1),
1137 PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0,
1138 MSEL2CR_MSEL0_0),
1139
1140 /* MSEL3 special cases */
1141 PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1),
1142 PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0),
1143 PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0),
1144 PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1),
1145 PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0),
1146 PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1),
1147
1148 /* MSEL4 special cases */
1149 PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0),
1150 PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1),
1151 PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0),
1152 PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1),
1153 PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0),
1154 PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0),
1155 PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
1156 PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
1157 PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
1158 };
1159
1160 #define SH73A0_PIN(pin, cfgs) \
1161 { \
1162 .name = __stringify(PORT##pin), \
1163 .enum_id = PORT##pin##_DATA, \
1164 .configs = cfgs, \
1165 }
1166
1167 #define __I (SH_PFC_PIN_CFG_INPUT)
1168 #define __O (SH_PFC_PIN_CFG_OUTPUT)
1169 #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1170 #define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
1171 #define __PU (SH_PFC_PIN_CFG_PULL_UP)
1172 #define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1173
1174 #define SH73A0_PIN_I_PD(pin) SH73A0_PIN(pin, __I | __PD)
1175 #define SH73A0_PIN_I_PU(pin) SH73A0_PIN(pin, __I | __PU)
1176 #define SH73A0_PIN_I_PU_PD(pin) SH73A0_PIN(pin, __I | __PUD)
1177 #define SH73A0_PIN_IO(pin) SH73A0_PIN(pin, __IO)
1178 #define SH73A0_PIN_IO_PD(pin) SH73A0_PIN(pin, __IO | __PD)
1179 #define SH73A0_PIN_IO_PU(pin) SH73A0_PIN(pin, __IO | __PU)
1180 #define SH73A0_PIN_IO_PU_PD(pin) SH73A0_PIN(pin, __IO | __PUD)
1181 #define SH73A0_PIN_O(pin) SH73A0_PIN(pin, __O)
1182
1183 static struct sh_pfc_pin pinmux_pins[] = {
1184 /* Table 25-1 (I/O and Pull U/D) */
1185 SH73A0_PIN_I_PD(0),
1186 SH73A0_PIN_I_PU(1),
1187 SH73A0_PIN_I_PU(2),
1188 SH73A0_PIN_I_PU(3),
1189 SH73A0_PIN_I_PU(4),
1190 SH73A0_PIN_I_PU(5),
1191 SH73A0_PIN_I_PU(6),
1192 SH73A0_PIN_I_PU(7),
1193 SH73A0_PIN_I_PU(8),
1194 SH73A0_PIN_I_PD(9),
1195 SH73A0_PIN_I_PD(10),
1196 SH73A0_PIN_I_PU_PD(11),
1197 SH73A0_PIN_IO_PU_PD(12),
1198 SH73A0_PIN_IO_PU_PD(13),
1199 SH73A0_PIN_IO_PU_PD(14),
1200 SH73A0_PIN_IO_PU_PD(15),
1201 SH73A0_PIN_IO_PD(16),
1202 SH73A0_PIN_IO_PD(17),
1203 SH73A0_PIN_IO_PU(18),
1204 SH73A0_PIN_IO_PU(19),
1205 SH73A0_PIN_O(20),
1206 SH73A0_PIN_O(21),
1207 SH73A0_PIN_O(22),
1208 SH73A0_PIN_O(23),
1209 SH73A0_PIN_O(24),
1210 SH73A0_PIN_I_PD(25),
1211 SH73A0_PIN_I_PD(26),
1212 SH73A0_PIN_IO_PU(27),
1213 SH73A0_PIN_IO_PU(28),
1214 SH73A0_PIN_IO_PD(29),
1215 SH73A0_PIN_IO_PD(30),
1216 SH73A0_PIN_IO_PU(31),
1217 SH73A0_PIN_IO_PD(32),
1218 SH73A0_PIN_I_PU_PD(33),
1219 SH73A0_PIN_IO_PD(34),
1220 SH73A0_PIN_I_PU_PD(35),
1221 SH73A0_PIN_IO_PD(36),
1222 SH73A0_PIN_IO(37),
1223 SH73A0_PIN_O(38),
1224 SH73A0_PIN_I_PU(39),
1225 SH73A0_PIN_I_PU_PD(40),
1226 SH73A0_PIN_O(41),
1227 SH73A0_PIN_IO_PD(42),
1228 SH73A0_PIN_IO_PU_PD(43),
1229 SH73A0_PIN_IO_PU_PD(44),
1230 SH73A0_PIN_IO_PD(45),
1231 SH73A0_PIN_IO_PD(46),
1232 SH73A0_PIN_IO_PD(47),
1233 SH73A0_PIN_I_PD(48),
1234 SH73A0_PIN_IO_PU_PD(49),
1235 SH73A0_PIN_IO_PD(50),
1236 SH73A0_PIN_IO_PD(51),
1237 SH73A0_PIN_O(52),
1238 SH73A0_PIN_IO_PU_PD(53),
1239 SH73A0_PIN_IO_PU_PD(54),
1240 SH73A0_PIN_IO_PD(55),
1241 SH73A0_PIN_I_PU_PD(56),
1242 SH73A0_PIN_IO(57),
1243 SH73A0_PIN_IO(58),
1244 SH73A0_PIN_IO(59),
1245 SH73A0_PIN_IO(60),
1246 SH73A0_PIN_IO(61),
1247 SH73A0_PIN_IO_PD(62),
1248 SH73A0_PIN_IO_PD(63),
1249 SH73A0_PIN_IO_PU_PD(64),
1250 SH73A0_PIN_IO_PD(65),
1251 SH73A0_PIN_IO_PU_PD(66),
1252 SH73A0_PIN_IO_PU_PD(67),
1253 SH73A0_PIN_IO_PU_PD(68),
1254 SH73A0_PIN_IO_PU_PD(69),
1255 SH73A0_PIN_IO_PU_PD(70),
1256 SH73A0_PIN_IO_PU_PD(71),
1257 SH73A0_PIN_IO_PU_PD(72),
1258 SH73A0_PIN_I_PU_PD(73),
1259 SH73A0_PIN_IO_PU(74),
1260 SH73A0_PIN_IO_PU(75),
1261 SH73A0_PIN_IO_PU(76),
1262 SH73A0_PIN_IO_PU(77),
1263 SH73A0_PIN_IO_PU(78),
1264 SH73A0_PIN_IO_PU(79),
1265 SH73A0_PIN_IO_PU(80),
1266 SH73A0_PIN_IO_PU(81),
1267 SH73A0_PIN_IO_PU(82),
1268 SH73A0_PIN_IO_PU(83),
1269 SH73A0_PIN_IO_PU(84),
1270 SH73A0_PIN_IO_PU(85),
1271 SH73A0_PIN_IO_PU(86),
1272 SH73A0_PIN_IO_PU(87),
1273 SH73A0_PIN_IO_PU(88),
1274 SH73A0_PIN_IO_PU(89),
1275 SH73A0_PIN_O(90),
1276 SH73A0_PIN_IO_PU(91),
1277 SH73A0_PIN_O(92),
1278 SH73A0_PIN_IO_PU(93),
1279 SH73A0_PIN_O(94),
1280 SH73A0_PIN_I_PU_PD(95),
1281 SH73A0_PIN_IO(96),
1282 SH73A0_PIN_IO(97),
1283 SH73A0_PIN_IO(98),
1284 SH73A0_PIN_I_PU(99),
1285 SH73A0_PIN_O(100),
1286 SH73A0_PIN_O(101),
1287 SH73A0_PIN_I_PU(102),
1288 SH73A0_PIN_IO_PD(103),
1289 SH73A0_PIN_I_PU_PD(104),
1290 SH73A0_PIN_I_PD(105),
1291 SH73A0_PIN_I_PD(106),
1292 SH73A0_PIN_I_PU_PD(107),
1293 SH73A0_PIN_I_PU_PD(108),
1294 SH73A0_PIN_IO_PD(109),
1295 SH73A0_PIN_IO_PD(110),
1296 SH73A0_PIN_IO_PU_PD(111),
1297 SH73A0_PIN_IO_PU_PD(112),
1298 SH73A0_PIN_IO_PU_PD(113),
1299 SH73A0_PIN_IO_PD(114),
1300 SH73A0_PIN_IO_PU(115),
1301 SH73A0_PIN_IO_PU(116),
1302 SH73A0_PIN_IO_PU_PD(117),
1303 SH73A0_PIN_IO_PU_PD(118),
1304 SH73A0_PIN_IO_PD(128),
1305 SH73A0_PIN_IO_PD(129),
1306 SH73A0_PIN_IO_PU_PD(130),
1307 SH73A0_PIN_IO_PD(131),
1308 SH73A0_PIN_IO_PD(132),
1309 SH73A0_PIN_IO_PD(133),
1310 SH73A0_PIN_IO_PU_PD(134),
1311 SH73A0_PIN_IO_PU_PD(135),
1312 SH73A0_PIN_IO_PU_PD(136),
1313 SH73A0_PIN_IO_PU_PD(137),
1314 SH73A0_PIN_IO_PD(138),
1315 SH73A0_PIN_IO_PD(139),
1316 SH73A0_PIN_IO_PD(140),
1317 SH73A0_PIN_IO_PD(141),
1318 SH73A0_PIN_IO_PD(142),
1319 SH73A0_PIN_IO_PD(143),
1320 SH73A0_PIN_IO_PU_PD(144),
1321 SH73A0_PIN_IO_PD(145),
1322 SH73A0_PIN_IO_PU_PD(146),
1323 SH73A0_PIN_IO_PU_PD(147),
1324 SH73A0_PIN_IO_PU_PD(148),
1325 SH73A0_PIN_IO_PU_PD(149),
1326 SH73A0_PIN_I_PU_PD(150),
1327 SH73A0_PIN_IO_PU_PD(151),
1328 SH73A0_PIN_IO_PU_PD(152),
1329 SH73A0_PIN_IO_PD(153),
1330 SH73A0_PIN_IO_PD(154),
1331 SH73A0_PIN_I_PU_PD(155),
1332 SH73A0_PIN_IO_PU_PD(156),
1333 SH73A0_PIN_I_PD(157),
1334 SH73A0_PIN_IO_PD(158),
1335 SH73A0_PIN_IO_PU_PD(159),
1336 SH73A0_PIN_IO_PU_PD(160),
1337 SH73A0_PIN_I_PU_PD(161),
1338 SH73A0_PIN_I_PU_PD(162),
1339 SH73A0_PIN_IO_PU_PD(163),
1340 SH73A0_PIN_I_PU_PD(164),
1341 SH73A0_PIN_IO_PD(192),
1342 SH73A0_PIN_IO_PU_PD(193),
1343 SH73A0_PIN_IO_PD(194),
1344 SH73A0_PIN_IO_PU_PD(195),
1345 SH73A0_PIN_IO_PD(196),
1346 SH73A0_PIN_IO_PD(197),
1347 SH73A0_PIN_IO_PD(198),
1348 SH73A0_PIN_IO_PD(199),
1349 SH73A0_PIN_IO_PU_PD(200),
1350 SH73A0_PIN_IO_PU_PD(201),
1351 SH73A0_PIN_IO_PU_PD(202),
1352 SH73A0_PIN_IO_PU_PD(203),
1353 SH73A0_PIN_IO_PU_PD(204),
1354 SH73A0_PIN_IO_PU_PD(205),
1355 SH73A0_PIN_IO_PU_PD(206),
1356 SH73A0_PIN_IO_PD(207),
1357 SH73A0_PIN_IO_PD(208),
1358 SH73A0_PIN_IO_PD(209),
1359 SH73A0_PIN_IO_PD(210),
1360 SH73A0_PIN_IO_PD(211),
1361 SH73A0_PIN_IO_PD(212),
1362 SH73A0_PIN_IO_PD(213),
1363 SH73A0_PIN_IO_PU_PD(214),
1364 SH73A0_PIN_IO_PU_PD(215),
1365 SH73A0_PIN_IO_PD(216),
1366 SH73A0_PIN_IO_PD(217),
1367 SH73A0_PIN_O(218),
1368 SH73A0_PIN_IO_PD(219),
1369 SH73A0_PIN_IO_PD(220),
1370 SH73A0_PIN_IO_PU_PD(221),
1371 SH73A0_PIN_IO_PU_PD(222),
1372 SH73A0_PIN_I_PU_PD(223),
1373 SH73A0_PIN_I_PU_PD(224),
1374 SH73A0_PIN_IO_PU_PD(225),
1375 SH73A0_PIN_O(226),
1376 SH73A0_PIN_IO_PU_PD(227),
1377 SH73A0_PIN_I_PU_PD(228),
1378 SH73A0_PIN_I_PD(229),
1379 SH73A0_PIN_IO(230),
1380 SH73A0_PIN_IO_PU_PD(231),
1381 SH73A0_PIN_IO_PU_PD(232),
1382 SH73A0_PIN_I_PU_PD(233),
1383 SH73A0_PIN_IO_PU_PD(234),
1384 SH73A0_PIN_IO_PU_PD(235),
1385 SH73A0_PIN_IO_PU_PD(236),
1386 SH73A0_PIN_IO_PD(237),
1387 SH73A0_PIN_IO_PU_PD(238),
1388 SH73A0_PIN_IO_PU_PD(239),
1389 SH73A0_PIN_IO_PU_PD(240),
1390 SH73A0_PIN_O(241),
1391 SH73A0_PIN_I_PD(242),
1392 SH73A0_PIN_IO_PU_PD(243),
1393 SH73A0_PIN_IO_PU_PD(244),
1394 SH73A0_PIN_IO_PU_PD(245),
1395 SH73A0_PIN_IO_PU_PD(246),
1396 SH73A0_PIN_IO_PU_PD(247),
1397 SH73A0_PIN_IO_PU_PD(248),
1398 SH73A0_PIN_IO_PU_PD(249),
1399 SH73A0_PIN_IO_PU_PD(250),
1400 SH73A0_PIN_IO_PU_PD(251),
1401 SH73A0_PIN_IO_PU_PD(252),
1402 SH73A0_PIN_IO_PU_PD(253),
1403 SH73A0_PIN_IO_PU_PD(254),
1404 SH73A0_PIN_IO_PU_PD(255),
1405 SH73A0_PIN_IO_PU_PD(256),
1406 SH73A0_PIN_IO_PU_PD(257),
1407 SH73A0_PIN_IO_PU_PD(258),
1408 SH73A0_PIN_IO_PU_PD(259),
1409 SH73A0_PIN_IO_PU_PD(260),
1410 SH73A0_PIN_IO_PU_PD(261),
1411 SH73A0_PIN_IO_PU_PD(262),
1412 SH73A0_PIN_IO_PU_PD(263),
1413 SH73A0_PIN_IO_PU_PD(264),
1414 SH73A0_PIN_IO_PU_PD(265),
1415 SH73A0_PIN_IO_PU_PD(266),
1416 SH73A0_PIN_IO_PU_PD(267),
1417 SH73A0_PIN_IO_PU_PD(268),
1418 SH73A0_PIN_IO_PU_PD(269),
1419 SH73A0_PIN_IO_PU_PD(270),
1420 SH73A0_PIN_IO_PU_PD(271),
1421 SH73A0_PIN_IO_PU_PD(272),
1422 SH73A0_PIN_IO_PU_PD(273),
1423 SH73A0_PIN_IO_PU_PD(274),
1424 SH73A0_PIN_IO_PU_PD(275),
1425 SH73A0_PIN_IO_PU_PD(276),
1426 SH73A0_PIN_IO_PU_PD(277),
1427 SH73A0_PIN_IO_PU_PD(278),
1428 SH73A0_PIN_IO_PU_PD(279),
1429 SH73A0_PIN_IO_PU_PD(280),
1430 SH73A0_PIN_O(281),
1431 SH73A0_PIN_O(282),
1432 SH73A0_PIN_I_PU(288),
1433 SH73A0_PIN_IO_PU_PD(289),
1434 SH73A0_PIN_IO_PU_PD(290),
1435 SH73A0_PIN_IO_PU_PD(291),
1436 SH73A0_PIN_IO_PU_PD(292),
1437 SH73A0_PIN_IO_PU_PD(293),
1438 SH73A0_PIN_IO_PU_PD(294),
1439 SH73A0_PIN_IO_PU_PD(295),
1440 SH73A0_PIN_IO_PU_PD(296),
1441 SH73A0_PIN_IO_PU_PD(297),
1442 SH73A0_PIN_IO_PU_PD(298),
1443 SH73A0_PIN_IO_PU_PD(299),
1444 SH73A0_PIN_IO_PU_PD(300),
1445 SH73A0_PIN_IO_PU_PD(301),
1446 SH73A0_PIN_IO_PU_PD(302),
1447 SH73A0_PIN_IO_PU_PD(303),
1448 SH73A0_PIN_IO_PU_PD(304),
1449 SH73A0_PIN_IO_PU_PD(305),
1450 SH73A0_PIN_O(306),
1451 SH73A0_PIN_O(307),
1452 SH73A0_PIN_I_PU(308),
1453 SH73A0_PIN_O(309),
1454 };
1455
1456 static const struct pinmux_range pinmux_ranges[] = {
1457 {.begin = 0, .end = 118,},
1458 {.begin = 128, .end = 164,},
1459 {.begin = 192, .end = 282,},
1460 {.begin = 288, .end = 309,},
1461 };
1462
1463 /* Pin numbers for pins without a corresponding GPIO port number are computed
1464 * from the row and column numbers with a 1000 offset to avoid collisions with
1465 * GPIO port numbers.
1466 */
1467 #define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1)
1468
1469 /* - BSC -------------------------------------------------------------------- */
1470 static const unsigned int bsc_data_0_7_pins[] = {
1471 /* D[0:7] */
1472 74, 75, 76, 77, 78, 79, 80, 81,
1473 };
1474 static const unsigned int bsc_data_0_7_mux[] = {
1475 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1476 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1477 };
1478 static const unsigned int bsc_data_8_15_pins[] = {
1479 /* D[8:15] */
1480 82, 83, 84, 85, 86, 87, 88, 89,
1481 };
1482 static const unsigned int bsc_data_8_15_mux[] = {
1483 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1484 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1485 };
1486 static const unsigned int bsc_cs4_pins[] = {
1487 /* CS */
1488 90,
1489 };
1490 static const unsigned int bsc_cs4_mux[] = {
1491 CS4__MARK,
1492 };
1493 static const unsigned int bsc_cs5_a_pins[] = {
1494 /* CS */
1495 91,
1496 };
1497 static const unsigned int bsc_cs5_a_mux[] = {
1498 CS5A__MARK,
1499 };
1500 static const unsigned int bsc_cs5_b_pins[] = {
1501 /* CS */
1502 92,
1503 };
1504 static const unsigned int bsc_cs5_b_mux[] = {
1505 CS5B__MARK,
1506 };
1507 static const unsigned int bsc_cs6_a_pins[] = {
1508 /* CS */
1509 94,
1510 };
1511 static const unsigned int bsc_cs6_a_mux[] = {
1512 CS6A__MARK,
1513 };
1514 static const unsigned int bsc_cs6_b_pins[] = {
1515 /* CS */
1516 93,
1517 };
1518 static const unsigned int bsc_cs6_b_mux[] = {
1519 CS6B__MARK,
1520 };
1521 static const unsigned int bsc_rd_pins[] = {
1522 /* RD */
1523 96,
1524 };
1525 static const unsigned int bsc_rd_mux[] = {
1526 RD__FSC_MARK,
1527 };
1528 static const unsigned int bsc_rdwr_0_pins[] = {
1529 /* RDWR */
1530 91,
1531 };
1532 static const unsigned int bsc_rdwr_0_mux[] = {
1533 PORT91_RDWR_MARK,
1534 };
1535 static const unsigned int bsc_rdwr_1_pins[] = {
1536 /* RDWR */
1537 97,
1538 };
1539 static const unsigned int bsc_rdwr_1_mux[] = {
1540 RDWR_FWE_MARK,
1541 };
1542 static const unsigned int bsc_rdwr_2_pins[] = {
1543 /* RDWR */
1544 149,
1545 };
1546 static const unsigned int bsc_rdwr_2_mux[] = {
1547 PORT149_RDWR_MARK,
1548 };
1549 static const unsigned int bsc_we0_pins[] = {
1550 /* WE0 */
1551 97,
1552 };
1553 static const unsigned int bsc_we0_mux[] = {
1554 WE0__FWE_MARK,
1555 };
1556 static const unsigned int bsc_we1_pins[] = {
1557 /* WE1 */
1558 98,
1559 };
1560 static const unsigned int bsc_we1_mux[] = {
1561 WE1__MARK,
1562 };
1563 /* - FSIA ------------------------------------------------------------------- */
1564 static const unsigned int fsia_mclk_in_pins[] = {
1565 /* CK */
1566 49,
1567 };
1568 static const unsigned int fsia_mclk_in_mux[] = {
1569 FSIACK_MARK,
1570 };
1571 static const unsigned int fsia_mclk_out_pins[] = {
1572 /* OMC */
1573 49,
1574 };
1575 static const unsigned int fsia_mclk_out_mux[] = {
1576 FSIAOMC_MARK,
1577 };
1578 static const unsigned int fsia_sclk_in_pins[] = {
1579 /* ILR, IBT */
1580 50, 51,
1581 };
1582 static const unsigned int fsia_sclk_in_mux[] = {
1583 FSIAILR_MARK, FSIAIBT_MARK,
1584 };
1585 static const unsigned int fsia_sclk_out_pins[] = {
1586 /* OLR, OBT */
1587 50, 51,
1588 };
1589 static const unsigned int fsia_sclk_out_mux[] = {
1590 FSIAOLR_MARK, FSIAOBT_MARK,
1591 };
1592 static const unsigned int fsia_data_in_pins[] = {
1593 /* ISLD */
1594 55,
1595 };
1596 static const unsigned int fsia_data_in_mux[] = {
1597 FSIAISLD_MARK,
1598 };
1599 static const unsigned int fsia_data_out_pins[] = {
1600 /* OSLD */
1601 52,
1602 };
1603 static const unsigned int fsia_data_out_mux[] = {
1604 FSIAOSLD_MARK,
1605 };
1606 static const unsigned int fsia_spdif_pins[] = {
1607 /* SPDIF */
1608 53,
1609 };
1610 static const unsigned int fsia_spdif_mux[] = {
1611 FSIASPDIF_MARK,
1612 };
1613 /* - FSIB ------------------------------------------------------------------- */
1614 static const unsigned int fsib_mclk_in_pins[] = {
1615 /* CK */
1616 54,
1617 };
1618 static const unsigned int fsib_mclk_in_mux[] = {
1619 FSIBCK_MARK,
1620 };
1621 static const unsigned int fsib_mclk_out_pins[] = {
1622 /* OMC */
1623 54,
1624 };
1625 static const unsigned int fsib_mclk_out_mux[] = {
1626 FSIBOMC_MARK,
1627 };
1628 static const unsigned int fsib_sclk_in_pins[] = {
1629 /* ILR, IBT */
1630 37, 36,
1631 };
1632 static const unsigned int fsib_sclk_in_mux[] = {
1633 FSIBILR_MARK, FSIBIBT_MARK,
1634 };
1635 static const unsigned int fsib_sclk_out_pins[] = {
1636 /* OLR, OBT */
1637 37, 36,
1638 };
1639 static const unsigned int fsib_sclk_out_mux[] = {
1640 FSIBOLR_MARK, FSIBOBT_MARK,
1641 };
1642 static const unsigned int fsib_data_in_pins[] = {
1643 /* ISLD */
1644 39,
1645 };
1646 static const unsigned int fsib_data_in_mux[] = {
1647 FSIBISLD_MARK,
1648 };
1649 static const unsigned int fsib_data_out_pins[] = {
1650 /* OSLD */
1651 38,
1652 };
1653 static const unsigned int fsib_data_out_mux[] = {
1654 FSIBOSLD_MARK,
1655 };
1656 static const unsigned int fsib_spdif_pins[] = {
1657 /* SPDIF */
1658 53,
1659 };
1660 static const unsigned int fsib_spdif_mux[] = {
1661 FSIBSPDIF_MARK,
1662 };
1663 /* - FSIC ------------------------------------------------------------------- */
1664 static const unsigned int fsic_mclk_in_pins[] = {
1665 /* CK */
1666 54,
1667 };
1668 static const unsigned int fsic_mclk_in_mux[] = {
1669 FSICCK_MARK,
1670 };
1671 static const unsigned int fsic_mclk_out_pins[] = {
1672 /* OMC */
1673 54,
1674 };
1675 static const unsigned int fsic_mclk_out_mux[] = {
1676 FSICOMC_MARK,
1677 };
1678 static const unsigned int fsic_sclk_in_pins[] = {
1679 /* ILR, IBT */
1680 46, 45,
1681 };
1682 static const unsigned int fsic_sclk_in_mux[] = {
1683 FSICILR_MARK, FSICIBT_MARK,
1684 };
1685 static const unsigned int fsic_sclk_out_pins[] = {
1686 /* OLR, OBT */
1687 46, 45,
1688 };
1689 static const unsigned int fsic_sclk_out_mux[] = {
1690 FSICOLR_MARK, FSICOBT_MARK,
1691 };
1692 static const unsigned int fsic_data_in_pins[] = {
1693 /* ISLD */
1694 48,
1695 };
1696 static const unsigned int fsic_data_in_mux[] = {
1697 FSICISLD_MARK,
1698 };
1699 static const unsigned int fsic_data_out_pins[] = {
1700 /* OSLD, OSLDT1, OSLDT2, OSLDT3 */
1701 47, 44, 42, 16,
1702 };
1703 static const unsigned int fsic_data_out_mux[] = {
1704 FSICOSLD_MARK, FSICOSLDT1_MARK, FSICOSLDT2_MARK, FSICOSLDT3_MARK,
1705 };
1706 static const unsigned int fsic_spdif_0_pins[] = {
1707 /* SPDIF */
1708 53,
1709 };
1710 static const unsigned int fsic_spdif_0_mux[] = {
1711 PORT53_FSICSPDIF_MARK,
1712 };
1713 static const unsigned int fsic_spdif_1_pins[] = {
1714 /* SPDIF */
1715 47,
1716 };
1717 static const unsigned int fsic_spdif_1_mux[] = {
1718 PORT47_FSICSPDIF_MARK,
1719 };
1720 /* - FSID ------------------------------------------------------------------- */
1721 static const unsigned int fsid_sclk_in_pins[] = {
1722 /* ILR, IBT */
1723 46, 45,
1724 };
1725 static const unsigned int fsid_sclk_in_mux[] = {
1726 FSIDILR_MARK, FSIDIBT_MARK,
1727 };
1728 static const unsigned int fsid_sclk_out_pins[] = {
1729 /* OLR, OBT */
1730 46, 45,
1731 };
1732 static const unsigned int fsid_sclk_out_mux[] = {
1733 FSIDOLR_MARK, FSIDOBT_MARK,
1734 };
1735 static const unsigned int fsid_data_in_pins[] = {
1736 /* ISLD */
1737 48,
1738 };
1739 static const unsigned int fsid_data_in_mux[] = {
1740 FSIDISLD_MARK,
1741 };
1742 /* - I2C2 ------------------------------------------------------------------- */
1743 static const unsigned int i2c2_0_pins[] = {
1744 /* SCL, SDA */
1745 237, 236,
1746 };
1747 static const unsigned int i2c2_0_mux[] = {
1748 PORT237_I2C_SCL2_MARK, PORT236_I2C_SDA2_MARK,
1749 };
1750 static const unsigned int i2c2_1_pins[] = {
1751 /* SCL, SDA */
1752 27, 28,
1753 };
1754 static const unsigned int i2c2_1_mux[] = {
1755 PORT27_I2C_SCL2_MARK, PORT28_I2C_SDA2_MARK,
1756 };
1757 static const unsigned int i2c2_2_pins[] = {
1758 /* SCL, SDA */
1759 115, 116,
1760 };
1761 static const unsigned int i2c2_2_mux[] = {
1762 PORT115_I2C_SCL2_MARK, PORT116_I2C_SDA2_MARK,
1763 };
1764 /* - I2C3 ------------------------------------------------------------------- */
1765 static const unsigned int i2c3_0_pins[] = {
1766 /* SCL, SDA */
1767 248, 249,
1768 };
1769 static const unsigned int i2c3_0_mux[] = {
1770 PORT248_I2C_SCL3_MARK, PORT249_I2C_SDA3_MARK,
1771 };
1772 static const unsigned int i2c3_1_pins[] = {
1773 /* SCL, SDA */
1774 27, 28,
1775 };
1776 static const unsigned int i2c3_1_mux[] = {
1777 PORT27_I2C_SCL3_MARK, PORT28_I2C_SDA3_MARK,
1778 };
1779 static const unsigned int i2c3_2_pins[] = {
1780 /* SCL, SDA */
1781 115, 116,
1782 };
1783 static const unsigned int i2c3_2_mux[] = {
1784 PORT115_I2C_SCL3_MARK, PORT116_I2C_SDA3_MARK,
1785 };
1786 /* - IrDA ------------------------------------------------------------------- */
1787 static const unsigned int irda_0_pins[] = {
1788 /* OUT, IN, FIRSEL */
1789 241, 242, 243,
1790 };
1791 static const unsigned int irda_0_mux[] = {
1792 PORT241_IRDA_OUT_MARK, PORT242_IRDA_IN_MARK, PORT243_IRDA_FIRSEL_MARK,
1793 };
1794 static const unsigned int irda_1_pins[] = {
1795 /* OUT, IN, FIRSEL */
1796 49, 53, 54,
1797 };
1798 static const unsigned int irda_1_mux[] = {
1799 PORT49_IRDA_OUT_MARK, PORT53_IRDA_IN_MARK, PORT54_IRDA_FIRSEL_MARK,
1800 };
1801 /* - KEYSC ------------------------------------------------------------------ */
1802 static const unsigned int keysc_in5_pins[] = {
1803 /* KEYIN[0:4] */
1804 66, 67, 68, 69, 70,
1805 };
1806 static const unsigned int keysc_in5_mux[] = {
1807 KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1808 KEYIN4_MARK,
1809 };
1810 static const unsigned int keysc_in6_pins[] = {
1811 /* KEYIN[0:5] */
1812 66, 67, 68, 69, 70, 71,
1813 };
1814 static const unsigned int keysc_in6_mux[] = {
1815 KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1816 KEYIN4_MARK, KEYIN5_MARK,
1817 };
1818 static const unsigned int keysc_in7_pins[] = {
1819 /* KEYIN[0:6] */
1820 66, 67, 68, 69, 70, 71, 72,
1821 };
1822 static const unsigned int keysc_in7_mux[] = {
1823 KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1824 KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK,
1825 };
1826 static const unsigned int keysc_in8_pins[] = {
1827 /* KEYIN[0:7] */
1828 66, 67, 68, 69, 70, 71, 72, 73,
1829 };
1830 static const unsigned int keysc_in8_mux[] = {
1831 KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1832 KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
1833 };
1834 static const unsigned int keysc_out04_pins[] = {
1835 /* KEYOUT[0:4] */
1836 65, 64, 63, 62, 61,
1837 };
1838 static const unsigned int keysc_out04_mux[] = {
1839 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, KEYOUT4_MARK,
1840 };
1841 static const unsigned int keysc_out5_pins[] = {
1842 /* KEYOUT5 */
1843 60,
1844 };
1845 static const unsigned int keysc_out5_mux[] = {
1846 KEYOUT5_MARK,
1847 };
1848 static const unsigned int keysc_out6_0_pins[] = {
1849 /* KEYOUT6 */
1850 59,
1851 };
1852 static const unsigned int keysc_out6_0_mux[] = {
1853 PORT59_KEYOUT6_MARK,
1854 };
1855 static const unsigned int keysc_out6_1_pins[] = {
1856 /* KEYOUT6 */
1857 131,
1858 };
1859 static const unsigned int keysc_out6_1_mux[] = {
1860 PORT131_KEYOUT6_MARK,
1861 };
1862 static const unsigned int keysc_out6_2_pins[] = {
1863 /* KEYOUT6 */
1864 143,
1865 };
1866 static const unsigned int keysc_out6_2_mux[] = {
1867 PORT143_KEYOUT6_MARK,
1868 };
1869 static const unsigned int keysc_out7_0_pins[] = {
1870 /* KEYOUT7 */
1871 58,
1872 };
1873 static const unsigned int keysc_out7_0_mux[] = {
1874 PORT58_KEYOUT7_MARK,
1875 };
1876 static const unsigned int keysc_out7_1_pins[] = {
1877 /* KEYOUT7 */
1878 132,
1879 };
1880 static const unsigned int keysc_out7_1_mux[] = {
1881 PORT132_KEYOUT7_MARK,
1882 };
1883 static const unsigned int keysc_out7_2_pins[] = {
1884 /* KEYOUT7 */
1885 144,
1886 };
1887 static const unsigned int keysc_out7_2_mux[] = {
1888 PORT144_KEYOUT7_MARK,
1889 };
1890 static const unsigned int keysc_out8_0_pins[] = {
1891 /* KEYOUT8 */
1892 PIN_NUMBER(6, 26),
1893 };
1894 static const unsigned int keysc_out8_0_mux[] = {
1895 KEYOUT8_MARK,
1896 };
1897 static const unsigned int keysc_out8_1_pins[] = {
1898 /* KEYOUT8 */
1899 136,
1900 };
1901 static const unsigned int keysc_out8_1_mux[] = {
1902 PORT136_KEYOUT8_MARK,
1903 };
1904 static const unsigned int keysc_out8_2_pins[] = {
1905 /* KEYOUT8 */
1906 138,
1907 };
1908 static const unsigned int keysc_out8_2_mux[] = {
1909 PORT138_KEYOUT8_MARK,
1910 };
1911 static const unsigned int keysc_out9_0_pins[] = {
1912 /* KEYOUT9 */
1913 137,
1914 };
1915 static const unsigned int keysc_out9_0_mux[] = {
1916 PORT137_KEYOUT9_MARK,
1917 };
1918 static const unsigned int keysc_out9_1_pins[] = {
1919 /* KEYOUT9 */
1920 139,
1921 };
1922 static const unsigned int keysc_out9_1_mux[] = {
1923 PORT139_KEYOUT9_MARK,
1924 };
1925 static const unsigned int keysc_out9_2_pins[] = {
1926 /* KEYOUT9 */
1927 149,
1928 };
1929 static const unsigned int keysc_out9_2_mux[] = {
1930 PORT149_KEYOUT9_MARK,
1931 };
1932 static const unsigned int keysc_out10_0_pins[] = {
1933 /* KEYOUT10 */
1934 132,
1935 };
1936 static const unsigned int keysc_out10_0_mux[] = {
1937 PORT132_KEYOUT10_MARK,
1938 };
1939 static const unsigned int keysc_out10_1_pins[] = {
1940 /* KEYOUT10 */
1941 142,
1942 };
1943 static const unsigned int keysc_out10_1_mux[] = {
1944 PORT142_KEYOUT10_MARK,
1945 };
1946 static const unsigned int keysc_out11_0_pins[] = {
1947 /* KEYOUT11 */
1948 131,
1949 };
1950 static const unsigned int keysc_out11_0_mux[] = {
1951 PORT131_KEYOUT11_MARK,
1952 };
1953 static const unsigned int keysc_out11_1_pins[] = {
1954 /* KEYOUT11 */
1955 143,
1956 };
1957 static const unsigned int keysc_out11_1_mux[] = {
1958 PORT143_KEYOUT11_MARK,
1959 };
1960 /* - LCD -------------------------------------------------------------------- */
1961 static const unsigned int lcd_data8_pins[] = {
1962 /* D[0:7] */
1963 192, 193, 194, 195, 196, 197, 198, 199,
1964 };
1965 static const unsigned int lcd_data8_mux[] = {
1966 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1967 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1968 };
1969 static const unsigned int lcd_data9_pins[] = {
1970 /* D[0:8] */
1971 192, 193, 194, 195, 196, 197, 198, 199,
1972 200,
1973 };
1974 static const unsigned int lcd_data9_mux[] = {
1975 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1976 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1977 LCDD8_MARK,
1978 };
1979 static const unsigned int lcd_data12_pins[] = {
1980 /* D[0:11] */
1981 192, 193, 194, 195, 196, 197, 198, 199,
1982 200, 201, 202, 203,
1983 };
1984 static const unsigned int lcd_data12_mux[] = {
1985 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1986 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1987 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1988 };
1989 static const unsigned int lcd_data16_pins[] = {
1990 /* D[0:15] */
1991 192, 193, 194, 195, 196, 197, 198, 199,
1992 200, 201, 202, 203, 204, 205, 206, 207,
1993 };
1994 static const unsigned int lcd_data16_mux[] = {
1995 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1996 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1997 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1998 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1999 };
2000 static const unsigned int lcd_data18_pins[] = {
2001 /* D[0:17] */
2002 192, 193, 194, 195, 196, 197, 198, 199,
2003 200, 201, 202, 203, 204, 205, 206, 207,
2004 208, 209,
2005 };
2006 static const unsigned int lcd_data18_mux[] = {
2007 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
2008 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
2009 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
2010 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
2011 LCDD16_MARK, LCDD17_MARK,
2012 };
2013 static const unsigned int lcd_data24_pins[] = {
2014 /* D[0:23] */
2015 192, 193, 194, 195, 196, 197, 198, 199,
2016 200, 201, 202, 203, 204, 205, 206, 207,
2017 208, 209, 210, 211, 212, 213, 214, 215
2018 };
2019 static const unsigned int lcd_data24_mux[] = {
2020 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
2021 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
2022 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
2023 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
2024 LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
2025 LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
2026 };
2027 static const unsigned int lcd_display_pins[] = {
2028 /* DON */
2029 222,
2030 };
2031 static const unsigned int lcd_display_mux[] = {
2032 LCDDON_MARK,
2033 };
2034 static const unsigned int lcd_lclk_pins[] = {
2035 /* LCLK */
2036 221,
2037 };
2038 static const unsigned int lcd_lclk_mux[] = {
2039 LCDLCLK_MARK,
2040 };
2041 static const unsigned int lcd_sync_pins[] = {
2042 /* VSYN, HSYN, DCK, DISP */
2043 220, 218, 216, 219,
2044 };
2045 static const unsigned int lcd_sync_mux[] = {
2046 LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
2047 };
2048 static const unsigned int lcd_sys_pins[] = {
2049 /* CS, WR, RD, RS */
2050 218, 216, 217, 219,
2051 };
2052 static const unsigned int lcd_sys_mux[] = {
2053 LCDCS__MARK, LCDWR__MARK, LCDRD__MARK, LCDRS_MARK,
2054 };
2055 /* - LCD2 ------------------------------------------------------------------- */
2056 static const unsigned int lcd2_data8_pins[] = {
2057 /* D[0:7] */
2058 128, 129, 142, 143, 144, 145, 138, 139,
2059 };
2060 static const unsigned int lcd2_data8_mux[] = {
2061 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2062 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2063 };
2064 static const unsigned int lcd2_data9_pins[] = {
2065 /* D[0:8] */
2066 128, 129, 142, 143, 144, 145, 138, 139,
2067 140,
2068 };
2069 static const unsigned int lcd2_data9_mux[] = {
2070 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2071 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2072 LCD2D8_MARK,
2073 };
2074 static const unsigned int lcd2_data12_pins[] = {
2075 /* D[0:12] */
2076 128, 129, 142, 143, 144, 145, 138, 139,
2077 140, 141, 130, 131,
2078 };
2079 static const unsigned int lcd2_data12_mux[] = {
2080 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2081 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2082 LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2083 };
2084 static const unsigned int lcd2_data16_pins[] = {
2085 /* D[0:15] */
2086 128, 129, 142, 143, 144, 145, 138, 139,
2087 140, 141, 130, 131, 132, 133, 134, 135,
2088 };
2089 static const unsigned int lcd2_data16_mux[] = {
2090 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2091 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2092 LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2093 LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2094 };
2095 static const unsigned int lcd2_data18_pins[] = {
2096 /* D[0:17] */
2097 128, 129, 142, 143, 144, 145, 138, 139,
2098 140, 141, 130, 131, 132, 133, 134, 135,
2099 136, 137,
2100 };
2101 static const unsigned int lcd2_data18_mux[] = {
2102 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2103 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2104 LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2105 LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2106 LCD2D16_MARK, LCD2D17_MARK,
2107 };
2108 static const unsigned int lcd2_data24_pins[] = {
2109 /* D[0:23] */
2110 128, 129, 142, 143, 144, 145, 138, 139,
2111 140, 141, 130, 131, 132, 133, 134, 135,
2112 136, 137, 146, 147, 234, 235, 238, 239
2113 };
2114 static const unsigned int lcd2_data24_mux[] = {
2115 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2116 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2117 LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2118 LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2119 LCD2D16_MARK, LCD2D17_MARK, LCD2D18_MARK, LCD2D19_MARK,
2120 LCD2D20_MARK, LCD2D21_MARK, LCD2D22_MARK, LCD2D23_MARK,
2121 };
2122 static const unsigned int lcd2_sync_0_pins[] = {
2123 /* VSYN, HSYN, DCK, DISP */
2124 128, 129, 146, 145,
2125 };
2126 static const unsigned int lcd2_sync_0_mux[] = {
2127 PORT128_LCD2VSYN_MARK, PORT129_LCD2HSYN_MARK,
2128 LCD2DCK_MARK, PORT145_LCD2DISP_MARK,
2129 };
2130 static const unsigned int lcd2_sync_1_pins[] = {
2131 /* VSYN, HSYN, DCK, DISP */
2132 222, 221, 219, 217,
2133 };
2134 static const unsigned int lcd2_sync_1_mux[] = {
2135 PORT222_LCD2VSYN_MARK, PORT221_LCD2HSYN_MARK,
2136 LCD2DCK_2_MARK, PORT217_LCD2DISP_MARK,
2137 };
2138 static const unsigned int lcd2_sys_0_pins[] = {
2139 /* CS, WR, RD, RS */
2140 129, 146, 147, 145,
2141 };
2142 static const unsigned int lcd2_sys_0_mux[] = {
2143 PORT129_LCD2CS__MARK, PORT146_LCD2WR__MARK,
2144 LCD2RD__MARK, PORT145_LCD2RS_MARK,
2145 };
2146 static const unsigned int lcd2_sys_1_pins[] = {
2147 /* CS, WR, RD, RS */
2148 221, 219, 147, 217,
2149 };
2150 static const unsigned int lcd2_sys_1_mux[] = {
2151 PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK,
2152 LCD2RD__MARK, PORT217_LCD2RS_MARK,
2153 };
2154 /* - MMCIF ------------------------------------------------------------------ */
2155 static const unsigned int mmc0_data1_0_pins[] = {
2156 /* D[0] */
2157 271,
2158 };
2159 static const unsigned int mmc0_data1_0_mux[] = {
2160 MMCD0_0_MARK,
2161 };
2162 static const unsigned int mmc0_data4_0_pins[] = {
2163 /* D[0:3] */
2164 271, 272, 273, 274,
2165 };
2166 static const unsigned int mmc0_data4_0_mux[] = {
2167 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
2168 };
2169 static const unsigned int mmc0_data8_0_pins[] = {
2170 /* D[0:7] */
2171 271, 272, 273, 274, 275, 276, 277, 278,
2172 };
2173 static const unsigned int mmc0_data8_0_mux[] = {
2174 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
2175 MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
2176 };
2177 static const unsigned int mmc0_ctrl_0_pins[] = {
2178 /* CMD, CLK */
2179 279, 270,
2180 };
2181 static const unsigned int mmc0_ctrl_0_mux[] = {
2182 MMCCMD0_MARK, MMCCLK0_MARK,
2183 };
2184
2185 static const unsigned int mmc0_data1_1_pins[] = {
2186 /* D[0] */
2187 305,
2188 };
2189 static const unsigned int mmc0_data1_1_mux[] = {
2190 MMCD1_0_MARK,
2191 };
2192 static const unsigned int mmc0_data4_1_pins[] = {
2193 /* D[0:3] */
2194 305, 304, 303, 302,
2195 };
2196 static const unsigned int mmc0_data4_1_mux[] = {
2197 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
2198 };
2199 static const unsigned int mmc0_data8_1_pins[] = {
2200 /* D[0:7] */
2201 305, 304, 303, 302, 301, 300, 299, 298,
2202 };
2203 static const unsigned int mmc0_data8_1_mux[] = {
2204 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
2205 MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
2206 };
2207 static const unsigned int mmc0_ctrl_1_pins[] = {
2208 /* CMD, CLK */
2209 297, 289,
2210 };
2211 static const unsigned int mmc0_ctrl_1_mux[] = {
2212 MMCCMD1_MARK, MMCCLK1_MARK,
2213 };
2214 /* - SCIFA0 ----------------------------------------------------------------- */
2215 static const unsigned int scifa0_data_pins[] = {
2216 /* RXD, TXD */
2217 43, 17,
2218 };
2219 static const unsigned int scifa0_data_mux[] = {
2220 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2221 };
2222 static const unsigned int scifa0_clk_pins[] = {
2223 /* SCK */
2224 16,
2225 };
2226 static const unsigned int scifa0_clk_mux[] = {
2227 SCIFA0_SCK_MARK,
2228 };
2229 static const unsigned int scifa0_ctrl_pins[] = {
2230 /* RTS, CTS */
2231 42, 44,
2232 };
2233 static const unsigned int scifa0_ctrl_mux[] = {
2234 SCIFA0_RTS__MARK, SCIFA0_CTS__MARK,
2235 };
2236 /* - SCIFA1 ----------------------------------------------------------------- */
2237 static const unsigned int scifa1_data_pins[] = {
2238 /* RXD, TXD */
2239 228, 225,
2240 };
2241 static const unsigned int scifa1_data_mux[] = {
2242 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2243 };
2244 static const unsigned int scifa1_clk_pins[] = {
2245 /* SCK */
2246 226,
2247 };
2248 static const unsigned int scifa1_clk_mux[] = {
2249 SCIFA1_SCK_MARK,
2250 };
2251 static const unsigned int scifa1_ctrl_pins[] = {
2252 /* RTS, CTS */
2253 227, 229,
2254 };
2255 static const unsigned int scifa1_ctrl_mux[] = {
2256 SCIFA1_RTS__MARK, SCIFA1_CTS__MARK,
2257 };
2258 /* - SCIFA2 ----------------------------------------------------------------- */
2259 static const unsigned int scifa2_data_0_pins[] = {
2260 /* RXD, TXD */
2261 155, 154,
2262 };
2263 static const unsigned int scifa2_data_0_mux[] = {
2264 SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
2265 };
2266 static const unsigned int scifa2_clk_0_pins[] = {
2267 /* SCK */
2268 158,
2269 };
2270 static const unsigned int scifa2_clk_0_mux[] = {
2271 SCIFA2_SCK1_MARK,
2272 };
2273 static const unsigned int scifa2_ctrl_0_pins[] = {
2274 /* RTS, CTS */
2275 156, 157,
2276 };
2277 static const unsigned int scifa2_ctrl_0_mux[] = {
2278 SCIFA2_RTS1__MARK, SCIFA2_CTS1__MARK,
2279 };
2280 static const unsigned int scifa2_data_1_pins[] = {
2281 /* RXD, TXD */
2282 233, 230,
2283 };
2284 static const unsigned int scifa2_data_1_mux[] = {
2285 SCIFA2_RXD2_MARK, SCIFA2_TXD2_MARK,
2286 };
2287 static const unsigned int scifa2_clk_1_pins[] = {
2288 /* SCK */
2289 232,
2290 };
2291 static const unsigned int scifa2_clk_1_mux[] = {
2292 SCIFA2_SCK2_MARK,
2293 };
2294 static const unsigned int scifa2_ctrl_1_pins[] = {
2295 /* RTS, CTS */
2296 234, 231,
2297 };
2298 static const unsigned int scifa2_ctrl_1_mux[] = {
2299 SCIFA2_RTS2__MARK, SCIFA2_CTS2__MARK,
2300 };
2301 /* - SCIFA3 ----------------------------------------------------------------- */
2302 static const unsigned int scifa3_data_pins[] = {
2303 /* RXD, TXD */
2304 108, 110,
2305 };
2306 static const unsigned int scifa3_data_mux[] = {
2307 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
2308 };
2309 static const unsigned int scifa3_ctrl_pins[] = {
2310 /* RTS, CTS */
2311 109, 107,
2312 };
2313 static const unsigned int scifa3_ctrl_mux[] = {
2314 SCIFA3_RTS__MARK, SCIFA3_CTS__MARK,
2315 };
2316 /* - SCIFA4 ----------------------------------------------------------------- */
2317 static const unsigned int scifa4_data_pins[] = {
2318 /* RXD, TXD */
2319 33, 32,
2320 };
2321 static const unsigned int scifa4_data_mux[] = {
2322 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
2323 };
2324 static const unsigned int scifa4_ctrl_pins[] = {
2325 /* RTS, CTS */
2326 34, 35,
2327 };
2328 static const unsigned int scifa4_ctrl_mux[] = {
2329 SCIFA4_RTS__MARK, SCIFA4_CTS__MARK,
2330 };
2331 /* - SCIFA5 ----------------------------------------------------------------- */
2332 static const unsigned int scifa5_data_0_pins[] = {
2333 /* RXD, TXD */
2334 246, 247,
2335 };
2336 static const unsigned int scifa5_data_0_mux[] = {
2337 PORT246_SCIFA5_RXD_MARK, PORT247_SCIFA5_TXD_MARK,
2338 };
2339 static const unsigned int scifa5_clk_0_pins[] = {
2340 /* SCK */
2341 248,
2342 };
2343 static const unsigned int scifa5_clk_0_mux[] = {
2344 PORT248_SCIFA5_SCK_MARK,
2345 };
2346 static const unsigned int scifa5_ctrl_0_pins[] = {
2347 /* RTS, CTS */
2348 245, 244,
2349 };
2350 static const unsigned int scifa5_ctrl_0_mux[] = {
2351 PORT245_SCIFA5_RTS__MARK, PORT244_SCIFA5_CTS__MARK,
2352 };
2353 static const unsigned int scifa5_data_1_pins[] = {
2354 /* RXD, TXD */
2355 195, 196,
2356 };
2357 static const unsigned int scifa5_data_1_mux[] = {
2358 PORT195_SCIFA5_RXD_MARK, PORT196_SCIFA5_TXD_MARK,
2359 };
2360 static const unsigned int scifa5_clk_1_pins[] = {
2361 /* SCK */
2362 197,
2363 };
2364 static const unsigned int scifa5_clk_1_mux[] = {
2365 PORT197_SCIFA5_SCK_MARK,
2366 };
2367 static const unsigned int scifa5_ctrl_1_pins[] = {
2368 /* RTS, CTS */
2369 194, 193,
2370 };
2371 static const unsigned int scifa5_ctrl_1_mux[] = {
2372 PORT194_SCIFA5_RTS__MARK, PORT193_SCIFA5_CTS__MARK,
2373 };
2374 static const unsigned int scifa5_data_2_pins[] = {
2375 /* RXD, TXD */
2376 162, 160,
2377 };
2378 static const unsigned int scifa5_data_2_mux[] = {
2379 PORT162_SCIFA5_RXD_MARK, PORT160_SCIFA5_TXD_MARK,
2380 };
2381 static const unsigned int scifa5_clk_2_pins[] = {
2382 /* SCK */
2383 159,
2384 };
2385 static const unsigned int scifa5_clk_2_mux[] = {
2386 PORT159_SCIFA5_SCK_MARK,
2387 };
2388 static const unsigned int scifa5_ctrl_2_pins[] = {
2389 /* RTS, CTS */
2390 163, 161,
2391 };
2392 static const unsigned int scifa5_ctrl_2_mux[] = {
2393 PORT163_SCIFA5_RTS__MARK, PORT161_SCIFA5_CTS__MARK,
2394 };
2395 /* - SCIFA6 ----------------------------------------------------------------- */
2396 static const unsigned int scifa6_pins[] = {
2397 /* TXD */
2398 240,
2399 };
2400 static const unsigned int scifa6_mux[] = {
2401 SCIFA6_TXD_MARK,
2402 };
2403 /* - SCIFA7 ----------------------------------------------------------------- */
2404 static const unsigned int scifa7_data_pins[] = {
2405 /* RXD, TXD */
2406 12, 18,
2407 };
2408 static const unsigned int scifa7_data_mux[] = {
2409 SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
2410 };
2411 static const unsigned int scifa7_ctrl_pins[] = {
2412 /* RTS, CTS */
2413 19, 13,
2414 };
2415 static const unsigned int scifa7_ctrl_mux[] = {
2416 SCIFA7_RTS__MARK, SCIFA7_CTS__MARK,
2417 };
2418 /* - SCIFB ------------------------------------------------------------------ */
2419 static const unsigned int scifb_data_0_pins[] = {
2420 /* RXD, TXD */
2421 162, 160,
2422 };
2423 static const unsigned int scifb_data_0_mux[] = {
2424 PORT162_SCIFB_RXD_MARK, PORT160_SCIFB_TXD_MARK,
2425 };
2426 static const unsigned int scifb_clk_0_pins[] = {
2427 /* SCK */
2428 159,
2429 };
2430 static const unsigned int scifb_clk_0_mux[] = {
2431 PORT159_SCIFB_SCK_MARK,
2432 };
2433 static const unsigned int scifb_ctrl_0_pins[] = {
2434 /* RTS, CTS */
2435 163, 161,
2436 };
2437 static const unsigned int scifb_ctrl_0_mux[] = {
2438 PORT163_SCIFB_RTS__MARK, PORT161_SCIFB_CTS__MARK,
2439 };
2440 static const unsigned int scifb_data_1_pins[] = {
2441 /* RXD, TXD */
2442 246, 247,
2443 };
2444 static const unsigned int scifb_data_1_mux[] = {
2445 PORT246_SCIFB_RXD_MARK, PORT247_SCIFB_TXD_MARK,
2446 };
2447 static const unsigned int scifb_clk_1_pins[] = {
2448 /* SCK */
2449 248,
2450 };
2451 static const unsigned int scifb_clk_1_mux[] = {
2452 PORT248_SCIFB_SCK_MARK,
2453 };
2454 static const unsigned int scifb_ctrl_1_pins[] = {
2455 /* RTS, CTS */
2456 245, 244,
2457 };
2458 static const unsigned int scifb_ctrl_1_mux[] = {
2459 PORT245_SCIFB_RTS__MARK, PORT244_SCIFB_CTS__MARK,
2460 };
2461 /* - SDHI0 ------------------------------------------------------------------ */
2462 static const unsigned int sdhi0_data1_pins[] = {
2463 /* D0 */
2464 252,
2465 };
2466 static const unsigned int sdhi0_data1_mux[] = {
2467 SDHID0_0_MARK,
2468 };
2469 static const unsigned int sdhi0_data4_pins[] = {
2470 /* D[0:3] */
2471 252, 253, 254, 255,
2472 };
2473 static const unsigned int sdhi0_data4_mux[] = {
2474 SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
2475 };
2476 static const unsigned int sdhi0_ctrl_pins[] = {
2477 /* CMD, CLK */
2478 256, 250,
2479 };
2480 static const unsigned int sdhi0_ctrl_mux[] = {
2481 SDHICMD0_MARK, SDHICLK0_MARK,
2482 };
2483 static const unsigned int sdhi0_cd_pins[] = {
2484 /* CD */
2485 251,
2486 };
2487 static const unsigned int sdhi0_cd_mux[] = {
2488 SDHICD0_MARK,
2489 };
2490 static const unsigned int sdhi0_wp_pins[] = {
2491 /* WP */
2492 257,
2493 };
2494 static const unsigned int sdhi0_wp_mux[] = {
2495 SDHIWP0_MARK,
2496 };
2497 /* - SDHI1 ------------------------------------------------------------------ */
2498 static const unsigned int sdhi1_data1_pins[] = {
2499 /* D0 */
2500 259,
2501 };
2502 static const unsigned int sdhi1_data1_mux[] = {
2503 SDHID1_0_MARK,
2504 };
2505 static const unsigned int sdhi1_data4_pins[] = {
2506 /* D[0:3] */
2507 259, 260, 261, 262,
2508 };
2509 static const unsigned int sdhi1_data4_mux[] = {
2510 SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
2511 };
2512 static const unsigned int sdhi1_ctrl_pins[] = {
2513 /* CMD, CLK */
2514 263, 258,
2515 };
2516 static const unsigned int sdhi1_ctrl_mux[] = {
2517 SDHICMD1_MARK, SDHICLK1_MARK,
2518 };
2519 /* - SDHI2 ------------------------------------------------------------------ */
2520 static const unsigned int sdhi2_data1_pins[] = {
2521 /* D0 */
2522 265,
2523 };
2524 static const unsigned int sdhi2_data1_mux[] = {
2525 SDHID2_0_MARK,
2526 };
2527 static const unsigned int sdhi2_data4_pins[] = {
2528 /* D[0:3] */
2529 265, 266, 267, 268,
2530 };
2531 static const unsigned int sdhi2_data4_mux[] = {
2532 SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
2533 };
2534 static const unsigned int sdhi2_ctrl_pins[] = {
2535 /* CMD, CLK */
2536 269, 264,
2537 };
2538 static const unsigned int sdhi2_ctrl_mux[] = {
2539 SDHICMD2_MARK, SDHICLK2_MARK,
2540 };
2541 /* - USB -------------------------------------------------------------------- */
2542 static const unsigned int usb_vbus_pins[] = {
2543 /* VBUS */
2544 0,
2545 };
2546 static const unsigned int usb_vbus_mux[] = {
2547 VBUS_0_MARK,
2548 };
2549
2550 static const struct sh_pfc_pin_group pinmux_groups[] = {
2551 SH_PFC_PIN_GROUP(bsc_data_0_7),
2552 SH_PFC_PIN_GROUP(bsc_data_8_15),
2553 SH_PFC_PIN_GROUP(bsc_cs4),
2554 SH_PFC_PIN_GROUP(bsc_cs5_a),
2555 SH_PFC_PIN_GROUP(bsc_cs5_b),
2556 SH_PFC_PIN_GROUP(bsc_cs6_a),
2557 SH_PFC_PIN_GROUP(bsc_cs6_b),
2558 SH_PFC_PIN_GROUP(bsc_rd),
2559 SH_PFC_PIN_GROUP(bsc_rdwr_0),
2560 SH_PFC_PIN_GROUP(bsc_rdwr_1),
2561 SH_PFC_PIN_GROUP(bsc_rdwr_2),
2562 SH_PFC_PIN_GROUP(bsc_we0),
2563 SH_PFC_PIN_GROUP(bsc_we1),
2564 SH_PFC_PIN_GROUP(fsia_mclk_in),
2565 SH_PFC_PIN_GROUP(fsia_mclk_out),
2566 SH_PFC_PIN_GROUP(fsia_sclk_in),
2567 SH_PFC_PIN_GROUP(fsia_sclk_out),
2568 SH_PFC_PIN_GROUP(fsia_data_in),
2569 SH_PFC_PIN_GROUP(fsia_data_out),
2570 SH_PFC_PIN_GROUP(fsia_spdif),
2571 SH_PFC_PIN_GROUP(fsib_mclk_in),
2572 SH_PFC_PIN_GROUP(fsib_mclk_out),
2573 SH_PFC_PIN_GROUP(fsib_sclk_in),
2574 SH_PFC_PIN_GROUP(fsib_sclk_out),
2575 SH_PFC_PIN_GROUP(fsib_data_in),
2576 SH_PFC_PIN_GROUP(fsib_data_out),
2577 SH_PFC_PIN_GROUP(fsib_spdif),
2578 SH_PFC_PIN_GROUP(fsic_mclk_in),
2579 SH_PFC_PIN_GROUP(fsic_mclk_out),
2580 SH_PFC_PIN_GROUP(fsic_sclk_in),
2581 SH_PFC_PIN_GROUP(fsic_sclk_out),
2582 SH_PFC_PIN_GROUP(fsic_data_in),
2583 SH_PFC_PIN_GROUP(fsic_data_out),
2584 SH_PFC_PIN_GROUP(fsic_spdif_0),
2585 SH_PFC_PIN_GROUP(fsic_spdif_1),
2586 SH_PFC_PIN_GROUP(fsid_sclk_in),
2587 SH_PFC_PIN_GROUP(fsid_sclk_out),
2588 SH_PFC_PIN_GROUP(fsid_data_in),
2589 SH_PFC_PIN_GROUP(i2c2_0),
2590 SH_PFC_PIN_GROUP(i2c2_1),
2591 SH_PFC_PIN_GROUP(i2c2_2),
2592 SH_PFC_PIN_GROUP(i2c3_0),
2593 SH_PFC_PIN_GROUP(i2c3_1),
2594 SH_PFC_PIN_GROUP(i2c3_2),
2595 SH_PFC_PIN_GROUP(irda_0),
2596 SH_PFC_PIN_GROUP(irda_1),
2597 SH_PFC_PIN_GROUP(keysc_in5),
2598 SH_PFC_PIN_GROUP(keysc_in6),
2599 SH_PFC_PIN_GROUP(keysc_in7),
2600 SH_PFC_PIN_GROUP(keysc_in8),
2601 SH_PFC_PIN_GROUP(keysc_out04),
2602 SH_PFC_PIN_GROUP(keysc_out5),
2603 SH_PFC_PIN_GROUP(keysc_out6_0),
2604 SH_PFC_PIN_GROUP(keysc_out6_1),
2605 SH_PFC_PIN_GROUP(keysc_out6_2),
2606 SH_PFC_PIN_GROUP(keysc_out7_0),
2607 SH_PFC_PIN_GROUP(keysc_out7_1),
2608 SH_PFC_PIN_GROUP(keysc_out7_2),
2609 SH_PFC_PIN_GROUP(keysc_out8_0),
2610 SH_PFC_PIN_GROUP(keysc_out8_1),
2611 SH_PFC_PIN_GROUP(keysc_out8_2),
2612 SH_PFC_PIN_GROUP(keysc_out9_0),
2613 SH_PFC_PIN_GROUP(keysc_out9_1),
2614 SH_PFC_PIN_GROUP(keysc_out9_2),
2615 SH_PFC_PIN_GROUP(keysc_out10_0),
2616 SH_PFC_PIN_GROUP(keysc_out10_1),
2617 SH_PFC_PIN_GROUP(keysc_out11_0),
2618 SH_PFC_PIN_GROUP(keysc_out11_1),
2619 SH_PFC_PIN_GROUP(lcd_data8),
2620 SH_PFC_PIN_GROUP(lcd_data9),
2621 SH_PFC_PIN_GROUP(lcd_data12),
2622 SH_PFC_PIN_GROUP(lcd_data16),
2623 SH_PFC_PIN_GROUP(lcd_data18),
2624 SH_PFC_PIN_GROUP(lcd_data24),
2625 SH_PFC_PIN_GROUP(lcd_display),
2626 SH_PFC_PIN_GROUP(lcd_lclk),
2627 SH_PFC_PIN_GROUP(lcd_sync),
2628 SH_PFC_PIN_GROUP(lcd_sys),
2629 SH_PFC_PIN_GROUP(lcd2_data8),
2630 SH_PFC_PIN_GROUP(lcd2_data9),
2631 SH_PFC_PIN_GROUP(lcd2_data12),
2632 SH_PFC_PIN_GROUP(lcd2_data16),
2633 SH_PFC_PIN_GROUP(lcd2_data18),
2634 SH_PFC_PIN_GROUP(lcd2_data24),
2635 SH_PFC_PIN_GROUP(lcd2_sync_0),
2636 SH_PFC_PIN_GROUP(lcd2_sync_1),
2637 SH_PFC_PIN_GROUP(lcd2_sys_0),
2638 SH_PFC_PIN_GROUP(lcd2_sys_1),
2639 SH_PFC_PIN_GROUP(mmc0_data1_0),
2640 SH_PFC_PIN_GROUP(mmc0_data4_0),
2641 SH_PFC_PIN_GROUP(mmc0_data8_0),
2642 SH_PFC_PIN_GROUP(mmc0_ctrl_0),
2643 SH_PFC_PIN_GROUP(mmc0_data1_1),
2644 SH_PFC_PIN_GROUP(mmc0_data4_1),
2645 SH_PFC_PIN_GROUP(mmc0_data8_1),
2646 SH_PFC_PIN_GROUP(mmc0_ctrl_1),
2647 SH_PFC_PIN_GROUP(scifa0_data),
2648 SH_PFC_PIN_GROUP(scifa0_clk),
2649 SH_PFC_PIN_GROUP(scifa0_ctrl),
2650 SH_PFC_PIN_GROUP(scifa1_data),
2651 SH_PFC_PIN_GROUP(scifa1_clk),
2652 SH_PFC_PIN_GROUP(scifa1_ctrl),
2653 SH_PFC_PIN_GROUP(scifa2_data_0),
2654 SH_PFC_PIN_GROUP(scifa2_clk_0),
2655 SH_PFC_PIN_GROUP(scifa2_ctrl_0),
2656 SH_PFC_PIN_GROUP(scifa2_data_1),
2657 SH_PFC_PIN_GROUP(scifa2_clk_1),
2658 SH_PFC_PIN_GROUP(scifa2_ctrl_1),
2659 SH_PFC_PIN_GROUP(scifa3_data),
2660 SH_PFC_PIN_GROUP(scifa3_ctrl),
2661 SH_PFC_PIN_GROUP(scifa4_data),
2662 SH_PFC_PIN_GROUP(scifa4_ctrl),
2663 SH_PFC_PIN_GROUP(scifa5_data_0),
2664 SH_PFC_PIN_GROUP(scifa5_clk_0),
2665 SH_PFC_PIN_GROUP(scifa5_ctrl_0),
2666 SH_PFC_PIN_GROUP(scifa5_data_1),
2667 SH_PFC_PIN_GROUP(scifa5_clk_1),
2668 SH_PFC_PIN_GROUP(scifa5_ctrl_1),
2669 SH_PFC_PIN_GROUP(scifa5_data_2),
2670 SH_PFC_PIN_GROUP(scifa5_clk_2),
2671 SH_PFC_PIN_GROUP(scifa5_ctrl_2),
2672 SH_PFC_PIN_GROUP(scifa6),
2673 SH_PFC_PIN_GROUP(scifa7_data),
2674 SH_PFC_PIN_GROUP(scifa7_ctrl),
2675 SH_PFC_PIN_GROUP(scifb_data_0),
2676 SH_PFC_PIN_GROUP(scifb_clk_0),
2677 SH_PFC_PIN_GROUP(scifb_ctrl_0),
2678 SH_PFC_PIN_GROUP(scifb_data_1),
2679 SH_PFC_PIN_GROUP(scifb_clk_1),
2680 SH_PFC_PIN_GROUP(scifb_ctrl_1),
2681 SH_PFC_PIN_GROUP(sdhi0_data1),
2682 SH_PFC_PIN_GROUP(sdhi0_data4),
2683 SH_PFC_PIN_GROUP(sdhi0_ctrl),
2684 SH_PFC_PIN_GROUP(sdhi0_cd),
2685 SH_PFC_PIN_GROUP(sdhi0_wp),
2686 SH_PFC_PIN_GROUP(sdhi1_data1),
2687 SH_PFC_PIN_GROUP(sdhi1_data4),
2688 SH_PFC_PIN_GROUP(sdhi1_ctrl),
2689 SH_PFC_PIN_GROUP(sdhi2_data1),
2690 SH_PFC_PIN_GROUP(sdhi2_data4),
2691 SH_PFC_PIN_GROUP(sdhi2_ctrl),
2692 SH_PFC_PIN_GROUP(usb_vbus),
2693 };
2694
2695 static const char * const bsc_groups[] = {
2696 "bsc_data_0_7",
2697 "bsc_data_8_15",
2698 "bsc_cs4",
2699 "bsc_cs5_a",
2700 "bsc_cs5_b",
2701 "bsc_cs6_a",
2702 "bsc_cs6_b",
2703 "bsc_rd",
2704 "bsc_rdwr_0",
2705 "bsc_rdwr_1",
2706 "bsc_rdwr_2",
2707 "bsc_we0",
2708 "bsc_we1",
2709 };
2710
2711 static const char * const fsia_groups[] = {
2712 "fsia_mclk_in",
2713 "fsia_mclk_out",
2714 "fsia_sclk_in",
2715 "fsia_sclk_out",
2716 "fsia_data_in",
2717 "fsia_data_out",
2718 "fsia_spdif",
2719 };
2720
2721 static const char * const fsib_groups[] = {
2722 "fsib_mclk_in",
2723 "fsib_mclk_out",
2724 "fsib_sclk_in",
2725 "fsib_sclk_out",
2726 "fsib_data_in",
2727 "fsib_data_out",
2728 "fsib_spdif",
2729 };
2730
2731 static const char * const fsic_groups[] = {
2732 "fsic_mclk_in",
2733 "fsic_mclk_out",
2734 "fsic_sclk_in",
2735 "fsic_sclk_out",
2736 "fsic_data_in",
2737 "fsic_data_out",
2738 "fsic_spdif",
2739 };
2740
2741 static const char * const fsid_groups[] = {
2742 "fsid_sclk_in",
2743 "fsid_sclk_out",
2744 "fsid_data_in",
2745 };
2746
2747 static const char * const i2c2_groups[] = {
2748 "i2c2_0",
2749 "i2c2_1",
2750 "i2c2_2",
2751 };
2752
2753 static const char * const i2c3_groups[] = {
2754 "i2c3_0",
2755 "i2c3_1",
2756 "i2c3_2",
2757 };
2758
2759 static const char * const irda_groups[] = {
2760 "irda_0",
2761 "irda_1",
2762 };
2763
2764 static const char * const keysc_groups[] = {
2765 "keysc_in5",
2766 "keysc_in6",
2767 "keysc_in7",
2768 "keysc_in8",
2769 "keysc_out04",
2770 "keysc_out5",
2771 "keysc_out6_0",
2772 "keysc_out6_1",
2773 "keysc_out6_2",
2774 "keysc_out7_0",
2775 "keysc_out7_1",
2776 "keysc_out7_2",
2777 "keysc_out8_0",
2778 "keysc_out8_1",
2779 "keysc_out8_2",
2780 "keysc_out9_0",
2781 "keysc_out9_1",
2782 "keysc_out9_2",
2783 "keysc_out10_0",
2784 "keysc_out10_1",
2785 "keysc_out11_0",
2786 "keysc_out11_1",
2787 };
2788
2789 static const char * const lcd_groups[] = {
2790 "lcd_data8",
2791 "lcd_data9",
2792 "lcd_data12",
2793 "lcd_data16",
2794 "lcd_data18",
2795 "lcd_data24",
2796 "lcd_display",
2797 "lcd_lclk",
2798 "lcd_sync",
2799 "lcd_sys",
2800 };
2801
2802 static const char * const lcd2_groups[] = {
2803 "lcd2_data8",
2804 "lcd2_data9",
2805 "lcd2_data12",
2806 "lcd2_data16",
2807 "lcd2_data18",
2808 "lcd2_data24",
2809 "lcd2_sync_0",
2810 "lcd2_sync_1",
2811 "lcd2_sys_0",
2812 "lcd2_sys_1",
2813 };
2814
2815 static const char * const mmc0_groups[] = {
2816 "mmc0_data1_0",
2817 "mmc0_data4_0",
2818 "mmc0_data8_0",
2819 "mmc0_ctrl_0",
2820 "mmc0_data1_1",
2821 "mmc0_data4_1",
2822 "mmc0_data8_1",
2823 "mmc0_ctrl_1",
2824 };
2825
2826 static const char * const scifa0_groups[] = {
2827 "scifa0_data",
2828 "scifa0_clk",
2829 "scifa0_ctrl",
2830 };
2831
2832 static const char * const scifa1_groups[] = {
2833 "scifa1_data",
2834 "scifa1_clk",
2835 "scifa1_ctrl",
2836 };
2837
2838 static const char * const scifa2_groups[] = {
2839 "scifa2_data_0",
2840 "scifa2_clk_0",
2841 "scifa2_ctrl_0",
2842 "scifa2_data_1",
2843 "scifa2_clk_1",
2844 "scifa2_ctrl_1",
2845 };
2846
2847 static const char * const scifa3_groups[] = {
2848 "scifa3_data",
2849 "scifa3_ctrl",
2850 };
2851
2852 static const char * const scifa4_groups[] = {
2853 "scifa4_data",
2854 "scifa4_ctrl",
2855 };
2856
2857 static const char * const scifa5_groups[] = {
2858 "scifa5_data_0",
2859 "scifa5_clk_0",
2860 "scifa5_ctrl_0",
2861 "scifa5_data_1",
2862 "scifa5_clk_1",
2863 "scifa5_ctrl_1",
2864 "scifa5_data_2",
2865 "scifa5_clk_2",
2866 "scifa5_ctrl_2",
2867 };
2868
2869 static const char * const scifa6_groups[] = {
2870 "scifa6",
2871 };
2872
2873 static const char * const scifa7_groups[] = {
2874 "scifa7_data",
2875 "scifa7_ctrl",
2876 };
2877
2878 static const char * const scifb_groups[] = {
2879 "scifb_data_0",
2880 "scifb_clk_0",
2881 "scifb_ctrl_0",
2882 "scifb_data_1",
2883 "scifb_clk_1",
2884 "scifb_ctrl_1",
2885 };
2886
2887 static const char * const sdhi0_groups[] = {
2888 "sdhi0_data1",
2889 "sdhi0_data4",
2890 "sdhi0_ctrl",
2891 "sdhi0_cd",
2892 "sdhi0_wp",
2893 };
2894
2895 static const char * const sdhi1_groups[] = {
2896 "sdhi1_data1",
2897 "sdhi1_data4",
2898 "sdhi1_ctrl",
2899 };
2900
2901 static const char * const sdhi2_groups[] = {
2902 "sdhi2_data1",
2903 "sdhi2_data4",
2904 "sdhi2_ctrl",
2905 };
2906
2907 static const char * const usb_groups[] = {
2908 "usb_vbus",
2909 };
2910
2911 static const struct sh_pfc_function pinmux_functions[] = {
2912 SH_PFC_FUNCTION(bsc),
2913 SH_PFC_FUNCTION(fsia),
2914 SH_PFC_FUNCTION(fsib),
2915 SH_PFC_FUNCTION(fsic),
2916 SH_PFC_FUNCTION(fsid),
2917 SH_PFC_FUNCTION(i2c2),
2918 SH_PFC_FUNCTION(i2c3),
2919 SH_PFC_FUNCTION(irda),
2920 SH_PFC_FUNCTION(keysc),
2921 SH_PFC_FUNCTION(lcd),
2922 SH_PFC_FUNCTION(lcd2),
2923 SH_PFC_FUNCTION(mmc0),
2924 SH_PFC_FUNCTION(scifa0),
2925 SH_PFC_FUNCTION(scifa1),
2926 SH_PFC_FUNCTION(scifa2),
2927 SH_PFC_FUNCTION(scifa3),
2928 SH_PFC_FUNCTION(scifa4),
2929 SH_PFC_FUNCTION(scifa5),
2930 SH_PFC_FUNCTION(scifa6),
2931 SH_PFC_FUNCTION(scifa7),
2932 SH_PFC_FUNCTION(scifb),
2933 SH_PFC_FUNCTION(sdhi0),
2934 SH_PFC_FUNCTION(sdhi1),
2935 SH_PFC_FUNCTION(sdhi2),
2936 SH_PFC_FUNCTION(usb),
2937 };
2938
2939 #define PINMUX_FN_BASE GPIO_FN_GPI0
2940
2941 static const struct pinmux_func pinmux_func_gpios[] = {
2942 /* Table 25-1 (Functions 0-7) */
2943 GPIO_FN(GPI0),
2944 GPIO_FN(GPI1),
2945 GPIO_FN(GPI2),
2946 GPIO_FN(GPI3),
2947 GPIO_FN(GPI4),
2948 GPIO_FN(GPI5),
2949 GPIO_FN(GPI6),
2950 GPIO_FN(GPI7),
2951 GPIO_FN(GPO7), \
2952 GPIO_FN(MFG0_OUT2),
2953 GPIO_FN(GPO6), \
2954 GPIO_FN(MFG1_OUT2),
2955 GPIO_FN(GPO5), \
2956 GPIO_FN(PORT16_VIO_CKOR),
2957 GPIO_FN(PORT19_VIO_CKO2),
2958 GPIO_FN(GPO0),
2959 GPIO_FN(GPO1),
2960 GPIO_FN(GPO2), \
2961 GPIO_FN(STATUS0),
2962 GPIO_FN(GPO3), \
2963 GPIO_FN(STATUS1),
2964 GPIO_FN(GPO4), \
2965 GPIO_FN(STATUS2),
2966 GPIO_FN(VINT),
2967 GPIO_FN(TCKON),
2968 GPIO_FN(XDVFS1), \
2969 GPIO_FN(MFG0_OUT1), \
2970 GPIO_FN(PORT27_IROUT),
2971 GPIO_FN(XDVFS2), \
2972 GPIO_FN(PORT28_TPU1TO1),
2973 GPIO_FN(SIM_RST), \
2974 GPIO_FN(PORT29_TPU1TO1),
2975 GPIO_FN(SIM_CLK), \
2976 GPIO_FN(PORT30_VIO_CKOR),
2977 GPIO_FN(SIM_D), \
2978 GPIO_FN(PORT31_IROUT),
2979 GPIO_FN(XWUP),
2980 GPIO_FN(VACK),
2981 GPIO_FN(XTAL1L),
2982 GPIO_FN(PORT49_IROUT), \
2983 GPIO_FN(BBIF2_TSYNC2), \
2984 GPIO_FN(TPU2TO2), \
2985
2986 GPIO_FN(BBIF2_TSCK2), \
2987 GPIO_FN(TPU2TO3), \
2988 GPIO_FN(BBIF2_TXD2),
2989 GPIO_FN(TPU3TO3), \
2990 GPIO_FN(TPU3TO2), \
2991 GPIO_FN(TPU0TO0),
2992 GPIO_FN(A0), \
2993 GPIO_FN(BS_),
2994 GPIO_FN(A12), \
2995 GPIO_FN(TPU4TO2),
2996 GPIO_FN(A13), \
2997 GPIO_FN(TPU0TO1),
2998 GPIO_FN(A14), \
2999 GPIO_FN(A15), \
3000 GPIO_FN(A16), \
3001 GPIO_FN(MSIOF0_SS1),
3002 GPIO_FN(A17), \
3003 GPIO_FN(MSIOF0_TSYNC),
3004 GPIO_FN(A18), \
3005 GPIO_FN(MSIOF0_TSCK),
3006 GPIO_FN(A19), \
3007 GPIO_FN(MSIOF0_TXD),
3008 GPIO_FN(A20), \
3009 GPIO_FN(MSIOF0_RSCK),
3010 GPIO_FN(A21), \
3011 GPIO_FN(MSIOF0_RSYNC),
3012 GPIO_FN(A22), \
3013 GPIO_FN(MSIOF0_MCK0),
3014 GPIO_FN(A23), \
3015 GPIO_FN(MSIOF0_MCK1),
3016 GPIO_FN(A24), \
3017 GPIO_FN(MSIOF0_RXD),
3018 GPIO_FN(A25), \
3019 GPIO_FN(MSIOF0_SS2),
3020 GPIO_FN(A26), \
3021 GPIO_FN(FCE1_),
3022 GPIO_FN(DACK0),
3023 GPIO_FN(FCE0_), \
3024 GPIO_FN(WAIT_), \
3025 GPIO_FN(DREQ0),
3026 GPIO_FN(FRB),
3027 GPIO_FN(CKO),
3028 GPIO_FN(NBRSTOUT_),
3029 GPIO_FN(NBRST_),
3030 GPIO_FN(BBIF2_TXD),
3031 GPIO_FN(BBIF2_RXD),
3032 GPIO_FN(BBIF2_SYNC),
3033 GPIO_FN(BBIF2_SCK),
3034 GPIO_FN(MFG3_IN2),
3035 GPIO_FN(MFG3_IN1),
3036 GPIO_FN(BBIF1_SS2), \
3037 GPIO_FN(MFG3_OUT1),
3038 GPIO_FN(HSI_RX_DATA), \
3039 GPIO_FN(BBIF1_RXD),
3040 GPIO_FN(HSI_TX_WAKE), \
3041 GPIO_FN(BBIF1_TSCK),
3042 GPIO_FN(HSI_TX_DATA), \
3043 GPIO_FN(BBIF1_TSYNC),
3044 GPIO_FN(HSI_TX_READY), \
3045 GPIO_FN(BBIF1_TXD),
3046 GPIO_FN(HSI_RX_READY), \
3047 GPIO_FN(BBIF1_RSCK), \
3048 GPIO_FN(HSI_RX_WAKE), \
3049 GPIO_FN(BBIF1_RSYNC), \
3050 GPIO_FN(HSI_RX_FLAG), \
3051 GPIO_FN(BBIF1_SS1), \
3052 GPIO_FN(BBIF1_FLOW),
3053 GPIO_FN(HSI_TX_FLAG),
3054 GPIO_FN(VIO_VD), \
3055 GPIO_FN(VIO2_VD), \
3056
3057 GPIO_FN(VIO_HD), \
3058 GPIO_FN(VIO2_HD), \
3059 GPIO_FN(VIO_D0), \
3060 GPIO_FN(PORT130_MSIOF2_RXD), \
3061 GPIO_FN(VIO_D1), \
3062 GPIO_FN(PORT131_MSIOF2_SS1), \
3063 GPIO_FN(VIO_D2), \
3064 GPIO_FN(PORT132_MSIOF2_SS2), \
3065 GPIO_FN(VIO_D3), \
3066 GPIO_FN(MSIOF2_TSYNC), \
3067 GPIO_FN(VIO_D4), \
3068 GPIO_FN(MSIOF2_TXD), \
3069 GPIO_FN(VIO_D5), \
3070 GPIO_FN(MSIOF2_TSCK), \
3071 GPIO_FN(VIO_D6), \
3072 GPIO_FN(VIO_D7), \
3073 GPIO_FN(VIO_D8), \
3074 GPIO_FN(VIO2_D0), \
3075 GPIO_FN(VIO_D9), \
3076 GPIO_FN(VIO2_D1), \
3077 GPIO_FN(VIO_D10), \
3078 GPIO_FN(TPU0TO2), \
3079 GPIO_FN(VIO2_D2), \
3080 GPIO_FN(VIO_D11), \
3081 GPIO_FN(TPU0TO3), \
3082 GPIO_FN(VIO2_D3), \
3083 GPIO_FN(VIO_D12), \
3084 GPIO_FN(VIO2_D4), \
3085 GPIO_FN(VIO_D13), \
3086 GPIO_FN(VIO2_D5), \
3087 GPIO_FN(VIO_D14), \
3088 GPIO_FN(VIO2_D6), \
3089 GPIO_FN(VIO_D15), \
3090 GPIO_FN(TPU1TO3), \
3091 GPIO_FN(VIO2_D7), \
3092 GPIO_FN(VIO_CLK), \
3093 GPIO_FN(VIO2_CLK), \
3094 GPIO_FN(VIO_FIELD), \
3095 GPIO_FN(VIO2_FIELD), \
3096 GPIO_FN(VIO_CKO),
3097 GPIO_FN(A27), \
3098 GPIO_FN(MFG0_IN1), \
3099 GPIO_FN(MFG0_IN2),
3100 GPIO_FN(TS_SPSYNC3), \
3101 GPIO_FN(MSIOF2_RSCK),
3102 GPIO_FN(TS_SDAT3), \
3103 GPIO_FN(MSIOF2_RSYNC),
3104 GPIO_FN(TPU1TO2), \
3105 GPIO_FN(TS_SDEN3), \
3106 GPIO_FN(PORT153_MSIOF2_SS1),
3107 GPIO_FN(MSIOF2_MCK0),
3108 GPIO_FN(MSIOF2_MCK1),
3109 GPIO_FN(PORT156_MSIOF2_SS2),
3110 GPIO_FN(PORT157_MSIOF2_RXD),
3111 GPIO_FN(DINT_), \
3112 GPIO_FN(TS_SCK3),
3113 GPIO_FN(NMI),
3114 GPIO_FN(TPU3TO0),
3115 GPIO_FN(BBIF2_TSYNC1),
3116 GPIO_FN(BBIF2_TSCK1),
3117 GPIO_FN(BBIF2_TXD1),
3118 GPIO_FN(MFG2_OUT2), \
3119 GPIO_FN(TPU2TO1),
3120 GPIO_FN(TPU4TO1), \
3121 GPIO_FN(MFG4_OUT2),
3122 GPIO_FN(D16),
3123 GPIO_FN(D17),
3124 GPIO_FN(D18),
3125 GPIO_FN(D19),
3126 GPIO_FN(D20),
3127 GPIO_FN(D21),
3128 GPIO_FN(D22),
3129 GPIO_FN(PORT207_MSIOF0L_SS1), \
3130 GPIO_FN(D23),
3131 GPIO_FN(PORT208_MSIOF0L_SS2), \
3132 GPIO_FN(D24),
3133 GPIO_FN(D25),
3134 GPIO_FN(DREQ2), \
3135 GPIO_FN(PORT210_MSIOF0L_SS1), \
3136 GPIO_FN(D26),
3137 GPIO_FN(PORT211_MSIOF0L_SS2), \
3138 GPIO_FN(D27),
3139 GPIO_FN(TS_SPSYNC1), \
3140 GPIO_FN(MSIOF0L_MCK0), \
3141 GPIO_FN(D28),
3142 GPIO_FN(TS_SDAT1), \
3143 GPIO_FN(MSIOF0L_MCK1), \
3144 GPIO_FN(D29),
3145 GPIO_FN(TS_SDEN1), \
3146 GPIO_FN(MSIOF0L_RSCK), \
3147 GPIO_FN(D30),
3148 GPIO_FN(TS_SCK1), \
3149 GPIO_FN(MSIOF0L_RSYNC), \
3150 GPIO_FN(D31),
3151 GPIO_FN(DACK2), \
3152 GPIO_FN(MSIOF0L_TSYNC), \
3153 GPIO_FN(VIO2_FIELD3), \
3154 GPIO_FN(DACK3), \
3155 GPIO_FN(PORT218_VIO_CKOR),
3156 GPIO_FN(DREQ3), \
3157 GPIO_FN(MSIOF0L_TSCK), \
3158 GPIO_FN(VIO2_CLK3), \
3159 GPIO_FN(DREQ1), \
3160 GPIO_FN(PWEN), \
3161 GPIO_FN(MSIOF0L_RXD), \
3162 GPIO_FN(VIO2_HD3), \
3163 GPIO_FN(DACK1), \
3164 GPIO_FN(OVCN), \
3165 GPIO_FN(MSIOF0L_TXD), \
3166 GPIO_FN(VIO2_VD3), \
3167
3168 GPIO_FN(OVCN2),
3169 GPIO_FN(EXTLP), \
3170 GPIO_FN(PORT226_VIO_CKO2),
3171 GPIO_FN(IDIN),
3172 GPIO_FN(MFG1_IN1),
3173 GPIO_FN(MSIOF1_TXD), \
3174 GPIO_FN(MSIOF1_TSYNC), \
3175 GPIO_FN(MSIOF1_TSCK), \
3176 GPIO_FN(MSIOF1_RXD), \
3177 GPIO_FN(MSIOF1_RSCK), \
3178 GPIO_FN(VIO2_CLK2), \
3179 GPIO_FN(MSIOF1_RSYNC), \
3180 GPIO_FN(MFG1_IN2), \
3181 GPIO_FN(VIO2_VD2), \
3182 GPIO_FN(MSIOF1_MCK0), \
3183 GPIO_FN(MSIOF1_MCK1), \
3184 GPIO_FN(MSIOF1_SS1), \
3185 GPIO_FN(VIO2_FIELD2), \
3186 GPIO_FN(MSIOF1_SS2), \
3187 GPIO_FN(VIO2_HD2), \
3188 GPIO_FN(PORT241_IROUT), \
3189 GPIO_FN(MFG4_OUT1), \
3190 GPIO_FN(TPU4TO0),
3191 GPIO_FN(MFG4_IN2),
3192 GPIO_FN(PORT243_VIO_CKO2),
3193 GPIO_FN(MFG2_IN1), \
3194 GPIO_FN(MSIOF2R_RXD),
3195 GPIO_FN(MFG2_IN2), \
3196 GPIO_FN(MSIOF2R_TXD),
3197 GPIO_FN(MFG1_OUT1), \
3198 GPIO_FN(TPU1TO0),
3199 GPIO_FN(MFG3_OUT2), \
3200 GPIO_FN(TPU3TO1),
3201 GPIO_FN(MFG2_OUT1), \
3202 GPIO_FN(TPU2TO0), \
3203 GPIO_FN(MSIOF2R_TSCK),
3204 GPIO_FN(PORT249_IROUT), \
3205 GPIO_FN(MFG4_IN1), \
3206 GPIO_FN(MSIOF2R_TSYNC),
3207 GPIO_FN(SDHICLK0),
3208 GPIO_FN(SDHICD0),
3209 GPIO_FN(SDHID0_0),
3210 GPIO_FN(SDHID0_1),
3211 GPIO_FN(SDHID0_2),
3212 GPIO_FN(SDHID0_3),
3213 GPIO_FN(SDHICMD0),
3214 GPIO_FN(SDHIWP0),
3215 GPIO_FN(SDHICLK1),
3216 GPIO_FN(SDHID1_0), \
3217 GPIO_FN(TS_SPSYNC2),
3218 GPIO_FN(SDHID1_1), \
3219 GPIO_FN(TS_SDAT2),
3220 GPIO_FN(SDHID1_2), \
3221 GPIO_FN(TS_SDEN2),
3222 GPIO_FN(SDHID1_3), \
3223 GPIO_FN(TS_SCK2),
3224 GPIO_FN(SDHICMD1),
3225 GPIO_FN(SDHICLK2),
3226 GPIO_FN(SDHID2_0), \
3227 GPIO_FN(TS_SPSYNC4),
3228 GPIO_FN(SDHID2_1), \
3229 GPIO_FN(TS_SDAT4),
3230 GPIO_FN(SDHID2_2), \
3231 GPIO_FN(TS_SDEN4),
3232 GPIO_FN(SDHID2_3), \
3233 GPIO_FN(TS_SCK4),
3234 GPIO_FN(SDHICMD2),
3235 GPIO_FN(MMCCLK0),
3236 GPIO_FN(MMCD0_0),
3237 GPIO_FN(MMCD0_1),
3238 GPIO_FN(MMCD0_2),
3239 GPIO_FN(MMCD0_3),
3240 GPIO_FN(MMCD0_4), \
3241 GPIO_FN(TS_SPSYNC5),
3242 GPIO_FN(MMCD0_5), \
3243 GPIO_FN(TS_SDAT5),
3244 GPIO_FN(MMCD0_6), \
3245 GPIO_FN(TS_SDEN5),
3246 GPIO_FN(MMCD0_7), \
3247 GPIO_FN(TS_SCK5),
3248 GPIO_FN(MMCCMD0),
3249 GPIO_FN(RESETOUTS_), \
3250 GPIO_FN(EXTAL2OUT),
3251 GPIO_FN(MCP_WAIT__MCP_FRB),
3252 GPIO_FN(MCP_CKO), \
3253 GPIO_FN(MMCCLK1),
3254 GPIO_FN(MCP_D15_MCP_NAF15),
3255 GPIO_FN(MCP_D14_MCP_NAF14),
3256 GPIO_FN(MCP_D13_MCP_NAF13),
3257 GPIO_FN(MCP_D12_MCP_NAF12),
3258 GPIO_FN(MCP_D11_MCP_NAF11),
3259 GPIO_FN(MCP_D10_MCP_NAF10),
3260 GPIO_FN(MCP_D9_MCP_NAF9),
3261 GPIO_FN(MCP_D8_MCP_NAF8), \
3262 GPIO_FN(MMCCMD1),
3263 GPIO_FN(MCP_D7_MCP_NAF7), \
3264 GPIO_FN(MMCD1_7),
3265
3266 GPIO_FN(MCP_D6_MCP_NAF6), \
3267 GPIO_FN(MMCD1_6),
3268 GPIO_FN(MCP_D5_MCP_NAF5), \
3269 GPIO_FN(MMCD1_5),
3270 GPIO_FN(MCP_D4_MCP_NAF4), \
3271 GPIO_FN(MMCD1_4),
3272 GPIO_FN(MCP_D3_MCP_NAF3), \
3273 GPIO_FN(MMCD1_3),
3274 GPIO_FN(MCP_D2_MCP_NAF2), \
3275 GPIO_FN(MMCD1_2),
3276 GPIO_FN(MCP_D1_MCP_NAF1), \
3277 GPIO_FN(MMCD1_1),
3278 GPIO_FN(MCP_D0_MCP_NAF0), \
3279 GPIO_FN(MMCD1_0),
3280 GPIO_FN(MCP_NBRSTOUT_),
3281 GPIO_FN(MCP_WE0__MCP_FWE), \
3282 GPIO_FN(MCP_RDWR_MCP_FWE),
3283
3284 /* MSEL2 special cases */
3285 GPIO_FN(TSIF2_TS_XX1),
3286 GPIO_FN(TSIF2_TS_XX2),
3287 GPIO_FN(TSIF2_TS_XX3),
3288 GPIO_FN(TSIF2_TS_XX4),
3289 GPIO_FN(TSIF2_TS_XX5),
3290 GPIO_FN(TSIF1_TS_XX1),
3291 GPIO_FN(TSIF1_TS_XX2),
3292 GPIO_FN(TSIF1_TS_XX3),
3293 GPIO_FN(TSIF1_TS_XX4),
3294 GPIO_FN(TSIF1_TS_XX5),
3295 GPIO_FN(TSIF0_TS_XX1),
3296 GPIO_FN(TSIF0_TS_XX2),
3297 GPIO_FN(TSIF0_TS_XX3),
3298 GPIO_FN(TSIF0_TS_XX4),
3299 GPIO_FN(TSIF0_TS_XX5),
3300 GPIO_FN(MST1_TS_XX1),
3301 GPIO_FN(MST1_TS_XX2),
3302 GPIO_FN(MST1_TS_XX3),
3303 GPIO_FN(MST1_TS_XX4),
3304 GPIO_FN(MST1_TS_XX5),
3305 GPIO_FN(MST0_TS_XX1),
3306 GPIO_FN(MST0_TS_XX2),
3307 GPIO_FN(MST0_TS_XX3),
3308 GPIO_FN(MST0_TS_XX4),
3309 GPIO_FN(MST0_TS_XX5),
3310
3311 /* MSEL3 special cases */
3312 GPIO_FN(SDHI0_VCCQ_MC0_ON),
3313 GPIO_FN(SDHI0_VCCQ_MC0_OFF),
3314 GPIO_FN(DEBUG_MON_VIO),
3315 GPIO_FN(DEBUG_MON_LCDD),
3316 GPIO_FN(LCDC_LCDC0),
3317 GPIO_FN(LCDC_LCDC1),
3318
3319 /* MSEL4 special cases */
3320 GPIO_FN(IRQ9_MEM_INT),
3321 GPIO_FN(IRQ9_MCP_INT),
3322 GPIO_FN(A11),
3323 GPIO_FN(TPU4TO3),
3324 GPIO_FN(RESETA_N_PU_ON),
3325 GPIO_FN(RESETA_N_PU_OFF),
3326 GPIO_FN(EDBGREQ_PD),
3327 GPIO_FN(EDBGREQ_PU),
3328 };
3329
3330 #undef PORTCR
3331 #define PORTCR(nr, reg) \
3332 { \
3333 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
3334 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
3335 PORT##nr##_FN0, PORT##nr##_FN1, \
3336 PORT##nr##_FN2, PORT##nr##_FN3, \
3337 PORT##nr##_FN4, PORT##nr##_FN5, \
3338 PORT##nr##_FN6, PORT##nr##_FN7 } \
3339 }
3340 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3341 PORTCR(0, 0xe6050000), /* PORT0CR */
3342 PORTCR(1, 0xe6050001), /* PORT1CR */
3343 PORTCR(2, 0xe6050002), /* PORT2CR */
3344 PORTCR(3, 0xe6050003), /* PORT3CR */
3345 PORTCR(4, 0xe6050004), /* PORT4CR */
3346 PORTCR(5, 0xe6050005), /* PORT5CR */
3347 PORTCR(6, 0xe6050006), /* PORT6CR */
3348 PORTCR(7, 0xe6050007), /* PORT7CR */
3349 PORTCR(8, 0xe6050008), /* PORT8CR */
3350 PORTCR(9, 0xe6050009), /* PORT9CR */
3351
3352 PORTCR(10, 0xe605000a), /* PORT10CR */
3353 PORTCR(11, 0xe605000b), /* PORT11CR */
3354 PORTCR(12, 0xe605000c), /* PORT12CR */
3355 PORTCR(13, 0xe605000d), /* PORT13CR */
3356 PORTCR(14, 0xe605000e), /* PORT14CR */
3357 PORTCR(15, 0xe605000f), /* PORT15CR */
3358 PORTCR(16, 0xe6050010), /* PORT16CR */
3359 PORTCR(17, 0xe6050011), /* PORT17CR */
3360 PORTCR(18, 0xe6050012), /* PORT18CR */
3361 PORTCR(19, 0xe6050013), /* PORT19CR */
3362
3363 PORTCR(20, 0xe6050014), /* PORT20CR */
3364 PORTCR(21, 0xe6050015), /* PORT21CR */
3365 PORTCR(22, 0xe6050016), /* PORT22CR */
3366 PORTCR(23, 0xe6050017), /* PORT23CR */
3367 PORTCR(24, 0xe6050018), /* PORT24CR */
3368 PORTCR(25, 0xe6050019), /* PORT25CR */
3369 PORTCR(26, 0xe605001a), /* PORT26CR */
3370 PORTCR(27, 0xe605001b), /* PORT27CR */
3371 PORTCR(28, 0xe605001c), /* PORT28CR */
3372 PORTCR(29, 0xe605001d), /* PORT29CR */
3373
3374 PORTCR(30, 0xe605001e), /* PORT30CR */
3375 PORTCR(31, 0xe605001f), /* PORT31CR */
3376 PORTCR(32, 0xe6051020), /* PORT32CR */
3377 PORTCR(33, 0xe6051021), /* PORT33CR */
3378 PORTCR(34, 0xe6051022), /* PORT34CR */
3379 PORTCR(35, 0xe6051023), /* PORT35CR */
3380 PORTCR(36, 0xe6051024), /* PORT36CR */
3381 PORTCR(37, 0xe6051025), /* PORT37CR */
3382 PORTCR(38, 0xe6051026), /* PORT38CR */
3383 PORTCR(39, 0xe6051027), /* PORT39CR */
3384
3385 PORTCR(40, 0xe6051028), /* PORT40CR */
3386 PORTCR(41, 0xe6051029), /* PORT41CR */
3387 PORTCR(42, 0xe605102a), /* PORT42CR */
3388 PORTCR(43, 0xe605102b), /* PORT43CR */
3389 PORTCR(44, 0xe605102c), /* PORT44CR */
3390 PORTCR(45, 0xe605102d), /* PORT45CR */
3391 PORTCR(46, 0xe605102e), /* PORT46CR */
3392 PORTCR(47, 0xe605102f), /* PORT47CR */
3393 PORTCR(48, 0xe6051030), /* PORT48CR */
3394 PORTCR(49, 0xe6051031), /* PORT49CR */
3395
3396 PORTCR(50, 0xe6051032), /* PORT50CR */
3397 PORTCR(51, 0xe6051033), /* PORT51CR */
3398 PORTCR(52, 0xe6051034), /* PORT52CR */
3399 PORTCR(53, 0xe6051035), /* PORT53CR */
3400 PORTCR(54, 0xe6051036), /* PORT54CR */
3401 PORTCR(55, 0xe6051037), /* PORT55CR */
3402 PORTCR(56, 0xe6051038), /* PORT56CR */
3403 PORTCR(57, 0xe6051039), /* PORT57CR */
3404 PORTCR(58, 0xe605103a), /* PORT58CR */
3405 PORTCR(59, 0xe605103b), /* PORT59CR */
3406
3407 PORTCR(60, 0xe605103c), /* PORT60CR */
3408 PORTCR(61, 0xe605103d), /* PORT61CR */
3409 PORTCR(62, 0xe605103e), /* PORT62CR */
3410 PORTCR(63, 0xe605103f), /* PORT63CR */
3411 PORTCR(64, 0xe6051040), /* PORT64CR */
3412 PORTCR(65, 0xe6051041), /* PORT65CR */
3413 PORTCR(66, 0xe6051042), /* PORT66CR */
3414 PORTCR(67, 0xe6051043), /* PORT67CR */
3415 PORTCR(68, 0xe6051044), /* PORT68CR */
3416 PORTCR(69, 0xe6051045), /* PORT69CR */
3417
3418 PORTCR(70, 0xe6051046), /* PORT70CR */
3419 PORTCR(71, 0xe6051047), /* PORT71CR */
3420 PORTCR(72, 0xe6051048), /* PORT72CR */
3421 PORTCR(73, 0xe6051049), /* PORT73CR */
3422 PORTCR(74, 0xe605104a), /* PORT74CR */
3423 PORTCR(75, 0xe605104b), /* PORT75CR */
3424 PORTCR(76, 0xe605104c), /* PORT76CR */
3425 PORTCR(77, 0xe605104d), /* PORT77CR */
3426 PORTCR(78, 0xe605104e), /* PORT78CR */
3427 PORTCR(79, 0xe605104f), /* PORT79CR */
3428
3429 PORTCR(80, 0xe6051050), /* PORT80CR */
3430 PORTCR(81, 0xe6051051), /* PORT81CR */
3431 PORTCR(82, 0xe6051052), /* PORT82CR */
3432 PORTCR(83, 0xe6051053), /* PORT83CR */
3433 PORTCR(84, 0xe6051054), /* PORT84CR */
3434 PORTCR(85, 0xe6051055), /* PORT85CR */
3435 PORTCR(86, 0xe6051056), /* PORT86CR */
3436 PORTCR(87, 0xe6051057), /* PORT87CR */
3437 PORTCR(88, 0xe6051058), /* PORT88CR */
3438 PORTCR(89, 0xe6051059), /* PORT89CR */
3439
3440 PORTCR(90, 0xe605105a), /* PORT90CR */
3441 PORTCR(91, 0xe605105b), /* PORT91CR */
3442 PORTCR(92, 0xe605105c), /* PORT92CR */
3443 PORTCR(93, 0xe605105d), /* PORT93CR */
3444 PORTCR(94, 0xe605105e), /* PORT94CR */
3445 PORTCR(95, 0xe605105f), /* PORT95CR */
3446 PORTCR(96, 0xe6052060), /* PORT96CR */
3447 PORTCR(97, 0xe6052061), /* PORT97CR */
3448 PORTCR(98, 0xe6052062), /* PORT98CR */
3449 PORTCR(99, 0xe6052063), /* PORT99CR */
3450
3451 PORTCR(100, 0xe6052064), /* PORT100CR */
3452 PORTCR(101, 0xe6052065), /* PORT101CR */
3453 PORTCR(102, 0xe6052066), /* PORT102CR */
3454 PORTCR(103, 0xe6052067), /* PORT103CR */
3455 PORTCR(104, 0xe6052068), /* PORT104CR */
3456 PORTCR(105, 0xe6052069), /* PORT105CR */
3457 PORTCR(106, 0xe605206a), /* PORT106CR */
3458 PORTCR(107, 0xe605206b), /* PORT107CR */
3459 PORTCR(108, 0xe605206c), /* PORT108CR */
3460 PORTCR(109, 0xe605206d), /* PORT109CR */
3461
3462 PORTCR(110, 0xe605206e), /* PORT110CR */
3463 PORTCR(111, 0xe605206f), /* PORT111CR */
3464 PORTCR(112, 0xe6052070), /* PORT112CR */
3465 PORTCR(113, 0xe6052071), /* PORT113CR */
3466 PORTCR(114, 0xe6052072), /* PORT114CR */
3467 PORTCR(115, 0xe6052073), /* PORT115CR */
3468 PORTCR(116, 0xe6052074), /* PORT116CR */
3469 PORTCR(117, 0xe6052075), /* PORT117CR */
3470 PORTCR(118, 0xe6052076), /* PORT118CR */
3471
3472 PORTCR(128, 0xe6052080), /* PORT128CR */
3473 PORTCR(129, 0xe6052081), /* PORT129CR */
3474
3475 PORTCR(130, 0xe6052082), /* PORT130CR */
3476 PORTCR(131, 0xe6052083), /* PORT131CR */
3477 PORTCR(132, 0xe6052084), /* PORT132CR */
3478 PORTCR(133, 0xe6052085), /* PORT133CR */
3479 PORTCR(134, 0xe6052086), /* PORT134CR */
3480 PORTCR(135, 0xe6052087), /* PORT135CR */
3481 PORTCR(136, 0xe6052088), /* PORT136CR */
3482 PORTCR(137, 0xe6052089), /* PORT137CR */
3483 PORTCR(138, 0xe605208a), /* PORT138CR */
3484 PORTCR(139, 0xe605208b), /* PORT139CR */
3485
3486 PORTCR(140, 0xe605208c), /* PORT140CR */
3487 PORTCR(141, 0xe605208d), /* PORT141CR */
3488 PORTCR(142, 0xe605208e), /* PORT142CR */
3489 PORTCR(143, 0xe605208f), /* PORT143CR */
3490 PORTCR(144, 0xe6052090), /* PORT144CR */
3491 PORTCR(145, 0xe6052091), /* PORT145CR */
3492 PORTCR(146, 0xe6052092), /* PORT146CR */
3493 PORTCR(147, 0xe6052093), /* PORT147CR */
3494 PORTCR(148, 0xe6052094), /* PORT148CR */
3495 PORTCR(149, 0xe6052095), /* PORT149CR */
3496
3497 PORTCR(150, 0xe6052096), /* PORT150CR */
3498 PORTCR(151, 0xe6052097), /* PORT151CR */
3499 PORTCR(152, 0xe6052098), /* PORT152CR */
3500 PORTCR(153, 0xe6052099), /* PORT153CR */
3501 PORTCR(154, 0xe605209a), /* PORT154CR */
3502 PORTCR(155, 0xe605209b), /* PORT155CR */
3503 PORTCR(156, 0xe605209c), /* PORT156CR */
3504 PORTCR(157, 0xe605209d), /* PORT157CR */
3505 PORTCR(158, 0xe605209e), /* PORT158CR */
3506 PORTCR(159, 0xe605209f), /* PORT159CR */
3507
3508 PORTCR(160, 0xe60520a0), /* PORT160CR */
3509 PORTCR(161, 0xe60520a1), /* PORT161CR */
3510 PORTCR(162, 0xe60520a2), /* PORT162CR */
3511 PORTCR(163, 0xe60520a3), /* PORT163CR */
3512 PORTCR(164, 0xe60520a4), /* PORT164CR */
3513
3514 PORTCR(192, 0xe60520c0), /* PORT192CR */
3515 PORTCR(193, 0xe60520c1), /* PORT193CR */
3516 PORTCR(194, 0xe60520c2), /* PORT194CR */
3517 PORTCR(195, 0xe60520c3), /* PORT195CR */
3518 PORTCR(196, 0xe60520c4), /* PORT196CR */
3519 PORTCR(197, 0xe60520c5), /* PORT197CR */
3520 PORTCR(198, 0xe60520c6), /* PORT198CR */
3521 PORTCR(199, 0xe60520c7), /* PORT199CR */
3522
3523 PORTCR(200, 0xe60520c8), /* PORT200CR */
3524 PORTCR(201, 0xe60520c9), /* PORT201CR */
3525 PORTCR(202, 0xe60520ca), /* PORT202CR */
3526 PORTCR(203, 0xe60520cb), /* PORT203CR */
3527 PORTCR(204, 0xe60520cc), /* PORT204CR */
3528 PORTCR(205, 0xe60520cd), /* PORT205CR */
3529 PORTCR(206, 0xe60520ce), /* PORT206CR */
3530 PORTCR(207, 0xe60520cf), /* PORT207CR */
3531 PORTCR(208, 0xe60520d0), /* PORT208CR */
3532 PORTCR(209, 0xe60520d1), /* PORT209CR */
3533
3534 PORTCR(210, 0xe60520d2), /* PORT210CR */
3535 PORTCR(211, 0xe60520d3), /* PORT211CR */
3536 PORTCR(212, 0xe60520d4), /* PORT212CR */
3537 PORTCR(213, 0xe60520d5), /* PORT213CR */
3538 PORTCR(214, 0xe60520d6), /* PORT214CR */
3539 PORTCR(215, 0xe60520d7), /* PORT215CR */
3540 PORTCR(216, 0xe60520d8), /* PORT216CR */
3541 PORTCR(217, 0xe60520d9), /* PORT217CR */
3542 PORTCR(218, 0xe60520da), /* PORT218CR */
3543 PORTCR(219, 0xe60520db), /* PORT219CR */
3544
3545 PORTCR(220, 0xe60520dc), /* PORT220CR */
3546 PORTCR(221, 0xe60520dd), /* PORT221CR */
3547 PORTCR(222, 0xe60520de), /* PORT222CR */
3548 PORTCR(223, 0xe60520df), /* PORT223CR */
3549 PORTCR(224, 0xe60530e0), /* PORT224CR */
3550 PORTCR(225, 0xe60530e1), /* PORT225CR */
3551 PORTCR(226, 0xe60530e2), /* PORT226CR */
3552 PORTCR(227, 0xe60530e3), /* PORT227CR */
3553 PORTCR(228, 0xe60530e4), /* PORT228CR */
3554 PORTCR(229, 0xe60530e5), /* PORT229CR */
3555
3556 PORTCR(230, 0xe60530e6), /* PORT230CR */
3557 PORTCR(231, 0xe60530e7), /* PORT231CR */
3558 PORTCR(232, 0xe60530e8), /* PORT232CR */
3559 PORTCR(233, 0xe60530e9), /* PORT233CR */
3560 PORTCR(234, 0xe60530ea), /* PORT234CR */
3561 PORTCR(235, 0xe60530eb), /* PORT235CR */
3562 PORTCR(236, 0xe60530ec), /* PORT236CR */
3563 PORTCR(237, 0xe60530ed), /* PORT237CR */
3564 PORTCR(238, 0xe60530ee), /* PORT238CR */
3565 PORTCR(239, 0xe60530ef), /* PORT239CR */
3566
3567 PORTCR(240, 0xe60530f0), /* PORT240CR */
3568 PORTCR(241, 0xe60530f1), /* PORT241CR */
3569 PORTCR(242, 0xe60530f2), /* PORT242CR */
3570 PORTCR(243, 0xe60530f3), /* PORT243CR */
3571 PORTCR(244, 0xe60530f4), /* PORT244CR */
3572 PORTCR(245, 0xe60530f5), /* PORT245CR */
3573 PORTCR(246, 0xe60530f6), /* PORT246CR */
3574 PORTCR(247, 0xe60530f7), /* PORT247CR */
3575 PORTCR(248, 0xe60530f8), /* PORT248CR */
3576 PORTCR(249, 0xe60530f9), /* PORT249CR */
3577
3578 PORTCR(250, 0xe60530fa), /* PORT250CR */
3579 PORTCR(251, 0xe60530fb), /* PORT251CR */
3580 PORTCR(252, 0xe60530fc), /* PORT252CR */
3581 PORTCR(253, 0xe60530fd), /* PORT253CR */
3582 PORTCR(254, 0xe60530fe), /* PORT254CR */
3583 PORTCR(255, 0xe60530ff), /* PORT255CR */
3584 PORTCR(256, 0xe6053100), /* PORT256CR */
3585 PORTCR(257, 0xe6053101), /* PORT257CR */
3586 PORTCR(258, 0xe6053102), /* PORT258CR */
3587 PORTCR(259, 0xe6053103), /* PORT259CR */
3588
3589 PORTCR(260, 0xe6053104), /* PORT260CR */
3590 PORTCR(261, 0xe6053105), /* PORT261CR */
3591 PORTCR(262, 0xe6053106), /* PORT262CR */
3592 PORTCR(263, 0xe6053107), /* PORT263CR */
3593 PORTCR(264, 0xe6053108), /* PORT264CR */
3594 PORTCR(265, 0xe6053109), /* PORT265CR */
3595 PORTCR(266, 0xe605310a), /* PORT266CR */
3596 PORTCR(267, 0xe605310b), /* PORT267CR */
3597 PORTCR(268, 0xe605310c), /* PORT268CR */
3598 PORTCR(269, 0xe605310d), /* PORT269CR */
3599
3600 PORTCR(270, 0xe605310e), /* PORT270CR */
3601 PORTCR(271, 0xe605310f), /* PORT271CR */
3602 PORTCR(272, 0xe6053110), /* PORT272CR */
3603 PORTCR(273, 0xe6053111), /* PORT273CR */
3604 PORTCR(274, 0xe6053112), /* PORT274CR */
3605 PORTCR(275, 0xe6053113), /* PORT275CR */
3606 PORTCR(276, 0xe6053114), /* PORT276CR */
3607 PORTCR(277, 0xe6053115), /* PORT277CR */
3608 PORTCR(278, 0xe6053116), /* PORT278CR */
3609 PORTCR(279, 0xe6053117), /* PORT279CR */
3610
3611 PORTCR(280, 0xe6053118), /* PORT280CR */
3612 PORTCR(281, 0xe6053119), /* PORT281CR */
3613 PORTCR(282, 0xe605311a), /* PORT282CR */
3614
3615 PORTCR(288, 0xe6052120), /* PORT288CR */
3616 PORTCR(289, 0xe6052121), /* PORT289CR */
3617
3618 PORTCR(290, 0xe6052122), /* PORT290CR */
3619 PORTCR(291, 0xe6052123), /* PORT291CR */
3620 PORTCR(292, 0xe6052124), /* PORT292CR */
3621 PORTCR(293, 0xe6052125), /* PORT293CR */
3622 PORTCR(294, 0xe6052126), /* PORT294CR */
3623 PORTCR(295, 0xe6052127), /* PORT295CR */
3624 PORTCR(296, 0xe6052128), /* PORT296CR */
3625 PORTCR(297, 0xe6052129), /* PORT297CR */
3626 PORTCR(298, 0xe605212a), /* PORT298CR */
3627 PORTCR(299, 0xe605212b), /* PORT299CR */
3628
3629 PORTCR(300, 0xe605212c), /* PORT300CR */
3630 PORTCR(301, 0xe605212d), /* PORT301CR */
3631 PORTCR(302, 0xe605212e), /* PORT302CR */
3632 PORTCR(303, 0xe605212f), /* PORT303CR */
3633 PORTCR(304, 0xe6052130), /* PORT304CR */
3634 PORTCR(305, 0xe6052131), /* PORT305CR */
3635 PORTCR(306, 0xe6052132), /* PORT306CR */
3636 PORTCR(307, 0xe6052133), /* PORT307CR */
3637 PORTCR(308, 0xe6052134), /* PORT308CR */
3638 PORTCR(309, 0xe6052135), /* PORT309CR */
3639
3640 { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1) {
3641 0, 0,
3642 0, 0,
3643 0, 0,
3644 0, 0,
3645 0, 0,
3646 0, 0,
3647 0, 0,
3648 0, 0,
3649 0, 0,
3650 0, 0,
3651 0, 0,
3652 0, 0,
3653 MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
3654 MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
3655 MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
3656 MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
3657 0, 0,
3658 MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
3659 MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
3660 MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
3661 MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
3662 MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
3663 MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
3664 MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
3665 MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
3666 MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
3667 MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
3668 MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
3669 MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
3670 MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
3671 MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
3672 MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
3673 }
3674 },
3675 { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
3676 0, 0,
3677 0, 0,
3678 0, 0,
3679 MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
3680 0, 0,
3681 0, 0,
3682 0, 0,
3683 0, 0,
3684 0, 0,
3685 0, 0,
3686 0, 0,
3687 0, 0,
3688 0, 0,
3689 0, 0,
3690 0, 0,
3691 0, 0,
3692 MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
3693 0, 0,
3694 0, 0,
3695 0, 0,
3696 MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
3697 0, 0,
3698 MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
3699 0, 0,
3700 0, 0,
3701 MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
3702 0, 0,
3703 0, 0,
3704 0, 0,
3705 MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
3706 0, 0,
3707 0, 0,
3708 }
3709 },
3710 { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
3711 0, 0,
3712 0, 0,
3713 MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
3714 0, 0,
3715 MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
3716 MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
3717 0, 0,
3718 0, 0,
3719 0, 0,
3720 MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
3721 MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
3722 MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
3723 MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
3724 0, 0,
3725 0, 0,
3726 0, 0,
3727 MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
3728 0, 0,
3729 MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
3730 MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
3731 MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
3732 MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
3733 MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
3734 MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
3735 MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
3736 0, 0,
3737 0, 0,
3738 MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
3739 0, 0,
3740 0, 0,
3741 MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
3742 0, 0,
3743 }
3744 },
3745 { },
3746 };
3747
3748 static const struct pinmux_data_reg pinmux_data_regs[] = {
3749 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
3750 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
3751 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
3752 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
3753 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
3754 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
3755 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
3756 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
3757 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
3758 },
3759 { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
3760 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
3761 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
3762 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
3763 PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
3764 PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
3765 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
3766 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
3767 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
3768 },
3769 { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32) {
3770 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
3771 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
3772 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
3773 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
3774 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
3775 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
3776 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
3777 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
3778 },
3779 { PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32) {
3780 0, 0, 0, 0,
3781 0, 0, 0, 0,
3782 0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
3783 PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
3784 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
3785 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
3786 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
3787 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
3788 },
3789 { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32) {
3790 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
3791 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
3792 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
3793 PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
3794 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
3795 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
3796 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
3797 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
3798 },
3799 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32) {
3800 0, 0, 0, 0,
3801 0, 0, 0, 0,
3802 0, 0, 0, 0,
3803 0, 0, 0, 0,
3804 0, 0, 0, 0,
3805 0, 0, 0, 0,
3806 0, 0, 0, PORT164_DATA,
3807 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
3808 },
3809 { PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32) {
3810 PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
3811 PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
3812 PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
3813 PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
3814 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
3815 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
3816 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
3817 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
3818 },
3819 { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) {
3820 PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
3821 PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
3822 PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
3823 PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
3824 PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
3825 PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
3826 PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
3827 PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
3828 },
3829 { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) {
3830 0, 0, 0, 0,
3831 0, PORT282_DATA, PORT281_DATA, PORT280_DATA,
3832 PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
3833 PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
3834 PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
3835 PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
3836 PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
3837 PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
3838 },
3839 { PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32) {
3840 0, 0, 0, 0,
3841 0, 0, 0, 0,
3842 0, 0, PORT309_DATA, PORT308_DATA,
3843 PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
3844 PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
3845 PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
3846 PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
3847 PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA }
3848 },
3849 { },
3850 };
3851
3852 /* External IRQ pins mapped at IRQPIN_BASE */
3853 #define EXT_IRQ16L(n) irq_pin(n)
3854 #define EXT_IRQ16H(n) irq_pin(n)
3855
3856 static const struct pinmux_irq pinmux_irqs[] = {
3857 PINMUX_IRQ(EXT_IRQ16H(19), 9),
3858 PINMUX_IRQ(EXT_IRQ16L(1), 10),
3859 PINMUX_IRQ(EXT_IRQ16L(0), 11),
3860 PINMUX_IRQ(EXT_IRQ16H(18), 13),
3861 PINMUX_IRQ(EXT_IRQ16H(20), 14),
3862 PINMUX_IRQ(EXT_IRQ16H(21), 15),
3863 PINMUX_IRQ(EXT_IRQ16H(31), 26),
3864 PINMUX_IRQ(EXT_IRQ16H(30), 27),
3865 PINMUX_IRQ(EXT_IRQ16H(29), 28),
3866 PINMUX_IRQ(EXT_IRQ16H(22), 40),
3867 PINMUX_IRQ(EXT_IRQ16H(23), 53),
3868 PINMUX_IRQ(EXT_IRQ16L(10), 54),
3869 PINMUX_IRQ(EXT_IRQ16L(9), 56),
3870 PINMUX_IRQ(EXT_IRQ16H(26), 115),
3871 PINMUX_IRQ(EXT_IRQ16H(27), 116),
3872 PINMUX_IRQ(EXT_IRQ16H(28), 117),
3873 PINMUX_IRQ(EXT_IRQ16H(24), 118),
3874 PINMUX_IRQ(EXT_IRQ16L(6), 147),
3875 PINMUX_IRQ(EXT_IRQ16L(2), 149),
3876 PINMUX_IRQ(EXT_IRQ16L(7), 150),
3877 PINMUX_IRQ(EXT_IRQ16L(12), 156),
3878 PINMUX_IRQ(EXT_IRQ16L(4), 159),
3879 PINMUX_IRQ(EXT_IRQ16H(25), 164),
3880 PINMUX_IRQ(EXT_IRQ16L(8), 223),
3881 PINMUX_IRQ(EXT_IRQ16L(3), 224),
3882 PINMUX_IRQ(EXT_IRQ16L(5), 227),
3883 PINMUX_IRQ(EXT_IRQ16H(17), 234),
3884 PINMUX_IRQ(EXT_IRQ16L(11), 238),
3885 PINMUX_IRQ(EXT_IRQ16L(13), 239),
3886 PINMUX_IRQ(EXT_IRQ16H(16), 249),
3887 PINMUX_IRQ(EXT_IRQ16L(14), 251),
3888 PINMUX_IRQ(EXT_IRQ16L(9), 308),
3889 };
3890
3891 #define PORTnCR_PULMD_OFF (0 << 6)
3892 #define PORTnCR_PULMD_DOWN (2 << 6)
3893 #define PORTnCR_PULMD_UP (3 << 6)
3894 #define PORTnCR_PULMD_MASK (3 << 6)
3895
3896 static const unsigned int sh73a0_portcr_offsets[] = {
3897 0x00000000, 0x00001000, 0x00001000, 0x00002000, 0x00002000,
3898 0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000,
3899 };
3900
sh73a0_pinmux_get_bias(struct sh_pfc * pfc,unsigned int pin)3901 static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
3902 {
3903 void __iomem *addr = pfc->window->virt
3904 + sh73a0_portcr_offsets[pin >> 5] + pin;
3905 u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
3906
3907 switch (value) {
3908 case PORTnCR_PULMD_UP:
3909 return PIN_CONFIG_BIAS_PULL_UP;
3910 case PORTnCR_PULMD_DOWN:
3911 return PIN_CONFIG_BIAS_PULL_DOWN;
3912 case PORTnCR_PULMD_OFF:
3913 default:
3914 return PIN_CONFIG_BIAS_DISABLE;
3915 }
3916 }
3917
sh73a0_pinmux_set_bias(struct sh_pfc * pfc,unsigned int pin,unsigned int bias)3918 static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3919 unsigned int bias)
3920 {
3921 void __iomem *addr = pfc->window->virt
3922 + sh73a0_portcr_offsets[pin >> 5] + pin;
3923 u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
3924
3925 switch (bias) {
3926 case PIN_CONFIG_BIAS_PULL_UP:
3927 value |= PORTnCR_PULMD_UP;
3928 break;
3929 case PIN_CONFIG_BIAS_PULL_DOWN:
3930 value |= PORTnCR_PULMD_DOWN;
3931 break;
3932 }
3933
3934 iowrite8(value, addr);
3935 }
3936
3937 static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = {
3938 .get_bias = sh73a0_pinmux_get_bias,
3939 .set_bias = sh73a0_pinmux_set_bias,
3940 };
3941
3942 const struct sh_pfc_soc_info sh73a0_pinmux_info = {
3943 .name = "sh73a0_pfc",
3944 .ops = &sh73a0_pinmux_ops,
3945
3946 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
3947 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
3948 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3949
3950 .pins = pinmux_pins,
3951 .nr_pins = ARRAY_SIZE(pinmux_pins),
3952 .ranges = pinmux_ranges,
3953 .nr_ranges = ARRAY_SIZE(pinmux_ranges),
3954 .groups = pinmux_groups,
3955 .nr_groups = ARRAY_SIZE(pinmux_groups),
3956 .functions = pinmux_functions,
3957 .nr_functions = ARRAY_SIZE(pinmux_functions),
3958
3959 .func_gpios = pinmux_func_gpios,
3960 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
3961
3962 .cfg_regs = pinmux_config_regs,
3963 .data_regs = pinmux_data_regs,
3964
3965 .gpio_data = pinmux_data,
3966 .gpio_data_size = ARRAY_SIZE(pinmux_data),
3967
3968 .gpio_irq = pinmux_irqs,
3969 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
3970 };
3971