1 /* 2 * Copyright (c) 2000-2012 LSI Corporation. 3 * 4 * 5 * Name: mpi2.h 6 * Title: MPI Message independent structures and definitions 7 * including System Interface Register Set and 8 * scatter/gather formats. 9 * Creation Date: June 21, 2006 10 * 11 * mpi2.h Version: 02.00.25 12 * 13 * Version History 14 * --------------- 15 * 16 * Date Version Description 17 * -------- -------- ------------------------------------------------------ 18 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 19 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT. 20 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT. 21 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT. 22 * Moved ReplyPostHostIndex register to offset 0x6C of the 23 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for 24 * MPI2_REPLY_POST_HOST_INDEX_OFFSET. 25 * Added union of request descriptors. 26 * Added union of reply descriptors. 27 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT. 28 * Added define for MPI2_VERSION_02_00. 29 * Fixed the size of the FunctionDependent5 field in the 30 * MPI2_DEFAULT_REPLY structure. 31 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT. 32 * Removed the MPI-defined Fault Codes and extended the 33 * product specific codes up to 0xEFFF. 34 * Added a sixth key value for the WriteSequence register 35 * and changed the flush value to 0x0. 36 * Added message function codes for Diagnostic Buffer Post 37 * and Diagnsotic Release. 38 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED 39 * Moved MPI2_VERSION_UNION from mpi2_ioc.h. 40 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT. 41 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT. 42 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT. 43 * Added #defines for marking a reply descriptor as unused. 44 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT. 45 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT. 46 * Moved LUN field defines from mpi2_init.h. 47 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT. 48 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT. 49 * In all request and reply descriptors, replaced VF_ID 50 * field with MSIxIndex field. 51 * Removed DevHandle field from 52 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those 53 * bytes reserved. 54 * Added RAID Accelerator functionality. 55 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT. 56 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT. 57 * Added MSI-x index mask and shift for Reply Post Host 58 * Index register. 59 * Added function code for Host Based Discovery Action. 60 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT. 61 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL. 62 * Added defines for product-specific range of message 63 * function codes, 0xF0 to 0xFF. 64 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT. 65 * Added alternative defines for the SGE Direction bit. 66 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT. 67 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT. 68 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define. 69 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT. 70 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE. 71 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT. 72 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT. 73 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT. 74 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT. 75 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT. 76 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT. 77 * Added Hard Reset delay timings. 78 * -------------------------------------------------------------------------- 79 */ 80 81 #ifndef MPI2_H 82 #define MPI2_H 83 84 85 /***************************************************************************** 86 * 87 * MPI Version Definitions 88 * 89 *****************************************************************************/ 90 91 #define MPI2_VERSION_MAJOR (0x02) 92 #define MPI2_VERSION_MINOR (0x00) 93 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 94 #define MPI2_VERSION_MAJOR_SHIFT (8) 95 #define MPI2_VERSION_MINOR_MASK (0x00FF) 96 #define MPI2_VERSION_MINOR_SHIFT (0) 97 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 98 MPI2_VERSION_MINOR) 99 100 #define MPI2_VERSION_02_00 (0x0200) 101 102 /* versioning for this MPI header set */ 103 #define MPI2_HEADER_VERSION_UNIT (0x19) 104 #define MPI2_HEADER_VERSION_DEV (0x00) 105 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 106 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 107 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 108 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 109 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) 110 111 112 /***************************************************************************** 113 * 114 * IOC State Definitions 115 * 116 *****************************************************************************/ 117 118 #define MPI2_IOC_STATE_RESET (0x00000000) 119 #define MPI2_IOC_STATE_READY (0x10000000) 120 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000) 121 #define MPI2_IOC_STATE_FAULT (0x40000000) 122 123 #define MPI2_IOC_STATE_MASK (0xF0000000) 124 #define MPI2_IOC_STATE_SHIFT (28) 125 126 /* Fault state range for prodcut specific codes */ 127 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000) 128 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF) 129 130 131 /***************************************************************************** 132 * 133 * System Interface Register Definitions 134 * 135 *****************************************************************************/ 136 137 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS 138 { 139 U32 Doorbell; /* 0x00 */ 140 U32 WriteSequence; /* 0x04 */ 141 U32 HostDiagnostic; /* 0x08 */ 142 U32 Reserved1; /* 0x0C */ 143 U32 DiagRWData; /* 0x10 */ 144 U32 DiagRWAddressLow; /* 0x14 */ 145 U32 DiagRWAddressHigh; /* 0x18 */ 146 U32 Reserved2[5]; /* 0x1C */ 147 U32 HostInterruptStatus; /* 0x30 */ 148 U32 HostInterruptMask; /* 0x34 */ 149 U32 DCRData; /* 0x38 */ 150 U32 DCRAddress; /* 0x3C */ 151 U32 Reserved3[2]; /* 0x40 */ 152 U32 ReplyFreeHostIndex; /* 0x48 */ 153 U32 Reserved4[8]; /* 0x4C */ 154 U32 ReplyPostHostIndex; /* 0x6C */ 155 U32 Reserved5; /* 0x70 */ 156 U32 HCBSize; /* 0x74 */ 157 U32 HCBAddressLow; /* 0x78 */ 158 U32 HCBAddressHigh; /* 0x7C */ 159 U32 Reserved6[16]; /* 0x80 */ 160 U32 RequestDescriptorPostLow; /* 0xC0 */ 161 U32 RequestDescriptorPostHigh; /* 0xC4 */ 162 U32 Reserved7[14]; /* 0xC8 */ 163 } MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS, 164 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t; 165 166 /* 167 * Defines for working with the Doorbell register. 168 */ 169 #define MPI2_DOORBELL_OFFSET (0x00000000) 170 171 /* IOC --> System values */ 172 #define MPI2_DOORBELL_USED (0x08000000) 173 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000) 174 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24) 175 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF) 176 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF) 177 178 /* System --> IOC values */ 179 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000) 180 #define MPI2_DOORBELL_FUNCTION_SHIFT (24) 181 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000) 182 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16) 183 184 185 /* 186 * Defines for the WriteSequence register 187 */ 188 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 189 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F) 190 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 191 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 192 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 193 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 194 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 195 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 196 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 197 198 /* 199 * Defines for the HostDiagnostic register 200 */ 201 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008) 202 203 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800) 204 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000) 205 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800) 206 207 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) 208 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200) 209 #define MPI2_DIAG_HCB_MODE (0x00000100) 210 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080) 211 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040) 212 #define MPI2_DIAG_RESET_HISTORY (0x00000020) 213 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010) 214 #define MPI2_DIAG_RESET_ADAPTER (0x00000004) 215 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002) 216 217 /* 218 * Offsets for DiagRWData and address 219 */ 220 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010) 221 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014) 222 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018) 223 224 /* 225 * Defines for the HostInterruptStatus register 226 */ 227 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030) 228 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000) 229 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS 230 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000) 231 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008) 232 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001) 233 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS 234 235 /* 236 * Defines for the HostInterruptMask register 237 */ 238 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034) 239 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000) 240 #define MPI2_HIM_REPLY_INT_MASK (0x00000008) 241 #define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK 242 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001) 243 #define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK 244 245 /* 246 * Offsets for DCRData and address 247 */ 248 #define MPI2_DCR_DATA_OFFSET (0x00000038) 249 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C) 250 251 /* 252 * Offset for the Reply Free Queue 253 */ 254 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048) 255 256 /* 257 * Defines for the Reply Descriptor Post Queue 258 */ 259 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 260 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF) 261 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000) 262 #define MPI2_RPHI_MSIX_INDEX_SHIFT (24) 263 264 /* 265 * Defines for the HCBSize and address 266 */ 267 #define MPI2_HCB_SIZE_OFFSET (0x00000074) 268 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000) 269 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001) 270 271 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078) 272 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C) 273 274 /* 275 * Offsets for the Request Queue 276 */ 277 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0) 278 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4) 279 280 281 /* Hard Reset delay timings */ 282 #define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000) 283 #define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000) 284 #define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000) 285 286 /***************************************************************************** 287 * 288 * Message Descriptors 289 * 290 *****************************************************************************/ 291 292 /* Request Descriptors */ 293 294 /* Default Request Descriptor */ 295 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR 296 { 297 U8 RequestFlags; /* 0x00 */ 298 U8 MSIxIndex; /* 0x01 */ 299 U16 SMID; /* 0x02 */ 300 U16 LMID; /* 0x04 */ 301 U16 DescriptorTypeDependent; /* 0x06 */ 302 } MPI2_DEFAULT_REQUEST_DESCRIPTOR, 303 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 304 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; 305 306 /* defines for the RequestFlags field */ 307 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 308 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 309 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 310 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 311 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 312 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 313 314 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 315 316 317 /* High Priority Request Descriptor */ 318 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR 319 { 320 U8 RequestFlags; /* 0x00 */ 321 U8 MSIxIndex; /* 0x01 */ 322 U16 SMID; /* 0x02 */ 323 U16 LMID; /* 0x04 */ 324 U16 Reserved1; /* 0x06 */ 325 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 326 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 327 Mpi2HighPriorityRequestDescriptor_t, 328 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; 329 330 331 /* SCSI IO Request Descriptor */ 332 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR 333 { 334 U8 RequestFlags; /* 0x00 */ 335 U8 MSIxIndex; /* 0x01 */ 336 U16 SMID; /* 0x02 */ 337 U16 LMID; /* 0x04 */ 338 U16 DevHandle; /* 0x06 */ 339 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 340 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 341 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; 342 343 344 /* SCSI Target Request Descriptor */ 345 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR 346 { 347 U8 RequestFlags; /* 0x00 */ 348 U8 MSIxIndex; /* 0x01 */ 349 U16 SMID; /* 0x02 */ 350 U16 LMID; /* 0x04 */ 351 U16 IoIndex; /* 0x06 */ 352 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 353 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 354 Mpi2SCSITargetRequestDescriptor_t, 355 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; 356 357 358 /* RAID Accelerator Request Descriptor */ 359 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR { 360 U8 RequestFlags; /* 0x00 */ 361 U8 MSIxIndex; /* 0x01 */ 362 U16 SMID; /* 0x02 */ 363 U16 LMID; /* 0x04 */ 364 U16 Reserved; /* 0x06 */ 365 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 366 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 367 Mpi2RAIDAcceleratorRequestDescriptor_t, 368 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t; 369 370 371 /* union of Request Descriptors */ 372 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION 373 { 374 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 375 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 376 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 377 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 378 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 379 U64 Words; 380 } MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION, 381 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t; 382 383 384 /* Reply Descriptors */ 385 386 /* Default Reply Descriptor */ 387 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR 388 { 389 U8 ReplyFlags; /* 0x00 */ 390 U8 MSIxIndex; /* 0x01 */ 391 U16 DescriptorTypeDependent1; /* 0x02 */ 392 U32 DescriptorTypeDependent2; /* 0x04 */ 393 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 394 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; 395 396 /* defines for the ReplyFlags field */ 397 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 398 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 399 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 400 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 401 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 402 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 403 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 404 405 /* values for marking a reply descriptor as unused */ 406 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 407 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 408 409 /* Address Reply Descriptor */ 410 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR 411 { 412 U8 ReplyFlags; /* 0x00 */ 413 U8 MSIxIndex; /* 0x01 */ 414 U16 SMID; /* 0x02 */ 415 U32 ReplyFrameAddress; /* 0x04 */ 416 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 417 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; 418 419 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00) 420 421 422 /* SCSI IO Success Reply Descriptor */ 423 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 424 { 425 U8 ReplyFlags; /* 0x00 */ 426 U8 MSIxIndex; /* 0x01 */ 427 U16 SMID; /* 0x02 */ 428 U16 TaskTag; /* 0x04 */ 429 U16 Reserved1; /* 0x06 */ 430 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 431 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 432 Mpi2SCSIIOSuccessReplyDescriptor_t, 433 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; 434 435 436 /* TargetAssist Success Reply Descriptor */ 437 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR 438 { 439 U8 ReplyFlags; /* 0x00 */ 440 U8 MSIxIndex; /* 0x01 */ 441 U16 SMID; /* 0x02 */ 442 U8 SequenceNumber; /* 0x04 */ 443 U8 Reserved1; /* 0x05 */ 444 U16 IoIndex; /* 0x06 */ 445 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 446 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 447 Mpi2TargetAssistSuccessReplyDescriptor_t, 448 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; 449 450 451 /* Target Command Buffer Reply Descriptor */ 452 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR 453 { 454 U8 ReplyFlags; /* 0x00 */ 455 U8 MSIxIndex; /* 0x01 */ 456 U8 VP_ID; /* 0x02 */ 457 U8 Flags; /* 0x03 */ 458 U16 InitiatorDevHandle; /* 0x04 */ 459 U16 IoIndex; /* 0x06 */ 460 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 461 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 462 Mpi2TargetCommandBufferReplyDescriptor_t, 463 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; 464 465 /* defines for Flags field */ 466 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F) 467 468 469 /* RAID Accelerator Success Reply Descriptor */ 470 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR { 471 U8 ReplyFlags; /* 0x00 */ 472 U8 MSIxIndex; /* 0x01 */ 473 U16 SMID; /* 0x02 */ 474 U32 Reserved; /* 0x04 */ 475 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 476 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 477 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, 478 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 479 480 481 /* union of Reply Descriptors */ 482 typedef union _MPI2_REPLY_DESCRIPTORS_UNION 483 { 484 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 485 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 486 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 487 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 488 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 489 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 490 U64 Words; 491 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, 492 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; 493 494 495 496 /***************************************************************************** 497 * 498 * Message Functions 499 * 500 *****************************************************************************/ 501 502 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 503 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 504 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 505 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 506 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 507 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 508 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 509 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 510 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 511 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 512 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 513 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 514 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 515 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 516 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 517 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 518 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 519 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 520 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 521 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ 522 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 523 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 524 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 525 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 526 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 527 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator*/ 528 /* Host Based Discovery Action */ 529 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) 530 /* Power Management Control */ 531 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) 532 /* Send Host Message */ 533 #define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31) 534 /* beginning of product-specific range */ 535 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) 536 /* end of product-specific range */ 537 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) 538 539 540 541 542 /* Doorbell functions */ 543 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 544 #define MPI2_FUNCTION_HANDSHAKE (0x42) 545 546 547 /***************************************************************************** 548 * 549 * IOC Status Values 550 * 551 *****************************************************************************/ 552 553 /* mask for IOCStatus status value */ 554 #define MPI2_IOCSTATUS_MASK (0x7FFF) 555 556 /**************************************************************************** 557 * Common IOCStatus values for all replies 558 ****************************************************************************/ 559 560 #define MPI2_IOCSTATUS_SUCCESS (0x0000) 561 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001) 562 #define MPI2_IOCSTATUS_BUSY (0x0002) 563 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003) 564 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004) 565 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005) 566 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 567 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007) 568 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008) 569 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) 570 571 /**************************************************************************** 572 * Config IOCStatus values 573 ****************************************************************************/ 574 575 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 576 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 577 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 578 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 579 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 580 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 581 582 /**************************************************************************** 583 * SCSI IO Reply 584 ****************************************************************************/ 585 586 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 587 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 588 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 589 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 590 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 591 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 592 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 593 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 594 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 595 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) 596 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) 597 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) 598 599 /**************************************************************************** 600 * For use by SCSI Initiator and SCSI Target end-to-end data protection 601 ****************************************************************************/ 602 603 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D) 604 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E) 605 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F) 606 607 /**************************************************************************** 608 * SCSI Target values 609 ****************************************************************************/ 610 611 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 612 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063) 613 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 614 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 615 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) 616 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D) 617 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E) 618 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F) 619 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 620 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 621 622 /**************************************************************************** 623 * Serial Attached SCSI values 624 ****************************************************************************/ 625 626 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 627 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 628 629 /**************************************************************************** 630 * Diagnostic Buffer Post / Diagnostic Release values 631 ****************************************************************************/ 632 633 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0) 634 635 /**************************************************************************** 636 * RAID Accelerator values 637 ****************************************************************************/ 638 639 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0) 640 641 /**************************************************************************** 642 * IOCStatus flag to indicate that log info is available 643 ****************************************************************************/ 644 645 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000) 646 647 /**************************************************************************** 648 * IOCLogInfo Types 649 ****************************************************************************/ 650 651 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000) 652 #define MPI2_IOCLOGINFO_TYPE_SHIFT (28) 653 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0) 654 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1) 655 #define MPI2_IOCLOGINFO_TYPE_FC (0x2) 656 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3) 657 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4) 658 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) 659 660 661 /***************************************************************************** 662 * 663 * Standard Message Structures 664 * 665 *****************************************************************************/ 666 667 /**************************************************************************** 668 * Request Message Header for all request messages 669 ****************************************************************************/ 670 671 typedef struct _MPI2_REQUEST_HEADER 672 { 673 U16 FunctionDependent1; /* 0x00 */ 674 U8 ChainOffset; /* 0x02 */ 675 U8 Function; /* 0x03 */ 676 U16 FunctionDependent2; /* 0x04 */ 677 U8 FunctionDependent3; /* 0x06 */ 678 U8 MsgFlags; /* 0x07 */ 679 U8 VP_ID; /* 0x08 */ 680 U8 VF_ID; /* 0x09 */ 681 U16 Reserved1; /* 0x0A */ 682 } MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER, 683 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t; 684 685 686 /**************************************************************************** 687 * Default Reply 688 ****************************************************************************/ 689 690 typedef struct _MPI2_DEFAULT_REPLY 691 { 692 U16 FunctionDependent1; /* 0x00 */ 693 U8 MsgLength; /* 0x02 */ 694 U8 Function; /* 0x03 */ 695 U16 FunctionDependent2; /* 0x04 */ 696 U8 FunctionDependent3; /* 0x06 */ 697 U8 MsgFlags; /* 0x07 */ 698 U8 VP_ID; /* 0x08 */ 699 U8 VF_ID; /* 0x09 */ 700 U16 Reserved1; /* 0x0A */ 701 U16 FunctionDependent5; /* 0x0C */ 702 U16 IOCStatus; /* 0x0E */ 703 U32 IOCLogInfo; /* 0x10 */ 704 } MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY, 705 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t; 706 707 708 /* common version structure/union used in messages and configuration pages */ 709 710 typedef struct _MPI2_VERSION_STRUCT 711 { 712 U8 Dev; /* 0x00 */ 713 U8 Unit; /* 0x01 */ 714 U8 Minor; /* 0x02 */ 715 U8 Major; /* 0x03 */ 716 } MPI2_VERSION_STRUCT; 717 718 typedef union _MPI2_VERSION_UNION 719 { 720 MPI2_VERSION_STRUCT Struct; 721 U32 Word; 722 } MPI2_VERSION_UNION; 723 724 725 /* LUN field defines, common to many structures */ 726 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) 727 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) 728 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) 729 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) 730 #define MPI2_LUN_LEVEL_1_WORD (0xFF00) 731 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00) 732 733 734 /***************************************************************************** 735 * 736 * Fusion-MPT MPI Scatter Gather Elements 737 * 738 *****************************************************************************/ 739 740 /**************************************************************************** 741 * MPI Simple Element structures 742 ****************************************************************************/ 743 744 typedef struct _MPI2_SGE_SIMPLE32 745 { 746 U32 FlagsLength; 747 U32 Address; 748 } MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32, 749 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t; 750 751 typedef struct _MPI2_SGE_SIMPLE64 752 { 753 U32 FlagsLength; 754 U64 Address; 755 } MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64, 756 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t; 757 758 typedef struct _MPI2_SGE_SIMPLE_UNION 759 { 760 U32 FlagsLength; 761 union 762 { 763 U32 Address32; 764 U64 Address64; 765 } u; 766 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, 767 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; 768 769 770 /**************************************************************************** 771 * MPI Chain Element structures 772 ****************************************************************************/ 773 774 typedef struct _MPI2_SGE_CHAIN32 775 { 776 U16 Length; 777 U8 NextChainOffset; 778 U8 Flags; 779 U32 Address; 780 } MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32, 781 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t; 782 783 typedef struct _MPI2_SGE_CHAIN64 784 { 785 U16 Length; 786 U8 NextChainOffset; 787 U8 Flags; 788 U64 Address; 789 } MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64, 790 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t; 791 792 typedef struct _MPI2_SGE_CHAIN_UNION 793 { 794 U16 Length; 795 U8 NextChainOffset; 796 U8 Flags; 797 union 798 { 799 U32 Address32; 800 U64 Address64; 801 } u; 802 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, 803 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; 804 805 806 /**************************************************************************** 807 * MPI Transaction Context Element structures 808 ****************************************************************************/ 809 810 typedef struct _MPI2_SGE_TRANSACTION32 811 { 812 U8 Reserved; 813 U8 ContextSize; 814 U8 DetailsLength; 815 U8 Flags; 816 U32 TransactionContext[1]; 817 U32 TransactionDetails[1]; 818 } MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32, 819 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t; 820 821 typedef struct _MPI2_SGE_TRANSACTION64 822 { 823 U8 Reserved; 824 U8 ContextSize; 825 U8 DetailsLength; 826 U8 Flags; 827 U32 TransactionContext[2]; 828 U32 TransactionDetails[1]; 829 } MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64, 830 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t; 831 832 typedef struct _MPI2_SGE_TRANSACTION96 833 { 834 U8 Reserved; 835 U8 ContextSize; 836 U8 DetailsLength; 837 U8 Flags; 838 U32 TransactionContext[3]; 839 U32 TransactionDetails[1]; 840 } MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96, 841 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t; 842 843 typedef struct _MPI2_SGE_TRANSACTION128 844 { 845 U8 Reserved; 846 U8 ContextSize; 847 U8 DetailsLength; 848 U8 Flags; 849 U32 TransactionContext[4]; 850 U32 TransactionDetails[1]; 851 } MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128, 852 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128; 853 854 typedef struct _MPI2_SGE_TRANSACTION_UNION 855 { 856 U8 Reserved; 857 U8 ContextSize; 858 U8 DetailsLength; 859 U8 Flags; 860 union 861 { 862 U32 TransactionContext32[1]; 863 U32 TransactionContext64[2]; 864 U32 TransactionContext96[3]; 865 U32 TransactionContext128[4]; 866 } u; 867 U32 TransactionDetails[1]; 868 } MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION, 869 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t; 870 871 872 /**************************************************************************** 873 * MPI SGE union for IO SGL's 874 ****************************************************************************/ 875 876 typedef struct _MPI2_MPI_SGE_IO_UNION 877 { 878 union 879 { 880 MPI2_SGE_SIMPLE_UNION Simple; 881 MPI2_SGE_CHAIN_UNION Chain; 882 } u; 883 } MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION, 884 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t; 885 886 887 /**************************************************************************** 888 * MPI SGE union for SGL's with Simple and Transaction elements 889 ****************************************************************************/ 890 891 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION 892 { 893 union 894 { 895 MPI2_SGE_SIMPLE_UNION Simple; 896 MPI2_SGE_TRANSACTION_UNION Transaction; 897 } u; 898 } MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION, 899 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t; 900 901 902 /**************************************************************************** 903 * All MPI SGE types union 904 ****************************************************************************/ 905 906 typedef struct _MPI2_MPI_SGE_UNION 907 { 908 union 909 { 910 MPI2_SGE_SIMPLE_UNION Simple; 911 MPI2_SGE_CHAIN_UNION Chain; 912 MPI2_SGE_TRANSACTION_UNION Transaction; 913 } u; 914 } MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION, 915 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t; 916 917 918 /**************************************************************************** 919 * MPI SGE field definition and masks 920 ****************************************************************************/ 921 922 /* Flags field bit definitions */ 923 924 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80) 925 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40) 926 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30) 927 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08) 928 #define MPI2_SGE_FLAGS_DIRECTION (0x04) 929 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02) 930 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01) 931 932 #define MPI2_SGE_FLAGS_SHIFT (24) 933 934 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF) 935 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF) 936 937 /* Element Type */ 938 939 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) 940 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10) 941 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30) 942 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30) 943 944 /* Address location */ 945 946 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00) 947 948 /* Direction */ 949 950 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00) 951 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04) 952 953 #define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST) 954 #define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC) 955 956 /* Address Size */ 957 958 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 959 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 960 961 /* Context Size */ 962 963 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00) 964 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02) 965 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04) 966 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06) 967 968 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000) 969 #define MPI2_SGE_CHAIN_OFFSET_SHIFT (16) 970 971 /**************************************************************************** 972 * MPI SGE operation Macros 973 ****************************************************************************/ 974 975 /* SIMPLE FlagsLength manipulations... */ 976 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT) 977 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT) 978 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK) 979 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK) 980 981 #define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l)) 982 983 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength) 984 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength) 985 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l) 986 987 /* CAUTION - The following are READ-MODIFY-WRITE! */ 988 #define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f) 989 #define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l) 990 991 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT) 992 993 994 /***************************************************************************** 995 * 996 * Fusion-MPT IEEE Scatter Gather Elements 997 * 998 *****************************************************************************/ 999 1000 /**************************************************************************** 1001 * IEEE Simple Element structures 1002 ****************************************************************************/ 1003 1004 typedef struct _MPI2_IEEE_SGE_SIMPLE32 1005 { 1006 U32 Address; 1007 U32 FlagsLength; 1008 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, 1009 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; 1010 1011 typedef struct _MPI2_IEEE_SGE_SIMPLE64 1012 { 1013 U64 Address; 1014 U32 Length; 1015 U16 Reserved1; 1016 U8 Reserved2; 1017 U8 Flags; 1018 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, 1019 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; 1020 1021 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION 1022 { 1023 MPI2_IEEE_SGE_SIMPLE32 Simple32; 1024 MPI2_IEEE_SGE_SIMPLE64 Simple64; 1025 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 1026 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; 1027 1028 1029 /**************************************************************************** 1030 * IEEE Chain Element structures 1031 ****************************************************************************/ 1032 1033 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 1034 1035 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 1036 1037 typedef union _MPI2_IEEE_SGE_CHAIN_UNION 1038 { 1039 MPI2_IEEE_SGE_CHAIN32 Chain32; 1040 MPI2_IEEE_SGE_CHAIN64 Chain64; 1041 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, 1042 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; 1043 1044 1045 /**************************************************************************** 1046 * All IEEE SGE types union 1047 ****************************************************************************/ 1048 1049 typedef struct _MPI2_IEEE_SGE_UNION 1050 { 1051 union 1052 { 1053 MPI2_IEEE_SGE_SIMPLE_UNION Simple; 1054 MPI2_IEEE_SGE_CHAIN_UNION Chain; 1055 } u; 1056 } MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION, 1057 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t; 1058 1059 1060 /**************************************************************************** 1061 * IEEE SGE field definitions and masks 1062 ****************************************************************************/ 1063 1064 /* Flags field bit definitions */ 1065 1066 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1067 1068 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1069 1070 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1071 1072 /* Element Type */ 1073 1074 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1075 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1076 1077 /* Data Location Address Space */ 1078 1079 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1080 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1081 /* IEEE Simple Element only */ 1082 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1083 /* IEEE Simple Element only */ 1084 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1085 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1086 /* IEEE Simple Element only */ 1087 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03) 1088 /* IEEE Chain Element only */ 1089 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR \ 1090 (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) /* typo in name */ 1091 1092 /**************************************************************************** 1093 * IEEE SGE operation Macros 1094 ****************************************************************************/ 1095 1096 /* SIMPLE FlagsLength manipulations... */ 1097 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT) 1098 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT) 1099 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK) 1100 1101 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l)) 1102 1103 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength) 1104 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength) 1105 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l) 1106 1107 /* CAUTION - The following are READ-MODIFY-WRITE! */ 1108 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f) 1109 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l) 1110 1111 1112 1113 1114 /***************************************************************************** 1115 * 1116 * Fusion-MPT MPI/IEEE Scatter Gather Unions 1117 * 1118 *****************************************************************************/ 1119 1120 typedef union _MPI2_SIMPLE_SGE_UNION 1121 { 1122 MPI2_SGE_SIMPLE_UNION MpiSimple; 1123 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1124 } MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION, 1125 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t; 1126 1127 1128 typedef union _MPI2_SGE_IO_UNION 1129 { 1130 MPI2_SGE_SIMPLE_UNION MpiSimple; 1131 MPI2_SGE_CHAIN_UNION MpiChain; 1132 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1133 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1134 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, 1135 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; 1136 1137 1138 /**************************************************************************** 1139 * 1140 * Values for SGLFlags field, used in many request messages with an SGL 1141 * 1142 ****************************************************************************/ 1143 1144 /* values for MPI SGL Data Location Address Space subfield */ 1145 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C) 1146 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00) 1147 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04) 1148 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) 1149 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) 1150 /* values for SGL Type subfield */ 1151 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03) 1152 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00) 1153 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) 1154 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02) 1155 1156 1157 #endif 1158 1159