1 /*
2 module/mite.h
3 Hardware driver for NI Mite PCI interface chip
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1999 David A. Schleef <ds@schleef.org>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21
22 */
23
24 #ifndef _MITE_H_
25 #define _MITE_H_
26
27 #include <linux/pci.h>
28 #include <linux/log2.h>
29 #include "../comedidev.h"
30
31 /* #define DEBUG_MITE */
32 #define PCIMIO_COMPAT
33
34 #ifdef DEBUG_MITE
35 #define MDPRINTK(format, args...) pr_debug(format , ## args)
36 #else
37 #define MDPRINTK(format, args...) do { } while (0)
38 #endif
39
40 #define MAX_MITE_DMA_CHANNELS 8
41
42 struct mite_dma_descriptor {
43 u32 count;
44 u32 addr;
45 u32 next;
46 u32 dar;
47 };
48
49 struct mite_dma_descriptor_ring {
50 struct device *hw_dev;
51 unsigned int n_links;
52 struct mite_dma_descriptor *descriptors;
53 dma_addr_t descriptors_dma_addr;
54 };
55
56 struct mite_channel {
57 struct mite_struct *mite;
58 unsigned channel;
59 int dir;
60 int done;
61 struct mite_dma_descriptor_ring *ring;
62 };
63
64 struct mite_struct {
65 struct pci_dev *pcidev;
66 resource_size_t mite_phys_addr;
67 void __iomem *mite_io_addr;
68 resource_size_t daq_phys_addr;
69 void __iomem *daq_io_addr;
70 struct mite_channel channels[MAX_MITE_DMA_CHANNELS];
71 short channel_allocated[MAX_MITE_DMA_CHANNELS];
72 int num_channels;
73 unsigned fifo_size;
74 spinlock_t lock;
75 };
76
77 struct mite_struct *mite_alloc(struct pci_dev *pcidev);
78
mite_free(struct mite_struct * mite)79 static inline void mite_free(struct mite_struct *mite)
80 {
81 kfree(mite);
82 }
83
mite_irq(struct mite_struct * mite)84 static inline unsigned int mite_irq(struct mite_struct *mite)
85 {
86 return mite->pcidev->irq;
87 };
88
mite_device_id(struct mite_struct * mite)89 static inline unsigned int mite_device_id(struct mite_struct *mite)
90 {
91 return mite->pcidev->device;
92 };
93
94 int mite_setup(struct mite_struct *mite);
95 int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1);
96 void mite_unsetup(struct mite_struct *mite);
97 struct mite_dma_descriptor_ring *mite_alloc_ring(struct mite_struct *mite);
98 void mite_free_ring(struct mite_dma_descriptor_ring *ring);
99 struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
100 struct
101 mite_dma_descriptor_ring
102 *ring, unsigned min_channel,
103 unsigned max_channel);
mite_request_channel(struct mite_struct * mite,struct mite_dma_descriptor_ring * ring)104 static inline struct mite_channel *mite_request_channel(struct mite_struct
105 *mite,
106 struct
107 mite_dma_descriptor_ring
108 *ring)
109 {
110 return mite_request_channel_in_range(mite, ring, 0,
111 mite->num_channels - 1);
112 }
113
114 void mite_release_channel(struct mite_channel *mite_chan);
115
116 unsigned mite_dma_tcr(struct mite_channel *mite_chan);
117 void mite_dma_arm(struct mite_channel *mite_chan);
118 void mite_dma_disarm(struct mite_channel *mite_chan);
119 int mite_sync_input_dma(struct mite_channel *mite_chan,
120 struct comedi_async *async);
121 int mite_sync_output_dma(struct mite_channel *mite_chan,
122 struct comedi_async *async);
123 u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan);
124 u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan);
125 u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan);
126 u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan);
127 u32 mite_bytes_in_transit(struct mite_channel *mite_chan);
128 unsigned mite_get_status(struct mite_channel *mite_chan);
129 int mite_done(struct mite_channel *mite_chan);
130
131 void mite_prep_dma(struct mite_channel *mite_chan,
132 unsigned int num_device_bits, unsigned int num_memory_bits);
133 int mite_buf_change(struct mite_dma_descriptor_ring *ring,
134 struct comedi_async *async);
135
136 #ifdef DEBUG_MITE
137 void mite_print_chsr(unsigned int chsr);
138 void mite_dump_regs(struct mite_channel *mite_chan);
139 #endif
140
CHAN_OFFSET(int channel)141 static inline int CHAN_OFFSET(int channel)
142 {
143 return 0x500 + 0x100 * channel;
144 };
145
146 enum mite_registers {
147 /* The bits 0x90180700 in MITE_UNKNOWN_DMA_BURST_REG can be
148 written and read back. The bits 0x1f always read as 1.
149 The rest always read as zero. */
150 MITE_UNKNOWN_DMA_BURST_REG = 0x28,
151 MITE_IODWBSR = 0xc0, /* IO Device Window Base Size Register */
152 MITE_IODWBSR_1 = 0xc4, /* IO Device Window Base Size Register 1 */
153 MITE_IODWCR_1 = 0xf4,
154 MITE_PCI_CONFIG_OFFSET = 0x300,
155 MITE_CSIGR = 0x460 /* chip signature */
156 };
MITE_CHOR(int channel)157 static inline int MITE_CHOR(int channel)
158 { /* channel operation */
159 return CHAN_OFFSET(channel) + 0x0;
160 };
161
MITE_CHCR(int channel)162 static inline int MITE_CHCR(int channel)
163 { /* channel control */
164 return CHAN_OFFSET(channel) + 0x4;
165 };
166
MITE_TCR(int channel)167 static inline int MITE_TCR(int channel)
168 { /* transfer count */
169 return CHAN_OFFSET(channel) + 0x8;
170 };
171
MITE_MCR(int channel)172 static inline int MITE_MCR(int channel)
173 { /* memory configuration */
174 return CHAN_OFFSET(channel) + 0xc;
175 };
176
MITE_MAR(int channel)177 static inline int MITE_MAR(int channel)
178 { /* memory address */
179 return CHAN_OFFSET(channel) + 0x10;
180 };
181
MITE_DCR(int channel)182 static inline int MITE_DCR(int channel)
183 { /* device configuration */
184 return CHAN_OFFSET(channel) + 0x14;
185 };
186
MITE_DAR(int channel)187 static inline int MITE_DAR(int channel)
188 { /* device address */
189 return CHAN_OFFSET(channel) + 0x18;
190 };
191
MITE_LKCR(int channel)192 static inline int MITE_LKCR(int channel)
193 { /* link configuration */
194 return CHAN_OFFSET(channel) + 0x1c;
195 };
196
MITE_LKAR(int channel)197 static inline int MITE_LKAR(int channel)
198 { /* link address */
199 return CHAN_OFFSET(channel) + 0x20;
200 };
201
MITE_LLKAR(int channel)202 static inline int MITE_LLKAR(int channel)
203 { /* see mite section of tnt5002 manual */
204 return CHAN_OFFSET(channel) + 0x24;
205 };
206
MITE_BAR(int channel)207 static inline int MITE_BAR(int channel)
208 { /* base address */
209 return CHAN_OFFSET(channel) + 0x28;
210 };
211
MITE_BCR(int channel)212 static inline int MITE_BCR(int channel)
213 { /* base count */
214 return CHAN_OFFSET(channel) + 0x2c;
215 };
216
MITE_SAR(int channel)217 static inline int MITE_SAR(int channel)
218 { /* ? address */
219 return CHAN_OFFSET(channel) + 0x30;
220 };
221
MITE_WSCR(int channel)222 static inline int MITE_WSCR(int channel)
223 { /* ? */
224 return CHAN_OFFSET(channel) + 0x34;
225 };
226
MITE_WSER(int channel)227 static inline int MITE_WSER(int channel)
228 { /* ? */
229 return CHAN_OFFSET(channel) + 0x38;
230 };
231
MITE_CHSR(int channel)232 static inline int MITE_CHSR(int channel)
233 { /* channel status */
234 return CHAN_OFFSET(channel) + 0x3c;
235 };
236
MITE_FCR(int channel)237 static inline int MITE_FCR(int channel)
238 { /* fifo count */
239 return CHAN_OFFSET(channel) + 0x40;
240 };
241
242 enum MITE_IODWBSR_bits {
243 WENAB = 0x80, /* window enable */
244 };
245
MITE_IODWBSR_1_WSIZE_bits(unsigned size)246 static inline unsigned MITE_IODWBSR_1_WSIZE_bits(unsigned size)
247 {
248 unsigned order = 0;
249
250 BUG_ON(size == 0);
251 order = ilog2(size);
252 BUG_ON(order < 1);
253 return (order - 1) & 0x1f;
254 }
255
256 enum MITE_UNKNOWN_DMA_BURST_bits {
257 UNKNOWN_DMA_BURST_ENABLE_BITS = 0x600
258 };
259
mite_csigr_version(u32 csigr_bits)260 static inline int mite_csigr_version(u32 csigr_bits)
261 {
262 return csigr_bits & 0xf;
263 };
264
mite_csigr_type(u32 csigr_bits)265 static inline int mite_csigr_type(u32 csigr_bits)
266 { /* original mite = 0, minimite = 1 */
267 return (csigr_bits >> 4) & 0xf;
268 };
269
mite_csigr_mmode(u32 csigr_bits)270 static inline int mite_csigr_mmode(u32 csigr_bits)
271 { /* mite mode, minimite = 1 */
272 return (csigr_bits >> 8) & 0x3;
273 };
274
mite_csigr_imode(u32 csigr_bits)275 static inline int mite_csigr_imode(u32 csigr_bits)
276 { /* cpu port interface mode, pci = 0x3 */
277 return (csigr_bits >> 12) & 0x3;
278 };
279
mite_csigr_dmac(u32 csigr_bits)280 static inline int mite_csigr_dmac(u32 csigr_bits)
281 { /* number of dma channels */
282 return (csigr_bits >> 16) & 0xf;
283 };
284
mite_csigr_wpdep(u32 csigr_bits)285 static inline int mite_csigr_wpdep(u32 csigr_bits)
286 { /* write post fifo depth */
287 unsigned int wpdep_bits = (csigr_bits >> 20) & 0x7;
288 if (wpdep_bits == 0)
289 return 0;
290 else
291 return 1 << (wpdep_bits - 1);
292 };
293
mite_csigr_wins(u32 csigr_bits)294 static inline int mite_csigr_wins(u32 csigr_bits)
295 {
296 return (csigr_bits >> 24) & 0x1f;
297 };
298
mite_csigr_iowins(u32 csigr_bits)299 static inline int mite_csigr_iowins(u32 csigr_bits)
300 { /* number of io windows */
301 return (csigr_bits >> 29) & 0x7;
302 };
303
304 enum MITE_MCR_bits {
305 MCRPON = 0,
306 };
307
308 enum MITE_DCR_bits {
309 DCR_NORMAL = (1 << 29),
310 DCRPON = 0,
311 };
312
313 enum MITE_CHOR_bits {
314 CHOR_DMARESET = (1 << 31),
315 CHOR_SET_SEND_TC = (1 << 11),
316 CHOR_CLR_SEND_TC = (1 << 10),
317 CHOR_SET_LPAUSE = (1 << 9),
318 CHOR_CLR_LPAUSE = (1 << 8),
319 CHOR_CLRDONE = (1 << 7),
320 CHOR_CLRRB = (1 << 6),
321 CHOR_CLRLC = (1 << 5),
322 CHOR_FRESET = (1 << 4),
323 CHOR_ABORT = (1 << 3), /* stop without emptying fifo */
324 CHOR_STOP = (1 << 2), /* stop after emptying fifo */
325 CHOR_CONT = (1 << 1),
326 CHOR_START = (1 << 0),
327 CHOR_PON = (CHOR_CLR_SEND_TC | CHOR_CLR_LPAUSE),
328 };
329
330 enum MITE_CHCR_bits {
331 CHCR_SET_DMA_IE = (1 << 31),
332 CHCR_CLR_DMA_IE = (1 << 30),
333 CHCR_SET_LINKP_IE = (1 << 29),
334 CHCR_CLR_LINKP_IE = (1 << 28),
335 CHCR_SET_SAR_IE = (1 << 27),
336 CHCR_CLR_SAR_IE = (1 << 26),
337 CHCR_SET_DONE_IE = (1 << 25),
338 CHCR_CLR_DONE_IE = (1 << 24),
339 CHCR_SET_MRDY_IE = (1 << 23),
340 CHCR_CLR_MRDY_IE = (1 << 22),
341 CHCR_SET_DRDY_IE = (1 << 21),
342 CHCR_CLR_DRDY_IE = (1 << 20),
343 CHCR_SET_LC_IE = (1 << 19),
344 CHCR_CLR_LC_IE = (1 << 18),
345 CHCR_SET_CONT_RB_IE = (1 << 17),
346 CHCR_CLR_CONT_RB_IE = (1 << 16),
347 CHCR_FIFODIS = (1 << 15),
348 CHCR_FIFO_ON = 0,
349 CHCR_BURSTEN = (1 << 14),
350 CHCR_NO_BURSTEN = 0,
351 CHCR_BYTE_SWAP_DEVICE = (1 << 6),
352 CHCR_BYTE_SWAP_MEMORY = (1 << 4),
353 CHCR_DIR = (1 << 3),
354 CHCR_DEV_TO_MEM = CHCR_DIR,
355 CHCR_MEM_TO_DEV = 0,
356 CHCR_NORMAL = (0 << 0),
357 CHCR_CONTINUE = (1 << 0),
358 CHCR_RINGBUFF = (2 << 0),
359 CHCR_LINKSHORT = (4 << 0),
360 CHCR_LINKLONG = (5 << 0),
361 CHCRPON =
362 (CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
363 CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
364 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE),
365 };
366
367 enum ConfigRegister_bits {
368 CR_REQS_MASK = 0x7 << 16,
369 CR_ASEQDONT = 0x0 << 10,
370 CR_ASEQUP = 0x1 << 10,
371 CR_ASEQDOWN = 0x2 << 10,
372 CR_ASEQ_MASK = 0x3 << 10,
373 CR_PSIZE8 = (1 << 8),
374 CR_PSIZE16 = (2 << 8),
375 CR_PSIZE32 = (3 << 8),
376 CR_PORTCPU = (0 << 6),
377 CR_PORTIO = (1 << 6),
378 CR_PORTVXI = (2 << 6),
379 CR_PORTMXI = (3 << 6),
380 CR_AMDEVICE = (1 << 0),
381 };
CR_REQS(int source)382 static inline int CR_REQS(int source)
383 {
384 return (source & 0x7) << 16;
385 };
386
CR_REQSDRQ(unsigned drq_line)387 static inline int CR_REQSDRQ(unsigned drq_line)
388 {
389 /* This also works on m-series when
390 using channels (drq_line) 4 or 5. */
391 return CR_REQS((drq_line & 0x3) | 0x4);
392 }
393
CR_RL(unsigned int retry_limit)394 static inline int CR_RL(unsigned int retry_limit)
395 {
396 int value = 0;
397
398 if (retry_limit)
399 value = 1 + ilog2(retry_limit);
400 if (value > 0x7)
401 value = 0x7;
402 return (value & 0x7) << 21;
403 }
404
405 enum CHSR_bits {
406 CHSR_INT = (1 << 31),
407 CHSR_LPAUSES = (1 << 29),
408 CHSR_SARS = (1 << 27),
409 CHSR_DONE = (1 << 25),
410 CHSR_MRDY = (1 << 23),
411 CHSR_DRDY = (1 << 21),
412 CHSR_LINKC = (1 << 19),
413 CHSR_CONTS_RB = (1 << 17),
414 CHSR_ERROR = (1 << 15),
415 CHSR_SABORT = (1 << 14),
416 CHSR_HABORT = (1 << 13),
417 CHSR_STOPS = (1 << 12),
418 CHSR_OPERR_mask = (3 << 10),
419 CHSR_OPERR_NOERROR = (0 << 10),
420 CHSR_OPERR_FIFOERROR = (1 << 10),
421 CHSR_OPERR_LINKERROR = (1 << 10), /* ??? */
422 CHSR_XFERR = (1 << 9),
423 CHSR_END = (1 << 8),
424 CHSR_DRQ1 = (1 << 7),
425 CHSR_DRQ0 = (1 << 6),
426 CHSR_LxERR_mask = (3 << 4),
427 CHSR_LBERR = (1 << 4),
428 CHSR_LRERR = (2 << 4),
429 CHSR_LOERR = (3 << 4),
430 CHSR_MxERR_mask = (3 << 2),
431 CHSR_MBERR = (1 << 2),
432 CHSR_MRERR = (2 << 2),
433 CHSR_MOERR = (3 << 2),
434 CHSR_DxERR_mask = (3 << 0),
435 CHSR_DBERR = (1 << 0),
436 CHSR_DRERR = (2 << 0),
437 CHSR_DOERR = (3 << 0),
438 };
439
mite_dma_reset(struct mite_channel * mite_chan)440 static inline void mite_dma_reset(struct mite_channel *mite_chan)
441 {
442 writel(CHOR_DMARESET | CHOR_FRESET,
443 mite_chan->mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
444 };
445
446 #endif
447