1 /*
2 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 */
15
16 #include <linux/export.h>
17 #include <linux/module.h>
18 #include <linux/types.h>
19 #include <linux/errno.h>
20 #include <linux/delay.h>
21 #include <linux/io.h>
22
23 #include "../imx-drm.h"
24 #include "imx-ipu-v3.h"
25 #include "ipu-prv.h"
26
27 #define DC_MAP_CONF_PTR(n) (0x108 + ((n) & ~0x1) * 2)
28 #define DC_MAP_CONF_VAL(n) (0x144 + ((n) & ~0x1) * 2)
29
30 #define DC_EVT_NF 0
31 #define DC_EVT_NL 1
32 #define DC_EVT_EOF 2
33 #define DC_EVT_NFIELD 3
34 #define DC_EVT_EOL 4
35 #define DC_EVT_EOFIELD 5
36 #define DC_EVT_NEW_ADDR 6
37 #define DC_EVT_NEW_CHAN 7
38 #define DC_EVT_NEW_DATA 8
39
40 #define DC_EVT_NEW_ADDR_W_0 0
41 #define DC_EVT_NEW_ADDR_W_1 1
42 #define DC_EVT_NEW_CHAN_W_0 2
43 #define DC_EVT_NEW_CHAN_W_1 3
44 #define DC_EVT_NEW_DATA_W_0 4
45 #define DC_EVT_NEW_DATA_W_1 5
46 #define DC_EVT_NEW_ADDR_R_0 6
47 #define DC_EVT_NEW_ADDR_R_1 7
48 #define DC_EVT_NEW_CHAN_R_0 8
49 #define DC_EVT_NEW_CHAN_R_1 9
50 #define DC_EVT_NEW_DATA_R_0 10
51 #define DC_EVT_NEW_DATA_R_1 11
52
53 #define DC_WR_CH_CONF 0x0
54 #define DC_WR_CH_ADDR 0x4
55 #define DC_RL_CH(evt) (8 + ((evt) & ~0x1) * 2)
56
57 #define DC_GEN 0xd4
58 #define DC_DISP_CONF1(disp) (0xd8 + (disp) * 4)
59 #define DC_DISP_CONF2(disp) (0xe8 + (disp) * 4)
60 #define DC_STAT 0x1c8
61
62 #define WROD(lf) (0x18 | ((lf) << 1))
63 #define WRG 0x01
64 #define WCLK 0xc9
65
66 #define SYNC_WAVE 0
67 #define NULL_WAVE (-1)
68
69 #define DC_GEN_SYNC_1_6_SYNC (2 << 1)
70 #define DC_GEN_SYNC_PRIORITY_1 (1 << 7)
71
72 #define DC_WR_CH_CONF_WORD_SIZE_8 (0 << 0)
73 #define DC_WR_CH_CONF_WORD_SIZE_16 (1 << 0)
74 #define DC_WR_CH_CONF_WORD_SIZE_24 (2 << 0)
75 #define DC_WR_CH_CONF_WORD_SIZE_32 (3 << 0)
76 #define DC_WR_CH_CONF_DISP_ID_PARALLEL(i) (((i) & 0x1) << 3)
77 #define DC_WR_CH_CONF_DISP_ID_SERIAL (2 << 3)
78 #define DC_WR_CH_CONF_DISP_ID_ASYNC (3 << 4)
79 #define DC_WR_CH_CONF_FIELD_MODE (1 << 9)
80 #define DC_WR_CH_CONF_PROG_TYPE_NORMAL (4 << 5)
81 #define DC_WR_CH_CONF_PROG_TYPE_MASK (7 << 5)
82 #define DC_WR_CH_CONF_PROG_DI_ID (1 << 2)
83 #define DC_WR_CH_CONF_PROG_DISP_ID(i) (((i) & 0x1) << 3)
84
85 #define IPU_DC_NUM_CHANNELS 10
86
87 struct ipu_dc_priv;
88
89 enum ipu_dc_map {
90 IPU_DC_MAP_RGB24,
91 IPU_DC_MAP_RGB565,
92 IPU_DC_MAP_GBR24, /* TVEv2 */
93 IPU_DC_MAP_BGR666,
94 };
95
96 struct ipu_dc {
97 /* The display interface number assigned to this dc channel */
98 unsigned int di;
99 void __iomem *base;
100 struct ipu_dc_priv *priv;
101 int chno;
102 bool in_use;
103 };
104
105 struct ipu_dc_priv {
106 void __iomem *dc_reg;
107 void __iomem *dc_tmpl_reg;
108 struct ipu_soc *ipu;
109 struct device *dev;
110 struct ipu_dc channels[IPU_DC_NUM_CHANNELS];
111 struct mutex mutex;
112 };
113
dc_link_event(struct ipu_dc * dc,int event,int addr,int priority)114 static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority)
115 {
116 u32 reg;
117
118 reg = readl(dc->base + DC_RL_CH(event));
119 reg &= ~(0xffff << (16 * (event & 0x1)));
120 reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
121 writel(reg, dc->base + DC_RL_CH(event));
122 }
123
dc_write_tmpl(struct ipu_dc * dc,int word,u32 opcode,u32 operand,int map,int wave,int glue,int sync,int stop)124 static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand,
125 int map, int wave, int glue, int sync, int stop)
126 {
127 struct ipu_dc_priv *priv = dc->priv;
128 u32 reg1, reg2;
129
130 if (opcode == WCLK) {
131 reg1 = (operand << 20) & 0xfff00000;
132 reg2 = operand >> 12 | opcode << 1 | stop << 9;
133 } else if (opcode == WRG) {
134 reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000);
135 reg2 = operand >> 17 | opcode << 7 | stop << 9;
136 } else {
137 reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000);
138 reg2 = operand >> 12 | opcode << 4 | stop << 9;
139 }
140 writel(reg1, priv->dc_tmpl_reg + word * 8);
141 writel(reg2, priv->dc_tmpl_reg + word * 8 + 4);
142 }
143
ipu_pixfmt_to_map(u32 fmt)144 static int ipu_pixfmt_to_map(u32 fmt)
145 {
146 switch (fmt) {
147 case V4L2_PIX_FMT_RGB24:
148 return IPU_DC_MAP_RGB24;
149 case V4L2_PIX_FMT_RGB565:
150 return IPU_DC_MAP_RGB565;
151 case IPU_PIX_FMT_GBR24:
152 return IPU_DC_MAP_GBR24;
153 case V4L2_PIX_FMT_BGR666:
154 return IPU_DC_MAP_BGR666;
155 default:
156 return -EINVAL;
157 }
158 }
159
ipu_dc_init_sync(struct ipu_dc * dc,struct ipu_di * di,bool interlaced,u32 pixel_fmt,u32 width)160 int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
161 u32 pixel_fmt, u32 width)
162 {
163 struct ipu_dc_priv *priv = dc->priv;
164 u32 reg = 0, map;
165
166 dc->di = ipu_di_get_num(di);
167
168 map = ipu_pixfmt_to_map(pixel_fmt);
169 if (map < 0) {
170 dev_dbg(priv->dev, "IPU_DISP: No MAP\n");
171 return -EINVAL;
172 }
173
174 if (interlaced) {
175 dc_link_event(dc, DC_EVT_NL, 0, 3);
176 dc_link_event(dc, DC_EVT_EOL, 0, 2);
177 dc_link_event(dc, DC_EVT_NEW_DATA, 0, 1);
178
179 /* Init template microcode */
180 dc_write_tmpl(dc, 0, WROD(0), 0, map, SYNC_WAVE, 0, 8, 1);
181 } else {
182 if (dc->di) {
183 dc_link_event(dc, DC_EVT_NL, 2, 3);
184 dc_link_event(dc, DC_EVT_EOL, 3, 2);
185 dc_link_event(dc, DC_EVT_NEW_DATA, 1, 1);
186 /* Init template microcode */
187 dc_write_tmpl(dc, 2, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
188 dc_write_tmpl(dc, 3, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);
189 dc_write_tmpl(dc, 4, WRG, 0, map, NULL_WAVE, 0, 0, 1);
190 dc_write_tmpl(dc, 1, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
191 } else {
192 dc_link_event(dc, DC_EVT_NL, 5, 3);
193 dc_link_event(dc, DC_EVT_EOL, 6, 2);
194 dc_link_event(dc, DC_EVT_NEW_DATA, 8, 1);
195 /* Init template microcode */
196 dc_write_tmpl(dc, 5, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
197 dc_write_tmpl(dc, 6, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);
198 dc_write_tmpl(dc, 7, WRG, 0, map, NULL_WAVE, 0, 0, 1);
199 dc_write_tmpl(dc, 8, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
200 }
201 }
202 dc_link_event(dc, DC_EVT_NF, 0, 0);
203 dc_link_event(dc, DC_EVT_NFIELD, 0, 0);
204 dc_link_event(dc, DC_EVT_EOF, 0, 0);
205 dc_link_event(dc, DC_EVT_EOFIELD, 0, 0);
206 dc_link_event(dc, DC_EVT_NEW_CHAN, 0, 0);
207 dc_link_event(dc, DC_EVT_NEW_ADDR, 0, 0);
208
209 reg = readl(dc->base + DC_WR_CH_CONF);
210 if (interlaced)
211 reg |= DC_WR_CH_CONF_FIELD_MODE;
212 else
213 reg &= ~DC_WR_CH_CONF_FIELD_MODE;
214 writel(reg, dc->base + DC_WR_CH_CONF);
215
216 writel(0x0, dc->base + DC_WR_CH_ADDR);
217 writel(width, priv->dc_reg + DC_DISP_CONF2(dc->di));
218
219 ipu_module_enable(priv->ipu, IPU_CONF_DC_EN);
220
221 return 0;
222 }
223 EXPORT_SYMBOL_GPL(ipu_dc_init_sync);
224
ipu_dc_enable_channel(struct ipu_dc * dc)225 void ipu_dc_enable_channel(struct ipu_dc *dc)
226 {
227 int di;
228 u32 reg;
229
230 di = dc->di;
231
232 reg = readl(dc->base + DC_WR_CH_CONF);
233 reg |= DC_WR_CH_CONF_PROG_TYPE_NORMAL;
234 writel(reg, dc->base + DC_WR_CH_CONF);
235 }
236 EXPORT_SYMBOL_GPL(ipu_dc_enable_channel);
237
ipu_dc_disable_channel(struct ipu_dc * dc)238 void ipu_dc_disable_channel(struct ipu_dc *dc)
239 {
240 struct ipu_dc_priv *priv = dc->priv;
241 u32 val;
242 int irq = 0, timeout = 50;
243
244 if (dc->chno == 1)
245 irq = IPU_IRQ_DC_FC_1;
246 else if (dc->chno == 5)
247 irq = IPU_IRQ_DP_SF_END;
248 else
249 return;
250
251 /* should wait for the interrupt here */
252 mdelay(50);
253
254 if (dc->di == 0)
255 val = 0x00000002;
256 else
257 val = 0x00000020;
258
259 /* Wait for DC triple buffer to empty */
260 while ((readl(priv->dc_reg + DC_STAT) & val) != val) {
261 msleep(2);
262 timeout -= 2;
263 if (timeout <= 0)
264 break;
265 }
266
267 val = readl(dc->base + DC_WR_CH_CONF);
268 val &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
269 writel(val, dc->base + DC_WR_CH_CONF);
270 }
271 EXPORT_SYMBOL_GPL(ipu_dc_disable_channel);
272
ipu_dc_map_config(struct ipu_dc_priv * priv,enum ipu_dc_map map,int byte_num,int offset,int mask)273 static void ipu_dc_map_config(struct ipu_dc_priv *priv, enum ipu_dc_map map,
274 int byte_num, int offset, int mask)
275 {
276 int ptr = map * 3 + byte_num;
277 u32 reg;
278
279 reg = readl(priv->dc_reg + DC_MAP_CONF_VAL(ptr));
280 reg &= ~(0xffff << (16 * (ptr & 0x1)));
281 reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
282 writel(reg, priv->dc_reg + DC_MAP_CONF_VAL(ptr));
283
284 reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
285 reg &= ~(0x1f << ((16 * (map & 0x1)) + (5 * byte_num)));
286 reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
287 writel(reg, priv->dc_reg + DC_MAP_CONF_PTR(map));
288 }
289
ipu_dc_map_clear(struct ipu_dc_priv * priv,int map)290 static void ipu_dc_map_clear(struct ipu_dc_priv *priv, int map)
291 {
292 u32 reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
293
294 writel(reg & ~(0xffff << (16 * (map & 0x1))),
295 priv->dc_reg + DC_MAP_CONF_PTR(map));
296 }
297
ipu_dc_get(struct ipu_soc * ipu,int channel)298 struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel)
299 {
300 struct ipu_dc_priv *priv = ipu->dc_priv;
301 struct ipu_dc *dc;
302
303 if (channel >= IPU_DC_NUM_CHANNELS)
304 return ERR_PTR(-ENODEV);
305
306 dc = &priv->channels[channel];
307
308 mutex_lock(&priv->mutex);
309
310 if (dc->in_use) {
311 mutex_unlock(&priv->mutex);
312 return ERR_PTR(-EBUSY);
313 }
314
315 dc->in_use = 1;
316
317 mutex_unlock(&priv->mutex);
318
319 return dc;
320 }
321 EXPORT_SYMBOL_GPL(ipu_dc_get);
322
ipu_dc_put(struct ipu_dc * dc)323 void ipu_dc_put(struct ipu_dc *dc)
324 {
325 struct ipu_dc_priv *priv = dc->priv;
326
327 mutex_lock(&priv->mutex);
328 dc->in_use = 0;
329 mutex_unlock(&priv->mutex);
330 }
331 EXPORT_SYMBOL_GPL(ipu_dc_put);
332
ipu_dc_init(struct ipu_soc * ipu,struct device * dev,unsigned long base,unsigned long template_base)333 int ipu_dc_init(struct ipu_soc *ipu, struct device *dev,
334 unsigned long base, unsigned long template_base)
335 {
336 struct ipu_dc_priv *priv;
337 static int channel_offsets[] = { 0, 0x1c, 0x38, 0x54, 0x58, 0x5c,
338 0x78, 0, 0x94, 0xb4};
339 int i;
340
341 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
342 if (!priv)
343 return -ENOMEM;
344
345 mutex_init(&priv->mutex);
346
347 priv->dev = dev;
348 priv->ipu = ipu;
349 priv->dc_reg = devm_ioremap(dev, base, PAGE_SIZE);
350 priv->dc_tmpl_reg = devm_ioremap(dev, template_base, PAGE_SIZE);
351 if (!priv->dc_reg || !priv->dc_tmpl_reg)
352 return -ENOMEM;
353
354 for (i = 0; i < IPU_DC_NUM_CHANNELS; i++) {
355 priv->channels[i].chno = i;
356 priv->channels[i].priv = priv;
357 priv->channels[i].base = priv->dc_reg + channel_offsets[i];
358 }
359
360 writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(1) |
361 DC_WR_CH_CONF_PROG_DI_ID,
362 priv->channels[1].base + DC_WR_CH_CONF);
363 writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(0),
364 priv->channels[5].base + DC_WR_CH_CONF);
365
366 writel(DC_GEN_SYNC_1_6_SYNC | DC_GEN_SYNC_PRIORITY_1, priv->dc_reg + DC_GEN);
367
368 ipu->dc_priv = priv;
369
370 dev_dbg(dev, "DC base: 0x%08lx template base: 0x%08lx\n",
371 base, template_base);
372
373 /* rgb24 */
374 ipu_dc_map_clear(priv, IPU_DC_MAP_RGB24);
375 ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 0, 7, 0xff); /* blue */
376 ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 1, 15, 0xff); /* green */
377 ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 2, 23, 0xff); /* red */
378
379 /* rgb565 */
380 ipu_dc_map_clear(priv, IPU_DC_MAP_RGB565);
381 ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 0, 4, 0xf8); /* blue */
382 ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 1, 10, 0xfc); /* green */
383 ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 2, 15, 0xf8); /* red */
384
385 /* gbr24 */
386 ipu_dc_map_clear(priv, IPU_DC_MAP_GBR24);
387 ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 2, 15, 0xff); /* green */
388 ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 1, 7, 0xff); /* blue */
389 ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 0, 23, 0xff); /* red */
390
391 /* bgr666 */
392 ipu_dc_map_clear(priv, IPU_DC_MAP_BGR666);
393 ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 0, 5, 0xfc); /* blue */
394 ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 1, 11, 0xfc); /* green */
395 ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 2, 17, 0xfc); /* red */
396
397 return 0;
398 }
399
ipu_dc_exit(struct ipu_soc * ipu)400 void ipu_dc_exit(struct ipu_soc *ipu)
401 {
402 }
403