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1 /***************************************************************************
2  *   Copyright (C) 2006-2010 by Marin Mitov                                *
3  *   mitov@issp.bas.bg                                                     *
4  *                                                                         *
5  *   This program is free software; you can redistribute it and/or modify  *
6  *   it under the terms of the GNU General Public License as published by  *
7  *   the Free Software Foundation; either version 2 of the License, or     *
8  *   (at your option) any later version.                                   *
9  *                                                                         *
10  *   This program is distributed in the hope that it will be useful,       *
11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
13  *   GNU General Public License for more details.                          *
14  *                                                                         *
15  *   You should have received a copy of the GNU General Public License     *
16  *   along with this program; if not, write to the                         *
17  *   Free Software Foundation, Inc.,                                       *
18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
19  ***************************************************************************/
20 
21 #include <linux/module.h>
22 #include <linux/version.h>
23 #include <linux/stringify.h>
24 #include <linux/delay.h>
25 #include <linux/kthread.h>
26 #include <linux/slab.h>
27 #include <media/v4l2-dev.h>
28 #include <media/v4l2-ioctl.h>
29 #include <media/v4l2-common.h>
30 #include <media/videobuf2-dma-contig.h>
31 
32 #include "dt3155v4l.h"
33 
34 #define DT3155_VENDOR_ID 0x8086
35 #define DT3155_DEVICE_ID 0x1223
36 
37 /* DT3155_CHUNK_SIZE is 4M (2^22) 8 full size buffers */
38 #define DT3155_CHUNK_SIZE (1U << 22)
39 
40 #define DT3155_COH_FLAGS (GFP_KERNEL | GFP_DMA32 | __GFP_COLD | __GFP_NOWARN)
41 
42 #define DT3155_BUF_SIZE (768 * 576)
43 
44 #ifdef CONFIG_DT3155_STREAMING
45 #define DT3155_CAPTURE_METHOD V4L2_CAP_STREAMING
46 #else
47 #define DT3155_CAPTURE_METHOD V4L2_CAP_READWRITE
48 #endif
49 
50 /*  global initializers (for all boards)  */
51 #ifdef CONFIG_DT3155_CCIR
52 static const u8 csr2_init = VT_50HZ;
53 #define DT3155_CURRENT_NORM V4L2_STD_625_50
54 static const unsigned int img_width = 768;
55 static const unsigned int img_height = 576;
56 static const unsigned int frames_per_sec = 25;
57 static const struct v4l2_fmtdesc frame_std[] = {
58 	{
59 	.index = 0,
60 	.type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
61 	.flags = 0,
62 	.description = "CCIR/50Hz 8 bits gray",
63 	.pixelformat = V4L2_PIX_FMT_GREY,
64 	},
65 };
66 #else
67 static const u8 csr2_init = VT_60HZ;
68 #define DT3155_CURRENT_NORM V4L2_STD_525_60
69 static const unsigned int img_width = 640;
70 static const unsigned int img_height = 480;
71 static const unsigned int frames_per_sec = 30;
72 static const struct v4l2_fmtdesc frame_std[] = {
73 	{
74 	.index = 0,
75 	.type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
76 	.flags = 0,
77 	.description = "RS-170/60Hz 8 bits gray",
78 	.pixelformat = V4L2_PIX_FMT_GREY,
79 	},
80 };
81 #endif
82 
83 #define NUM_OF_FORMATS ARRAY_SIZE(frame_std)
84 
85 static u8 config_init = ACQ_MODE_EVEN;
86 
87 /**
88  * read_i2c_reg - reads an internal i2c register
89  *
90  * @addr:	dt3155 mmio base address
91  * @index:	index (internal address) of register to read
92  * @data:	pointer to byte the read data will be placed in
93  *
94  * returns:	zero on success or error code
95  *
96  * This function starts reading the specified (by index) register
97  * and busy waits for the process to finish. The result is placed
98  * in a byte pointed by data.
99  */
100 static int
read_i2c_reg(void __iomem * addr,u8 index,u8 * data)101 read_i2c_reg(void __iomem *addr, u8 index, u8 *data)
102 {
103 	u32 tmp = index;
104 
105 	iowrite32((tmp<<17) | IIC_READ, addr + IIC_CSR2);
106 	mmiowb();
107 	udelay(45); /* wait at least 43 usec for NEW_CYCLE to clear */
108 	if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
109 		return -EIO; /* error: NEW_CYCLE not cleared */
110 	tmp = ioread32(addr + IIC_CSR1);
111 	if (tmp & DIRECT_ABORT) {
112 		/* reset DIRECT_ABORT bit */
113 		iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
114 		return -EIO; /* error: DIRECT_ABORT set */
115 	}
116 	*data = tmp>>24;
117 	return 0;
118 }
119 
120 /**
121  * write_i2c_reg - writes to an internal i2c register
122  *
123  * @addr:	dt3155 mmio base address
124  * @index:	index (internal address) of register to read
125  * @data:	data to be written
126  *
127  * returns:	zero on success or error code
128  *
129  * This function starts writting the specified (by index) register
130  * and busy waits for the process to finish.
131  */
132 static int
write_i2c_reg(void __iomem * addr,u8 index,u8 data)133 write_i2c_reg(void __iomem *addr, u8 index, u8 data)
134 {
135 	u32 tmp = index;
136 
137 	iowrite32((tmp<<17) | IIC_WRITE | data, addr + IIC_CSR2);
138 	mmiowb();
139 	udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
140 	if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
141 		return -EIO; /* error: NEW_CYCLE not cleared */
142 	if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
143 		/* reset DIRECT_ABORT bit */
144 		iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
145 		return -EIO; /* error: DIRECT_ABORT set */
146 	}
147 	return 0;
148 }
149 
150 /**
151  * write_i2c_reg_nowait - writes to an internal i2c register
152  *
153  * @addr:	dt3155 mmio base address
154  * @index:	index (internal address) of register to read
155  * @data:	data to be written
156  *
157  * This function starts writting the specified (by index) register
158  * and then returns.
159  */
write_i2c_reg_nowait(void __iomem * addr,u8 index,u8 data)160 static void write_i2c_reg_nowait(void __iomem *addr, u8 index, u8 data)
161 {
162 	u32 tmp = index;
163 
164 	iowrite32((tmp<<17) | IIC_WRITE | data, addr + IIC_CSR2);
165 	mmiowb();
166 }
167 
168 /**
169  * wait_i2c_reg - waits the read/write to finish
170  *
171  * @addr:	dt3155 mmio base address
172  *
173  * returns:	zero on success or error code
174  *
175  * This function waits reading/writting to finish.
176  */
wait_i2c_reg(void __iomem * addr)177 static int wait_i2c_reg(void __iomem *addr)
178 {
179 	if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
180 		udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
181 	if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
182 		return -EIO; /* error: NEW_CYCLE not cleared */
183 	if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
184 		/* reset DIRECT_ABORT bit */
185 		iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
186 		return -EIO; /* error: DIRECT_ABORT set */
187 	}
188 	return 0;
189 }
190 
191 static int
dt3155_start_acq(struct dt3155_priv * pd)192 dt3155_start_acq(struct dt3155_priv *pd)
193 {
194 	struct vb2_buffer *vb = pd->curr_buf;
195 	dma_addr_t dma_addr;
196 
197 	dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
198 	iowrite32(dma_addr, pd->regs + EVEN_DMA_START);
199 	iowrite32(dma_addr + img_width, pd->regs + ODD_DMA_START);
200 	iowrite32(img_width, pd->regs + EVEN_DMA_STRIDE);
201 	iowrite32(img_width, pd->regs + ODD_DMA_STRIDE);
202 	/* enable interrupts, clear all irq flags */
203 	iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
204 			FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
205 	iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
206 		  FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD,
207 							pd->regs + CSR1);
208 	wait_i2c_reg(pd->regs);
209 	write_i2c_reg(pd->regs, CONFIG, pd->config);
210 	write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE);
211 	write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE);
212 
213 	/*  start the board  */
214 	write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD);
215 	return 0; /* success  */
216 }
217 
218 /*
219  *	driver-specific callbacks (vb2_ops)
220  */
221 static int
dt3155_queue_setup(struct vb2_queue * q,const struct v4l2_format * fmt,unsigned int * num_buffers,unsigned int * num_planes,unsigned int sizes[],void * alloc_ctxs[])222 dt3155_queue_setup(struct vb2_queue *q, const struct v4l2_format *fmt,
223 		unsigned int *num_buffers, unsigned int *num_planes,
224 		unsigned int sizes[], void *alloc_ctxs[])
225 
226 {
227 	struct dt3155_priv *pd = vb2_get_drv_priv(q);
228 	void *ret;
229 
230 	if (*num_buffers == 0)
231 		*num_buffers = 1;
232 	*num_planes = 1;
233 	sizes[0] = img_width * img_height;
234 	if (pd->q->alloc_ctx[0])
235 		return 0;
236 	ret = vb2_dma_contig_init_ctx(&pd->pdev->dev);
237 	if (IS_ERR(ret))
238 		return PTR_ERR(ret);
239 	pd->q->alloc_ctx[0] = ret;
240 	return 0;
241 }
242 
243 static void
dt3155_wait_prepare(struct vb2_queue * q)244 dt3155_wait_prepare(struct vb2_queue *q)
245 {
246 	struct dt3155_priv *pd = vb2_get_drv_priv(q);
247 
248 	mutex_unlock(pd->vdev->lock);
249 }
250 
251 static void
dt3155_wait_finish(struct vb2_queue * q)252 dt3155_wait_finish(struct vb2_queue *q)
253 {
254 	struct dt3155_priv *pd = vb2_get_drv_priv(q);
255 
256 	mutex_lock(pd->vdev->lock);
257 }
258 
259 static int
dt3155_buf_prepare(struct vb2_buffer * vb)260 dt3155_buf_prepare(struct vb2_buffer *vb)
261 {
262 	vb2_set_plane_payload(vb, 0, img_width * img_height);
263 	return 0;
264 }
265 
266 static int
dt3155_stop_streaming(struct vb2_queue * q)267 dt3155_stop_streaming(struct vb2_queue *q)
268 {
269 	struct dt3155_priv *pd = vb2_get_drv_priv(q);
270 	struct vb2_buffer *vb;
271 
272 	spin_lock_irq(&pd->lock);
273 	while (!list_empty(&pd->dmaq)) {
274 		vb = list_first_entry(&pd->dmaq, typeof(*vb), done_entry);
275 		list_del(&vb->done_entry);
276 		vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
277 	}
278 	spin_unlock_irq(&pd->lock);
279 	msleep(45); /* irq hendler will stop the hardware */
280 	return 0;
281 }
282 
283 static void
dt3155_buf_queue(struct vb2_buffer * vb)284 dt3155_buf_queue(struct vb2_buffer *vb)
285 {
286 	struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue);
287 
288 	/*  pd->q->streaming = 1 when dt3155_buf_queue() is invoked  */
289 	spin_lock_irq(&pd->lock);
290 	if (pd->curr_buf)
291 		list_add_tail(&vb->done_entry, &pd->dmaq);
292 	else {
293 		pd->curr_buf = vb;
294 		dt3155_start_acq(pd);
295 	}
296 	spin_unlock_irq(&pd->lock);
297 }
298 /*
299  *	end driver-specific callbacks
300  */
301 
302 const struct vb2_ops q_ops = {
303 	.queue_setup = dt3155_queue_setup,
304 	.wait_prepare = dt3155_wait_prepare,
305 	.wait_finish = dt3155_wait_finish,
306 	.buf_prepare = dt3155_buf_prepare,
307 	.stop_streaming = dt3155_stop_streaming,
308 	.buf_queue = dt3155_buf_queue,
309 };
310 
311 static irqreturn_t
dt3155_irq_handler_even(int irq,void * dev_id)312 dt3155_irq_handler_even(int irq, void *dev_id)
313 {
314 	struct dt3155_priv *ipd = dev_id;
315 	struct vb2_buffer *ivb;
316 	dma_addr_t dma_addr;
317 	u32 tmp;
318 
319 	tmp = ioread32(ipd->regs + INT_CSR) & (FLD_START | FLD_END_ODD);
320 	if (!tmp)
321 		return IRQ_NONE;  /* not our irq */
322 	if ((tmp & FLD_START) && !(tmp & FLD_END_ODD)) {
323 		iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START,
324 							ipd->regs + INT_CSR);
325 		ipd->field_count++;
326 		return IRQ_HANDLED; /* start of field irq */
327 	}
328 	if ((tmp & FLD_START) && (tmp & FLD_END_ODD))
329 		ipd->stats.start_before_end++;
330 	/*	check for corrupted fields     */
331 /*	write_i2c_reg(ipd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE);	*/
332 /*	write_i2c_reg(ipd->regs, ODD_CSR, CSR_ERROR | CSR_DONE);	*/
333 	tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD);
334 	if (tmp) {
335 		ipd->stats.corrupted_fields++;
336 		iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
337 						FLD_DN_ODD | FLD_DN_EVEN |
338 						CAP_CONT_EVEN | CAP_CONT_ODD,
339 							ipd->regs + CSR1);
340 		mmiowb();
341 	}
342 
343 	spin_lock(&ipd->lock);
344 	if (ipd->curr_buf) {
345 		v4l2_get_timestamp(&ipd->curr_buf->v4l2_buf.timestamp);
346 		ipd->curr_buf->v4l2_buf.sequence = (ipd->field_count) >> 1;
347 		vb2_buffer_done(ipd->curr_buf, VB2_BUF_STATE_DONE);
348 	}
349 
350 	if (!ipd->q->streaming || list_empty(&ipd->dmaq))
351 		goto stop_dma;
352 	ivb = list_first_entry(&ipd->dmaq, typeof(*ivb), done_entry);
353 	list_del(&ivb->done_entry);
354 	ipd->curr_buf = ivb;
355 	dma_addr = vb2_dma_contig_plane_dma_addr(ivb, 0);
356 	iowrite32(dma_addr, ipd->regs + EVEN_DMA_START);
357 	iowrite32(dma_addr + img_width, ipd->regs + ODD_DMA_START);
358 	iowrite32(img_width, ipd->regs + EVEN_DMA_STRIDE);
359 	iowrite32(img_width, ipd->regs + ODD_DMA_STRIDE);
360 	mmiowb();
361 	/* enable interrupts, clear all irq flags */
362 	iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
363 			FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR);
364 	spin_unlock(&ipd->lock);
365 	return IRQ_HANDLED;
366 
367 stop_dma:
368 	ipd->curr_buf = NULL;
369 	/* stop the board */
370 	write_i2c_reg_nowait(ipd->regs, CSR2, ipd->csr2);
371 	iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
372 		  FLD_DN_ODD | FLD_DN_EVEN, ipd->regs + CSR1);
373 	/* disable interrupts, clear all irq flags */
374 	iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR);
375 	spin_unlock(&ipd->lock);
376 	return IRQ_HANDLED;
377 }
378 
379 static int
dt3155_open(struct file * filp)380 dt3155_open(struct file *filp)
381 {
382 	int ret = 0;
383 	struct dt3155_priv *pd = video_drvdata(filp);
384 
385 	if (mutex_lock_interruptible(&pd->mux))
386 		return -ERESTARTSYS;
387 	if (!pd->users) {
388 		pd->q = kzalloc(sizeof(*pd->q), GFP_KERNEL);
389 		if (!pd->q) {
390 			ret = -ENOMEM;
391 			goto err_alloc_queue;
392 		}
393 		pd->q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
394 		pd->q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
395 		pd->q->io_modes = VB2_READ | VB2_MMAP;
396 		pd->q->ops = &q_ops;
397 		pd->q->mem_ops = &vb2_dma_contig_memops;
398 		pd->q->drv_priv = pd;
399 		pd->curr_buf = NULL;
400 		pd->field_count = 0;
401 		ret = vb2_queue_init(pd->q);
402 		if (ret < 0)
403 			goto err_request_irq;
404 		INIT_LIST_HEAD(&pd->dmaq);
405 		spin_lock_init(&pd->lock);
406 		/* disable all irqs, clear all irq flags */
407 		iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD,
408 						pd->regs + INT_CSR);
409 		ret = request_irq(pd->pdev->irq, dt3155_irq_handler_even,
410 						IRQF_SHARED, DT3155_NAME, pd);
411 		if (ret)
412 			goto err_request_irq;
413 	}
414 	pd->users++;
415 	mutex_unlock(&pd->mux);
416 	return 0; /* success */
417 err_request_irq:
418 	kfree(pd->q);
419 	pd->q = NULL;
420 err_alloc_queue:
421 	mutex_unlock(&pd->mux);
422 	return ret;
423 }
424 
425 static int
dt3155_release(struct file * filp)426 dt3155_release(struct file *filp)
427 {
428 	struct dt3155_priv *pd = video_drvdata(filp);
429 
430 	mutex_lock(&pd->mux);
431 	pd->users--;
432 	BUG_ON(pd->users < 0);
433 	if (!pd->users) {
434 		vb2_queue_release(pd->q);
435 		free_irq(pd->pdev->irq, pd);
436 		if (pd->q->alloc_ctx[0])
437 			vb2_dma_contig_cleanup_ctx(pd->q->alloc_ctx[0]);
438 		kfree(pd->q);
439 		pd->q = NULL;
440 	}
441 	mutex_unlock(&pd->mux);
442 	return 0;
443 }
444 
445 static ssize_t
dt3155_read(struct file * filp,char __user * user,size_t size,loff_t * loff)446 dt3155_read(struct file *filp, char __user *user, size_t size, loff_t *loff)
447 {
448 	struct dt3155_priv *pd = video_drvdata(filp);
449 	ssize_t res;
450 
451 	if (mutex_lock_interruptible(&pd->mux))
452 		return -ERESTARTSYS;
453 	res = vb2_read(pd->q, user, size, loff, filp->f_flags & O_NONBLOCK);
454 	mutex_unlock(&pd->mux);
455 	return res;
456 }
457 
458 static unsigned int
dt3155_poll(struct file * filp,struct poll_table_struct * polltbl)459 dt3155_poll(struct file *filp, struct poll_table_struct *polltbl)
460 {
461 	struct dt3155_priv *pd = video_drvdata(filp);
462 	unsigned int res;
463 
464 	mutex_lock(&pd->mux);
465 	res = vb2_poll(pd->q, filp, polltbl);
466 	mutex_unlock(&pd->mux);
467 	return res;
468 }
469 
470 static int
dt3155_mmap(struct file * filp,struct vm_area_struct * vma)471 dt3155_mmap(struct file *filp, struct vm_area_struct *vma)
472 {
473 	struct dt3155_priv *pd = video_drvdata(filp);
474 	int res;
475 
476 	if (mutex_lock_interruptible(&pd->mux))
477 		return -ERESTARTSYS;
478 	res = vb2_mmap(pd->q, vma);
479 	mutex_unlock(&pd->mux);
480 	return res;
481 }
482 
483 static const struct v4l2_file_operations dt3155_fops = {
484 	.owner = THIS_MODULE,
485 	.open = dt3155_open,
486 	.release = dt3155_release,
487 	.read = dt3155_read,
488 	.poll = dt3155_poll,
489 	.unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */
490 	.mmap = dt3155_mmap,
491 };
492 
493 static int
dt3155_ioc_streamon(struct file * filp,void * p,enum v4l2_buf_type type)494 dt3155_ioc_streamon(struct file *filp, void *p, enum v4l2_buf_type type)
495 {
496 	struct dt3155_priv *pd = video_drvdata(filp);
497 
498 	return vb2_streamon(pd->q, type);
499 }
500 
501 static int
dt3155_ioc_streamoff(struct file * filp,void * p,enum v4l2_buf_type type)502 dt3155_ioc_streamoff(struct file *filp, void *p, enum v4l2_buf_type type)
503 {
504 	struct dt3155_priv *pd = video_drvdata(filp);
505 
506 	return vb2_streamoff(pd->q, type);
507 }
508 
509 static int
dt3155_ioc_querycap(struct file * filp,void * p,struct v4l2_capability * cap)510 dt3155_ioc_querycap(struct file *filp, void *p, struct v4l2_capability *cap)
511 {
512 	struct dt3155_priv *pd = video_drvdata(filp);
513 
514 	strcpy(cap->driver, DT3155_NAME);
515 	strcpy(cap->card, DT3155_NAME " frame grabber");
516 	sprintf(cap->bus_info, "PCI:%s", pci_name(pd->pdev));
517 	cap->version =
518 	       KERNEL_VERSION(DT3155_VER_MAJ, DT3155_VER_MIN, DT3155_VER_EXT);
519 	cap->capabilities = V4L2_CAP_VIDEO_CAPTURE |
520 				DT3155_CAPTURE_METHOD;
521 	return 0;
522 }
523 
524 static int
dt3155_ioc_enum_fmt_vid_cap(struct file * filp,void * p,struct v4l2_fmtdesc * f)525 dt3155_ioc_enum_fmt_vid_cap(struct file *filp, void *p, struct v4l2_fmtdesc *f)
526 {
527 	if (f->index >= NUM_OF_FORMATS)
528 		return -EINVAL;
529 	*f = frame_std[f->index];
530 	return 0;
531 }
532 
533 static int
dt3155_ioc_g_fmt_vid_cap(struct file * filp,void * p,struct v4l2_format * f)534 dt3155_ioc_g_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
535 {
536 	if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
537 		return -EINVAL;
538 	f->fmt.pix.width = img_width;
539 	f->fmt.pix.height = img_height;
540 	f->fmt.pix.pixelformat = V4L2_PIX_FMT_GREY;
541 	f->fmt.pix.field = V4L2_FIELD_NONE;
542 	f->fmt.pix.bytesperline = f->fmt.pix.width;
543 	f->fmt.pix.sizeimage = f->fmt.pix.width * f->fmt.pix.height;
544 	f->fmt.pix.colorspace = 0;
545 	f->fmt.pix.priv = 0;
546 	return 0;
547 }
548 
549 static int
dt3155_ioc_try_fmt_vid_cap(struct file * filp,void * p,struct v4l2_format * f)550 dt3155_ioc_try_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
551 {
552 	if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
553 		return -EINVAL;
554 	if (f->fmt.pix.width == img_width &&
555 		f->fmt.pix.height == img_height &&
556 		f->fmt.pix.pixelformat == V4L2_PIX_FMT_GREY &&
557 		f->fmt.pix.field == V4L2_FIELD_NONE &&
558 		f->fmt.pix.bytesperline == f->fmt.pix.width &&
559 		f->fmt.pix.sizeimage == f->fmt.pix.width * f->fmt.pix.height)
560 			return 0;
561 	else
562 		return -EINVAL;
563 }
564 
565 static int
dt3155_ioc_s_fmt_vid_cap(struct file * filp,void * p,struct v4l2_format * f)566 dt3155_ioc_s_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
567 {
568 	return dt3155_ioc_g_fmt_vid_cap(filp, p, f);
569 }
570 
571 static int
dt3155_ioc_reqbufs(struct file * filp,void * p,struct v4l2_requestbuffers * b)572 dt3155_ioc_reqbufs(struct file *filp, void *p, struct v4l2_requestbuffers *b)
573 {
574 	struct dt3155_priv *pd = video_drvdata(filp);
575 
576 	return vb2_reqbufs(pd->q, b);
577 }
578 
579 static int
dt3155_ioc_querybuf(struct file * filp,void * p,struct v4l2_buffer * b)580 dt3155_ioc_querybuf(struct file *filp, void *p, struct v4l2_buffer *b)
581 {
582 	struct dt3155_priv *pd = video_drvdata(filp);
583 
584 	return vb2_querybuf(pd->q, b);
585 }
586 
587 static int
dt3155_ioc_qbuf(struct file * filp,void * p,struct v4l2_buffer * b)588 dt3155_ioc_qbuf(struct file *filp, void *p, struct v4l2_buffer *b)
589 {
590 	struct dt3155_priv *pd = video_drvdata(filp);
591 
592 	return vb2_qbuf(pd->q, b);
593 }
594 
595 static int
dt3155_ioc_dqbuf(struct file * filp,void * p,struct v4l2_buffer * b)596 dt3155_ioc_dqbuf(struct file *filp, void *p, struct v4l2_buffer *b)
597 {
598 	struct dt3155_priv *pd = video_drvdata(filp);
599 
600 	return vb2_dqbuf(pd->q, b, filp->f_flags & O_NONBLOCK);
601 }
602 
603 static int
dt3155_ioc_querystd(struct file * filp,void * p,v4l2_std_id * norm)604 dt3155_ioc_querystd(struct file *filp, void *p, v4l2_std_id *norm)
605 {
606 	*norm = DT3155_CURRENT_NORM;
607 	return 0;
608 }
609 
610 static int
dt3155_ioc_g_std(struct file * filp,void * p,v4l2_std_id * norm)611 dt3155_ioc_g_std(struct file *filp, void *p, v4l2_std_id *norm)
612 {
613 	*norm = DT3155_CURRENT_NORM;
614 	return 0;
615 }
616 
617 static int
dt3155_ioc_s_std(struct file * filp,void * p,v4l2_std_id norm)618 dt3155_ioc_s_std(struct file *filp, void *p, v4l2_std_id norm)
619 {
620 	if (norm & DT3155_CURRENT_NORM)
621 		return 0;
622 	return -EINVAL;
623 }
624 
625 static int
dt3155_ioc_enum_input(struct file * filp,void * p,struct v4l2_input * input)626 dt3155_ioc_enum_input(struct file *filp, void *p, struct v4l2_input *input)
627 {
628 	if (input->index)
629 		return -EINVAL;
630 	strcpy(input->name, "Coax in");
631 	input->type = V4L2_INPUT_TYPE_CAMERA;
632 	/*
633 	 * FIXME: input->std = 0 according to v4l2 API
634 	 * VIDIOC_G_STD, VIDIOC_S_STD, VIDIOC_QUERYSTD and VIDIOC_ENUMSTD
635 	 * should return -EINVAL
636 	 */
637 	input->std = DT3155_CURRENT_NORM;
638 	input->status = 0;/* FIXME: add sync detection & V4L2_IN_ST_NO_H_LOCK */
639 	return 0;
640 }
641 
642 static int
dt3155_ioc_g_input(struct file * filp,void * p,unsigned int * i)643 dt3155_ioc_g_input(struct file *filp, void *p, unsigned int *i)
644 {
645 	*i = 0;
646 	return 0;
647 }
648 
649 static int
dt3155_ioc_s_input(struct file * filp,void * p,unsigned int i)650 dt3155_ioc_s_input(struct file *filp, void *p, unsigned int i)
651 {
652 	if (i)
653 		return -EINVAL;
654 	return 0;
655 }
656 
657 static int
dt3155_ioc_g_parm(struct file * filp,void * p,struct v4l2_streamparm * parms)658 dt3155_ioc_g_parm(struct file *filp, void *p, struct v4l2_streamparm *parms)
659 {
660 	if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
661 		return -EINVAL;
662 	parms->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
663 	parms->parm.capture.capturemode = 0;
664 	parms->parm.capture.timeperframe.numerator = 1001;
665 	parms->parm.capture.timeperframe.denominator = frames_per_sec * 1000;
666 	parms->parm.capture.extendedmode = 0;
667 	parms->parm.capture.readbuffers = 1; /* FIXME: 2 buffers? */
668 	return 0;
669 }
670 
671 static int
dt3155_ioc_s_parm(struct file * filp,void * p,struct v4l2_streamparm * parms)672 dt3155_ioc_s_parm(struct file *filp, void *p, struct v4l2_streamparm *parms)
673 {
674 	if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
675 		return -EINVAL;
676 	parms->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
677 	parms->parm.capture.capturemode = 0;
678 	parms->parm.capture.timeperframe.numerator = 1001;
679 	parms->parm.capture.timeperframe.denominator = frames_per_sec * 1000;
680 	parms->parm.capture.extendedmode = 0;
681 	parms->parm.capture.readbuffers = 1; /* FIXME: 2 buffers? */
682 	return 0;
683 }
684 
685 static const struct v4l2_ioctl_ops dt3155_ioctl_ops = {
686 	.vidioc_streamon = dt3155_ioc_streamon,
687 	.vidioc_streamoff = dt3155_ioc_streamoff,
688 	.vidioc_querycap = dt3155_ioc_querycap,
689 /*
690 	.vidioc_g_priority = dt3155_ioc_g_priority,
691 	.vidioc_s_priority = dt3155_ioc_s_priority,
692 */
693 	.vidioc_enum_fmt_vid_cap = dt3155_ioc_enum_fmt_vid_cap,
694 	.vidioc_try_fmt_vid_cap = dt3155_ioc_try_fmt_vid_cap,
695 	.vidioc_g_fmt_vid_cap = dt3155_ioc_g_fmt_vid_cap,
696 	.vidioc_s_fmt_vid_cap = dt3155_ioc_s_fmt_vid_cap,
697 	.vidioc_reqbufs = dt3155_ioc_reqbufs,
698 	.vidioc_querybuf = dt3155_ioc_querybuf,
699 	.vidioc_qbuf = dt3155_ioc_qbuf,
700 	.vidioc_dqbuf = dt3155_ioc_dqbuf,
701 	.vidioc_querystd = dt3155_ioc_querystd,
702 	.vidioc_g_std = dt3155_ioc_g_std,
703 	.vidioc_s_std = dt3155_ioc_s_std,
704 	.vidioc_enum_input = dt3155_ioc_enum_input,
705 	.vidioc_g_input = dt3155_ioc_g_input,
706 	.vidioc_s_input = dt3155_ioc_s_input,
707 /*
708 	.vidioc_queryctrl = dt3155_ioc_queryctrl,
709 	.vidioc_g_ctrl = dt3155_ioc_g_ctrl,
710 	.vidioc_s_ctrl = dt3155_ioc_s_ctrl,
711 	.vidioc_querymenu = dt3155_ioc_querymenu,
712 	.vidioc_g_ext_ctrls = dt3155_ioc_g_ext_ctrls,
713 	.vidioc_s_ext_ctrls = dt3155_ioc_s_ext_ctrls,
714 */
715 	.vidioc_g_parm = dt3155_ioc_g_parm,
716 	.vidioc_s_parm = dt3155_ioc_s_parm,
717 /*
718 	.vidioc_cropcap = dt3155_ioc_cropcap,
719 	.vidioc_g_crop = dt3155_ioc_g_crop,
720 	.vidioc_s_crop = dt3155_ioc_s_crop,
721 	.vidioc_enum_framesizes = dt3155_ioc_enum_framesizes,
722 	.vidioc_enum_frameintervals = dt3155_ioc_enum_frameintervals,
723 */
724 };
725 
726 static int
dt3155_init_board(struct pci_dev * pdev)727 dt3155_init_board(struct pci_dev *pdev)
728 {
729 	struct dt3155_priv *pd = pci_get_drvdata(pdev);
730 	void *buf_cpu;
731 	dma_addr_t buf_dma;
732 	int i;
733 	u8 tmp;
734 
735 	pci_set_master(pdev); /* dt3155 needs it */
736 
737 	/*  resetting the adapter  */
738 	iowrite32(FLD_CRPT_ODD | FLD_CRPT_EVEN | FLD_DN_ODD | FLD_DN_EVEN,
739 							pd->regs + CSR1);
740 	mmiowb();
741 	msleep(20);
742 
743 	/*  initializing adaper registers  */
744 	iowrite32(FIFO_EN | SRST, pd->regs + CSR1);
745 	mmiowb();
746 	iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT);
747 	iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT);
748 	iowrite32(0x00000020, pd->regs + FIFO_TRIGER);
749 	iowrite32(0x00000103, pd->regs + XFER_MODE);
750 	iowrite32(0, pd->regs + RETRY_WAIT_CNT);
751 	iowrite32(0, pd->regs + INT_CSR);
752 	iowrite32(1, pd->regs + EVEN_FLD_MASK);
753 	iowrite32(1, pd->regs + ODD_FLD_MASK);
754 	iowrite32(0, pd->regs + MASK_LENGTH);
755 	iowrite32(0x0005007C, pd->regs + FIFO_FLAG_CNT);
756 	iowrite32(0x01010101, pd->regs + IIC_CLK_DUR);
757 	mmiowb();
758 
759 	/* verifying that we have a DT3155 board (not just a SAA7116 chip) */
760 	read_i2c_reg(pd->regs, DT_ID, &tmp);
761 	if (tmp != DT3155_ID)
762 		return -ENODEV;
763 
764 	/* initialize AD LUT */
765 	write_i2c_reg(pd->regs, AD_ADDR, 0);
766 	for (i = 0; i < 256; i++)
767 		write_i2c_reg(pd->regs, AD_LUT, i);
768 
769 	/* initialize ADC references */
770 	/* FIXME: pos_ref & neg_ref depend on VT_50HZ */
771 	write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
772 	write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
773 	write_i2c_reg(pd->regs, AD_ADDR, AD_POS_REF);
774 	write_i2c_reg(pd->regs, AD_CMD, 34);
775 	write_i2c_reg(pd->regs, AD_ADDR, AD_NEG_REF);
776 	write_i2c_reg(pd->regs, AD_CMD, 0);
777 
778 	/* initialize PM LUT */
779 	write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM);
780 	for (i = 0; i < 256; i++) {
781 		write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
782 		write_i2c_reg(pd->regs, PM_LUT_DATA, i);
783 	}
784 	write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM | PM_LUT_SEL);
785 	for (i = 0; i < 256; i++) {
786 		write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
787 		write_i2c_reg(pd->regs, PM_LUT_DATA, i);
788 	}
789 	write_i2c_reg(pd->regs, CONFIG, pd->config); /*  ACQ_MODE_EVEN  */
790 
791 	/* select channel 1 for input and set sync level */
792 	write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
793 	write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
794 
795 	/* allocate memory, and initialize the DMA machine */
796 	buf_cpu = dma_alloc_coherent(&pdev->dev, DT3155_BUF_SIZE, &buf_dma,
797 								GFP_KERNEL);
798 	if (!buf_cpu)
799 		return -ENOMEM;
800 	iowrite32(buf_dma, pd->regs + EVEN_DMA_START);
801 	iowrite32(buf_dma, pd->regs + ODD_DMA_START);
802 	iowrite32(0, pd->regs + EVEN_DMA_STRIDE);
803 	iowrite32(0, pd->regs + ODD_DMA_STRIDE);
804 
805 	/*  Perform a pseudo even field acquire    */
806 	iowrite32(FIFO_EN | SRST | CAP_CONT_ODD, pd->regs + CSR1);
807 	write_i2c_reg(pd->regs, CSR2, pd->csr2 | SYNC_SNTL);
808 	write_i2c_reg(pd->regs, CONFIG, pd->config);
809 	write_i2c_reg(pd->regs, EVEN_CSR, CSR_SNGL);
810 	write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | SYNC_SNTL);
811 	msleep(100);
812 	read_i2c_reg(pd->regs, CSR2, &tmp);
813 	write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_SNGL | CSR_DONE);
814 	write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_SNGL | CSR_DONE);
815 	write_i2c_reg(pd->regs, CSR2, pd->csr2);
816 	iowrite32(FIFO_EN | SRST | FLD_DN_EVEN | FLD_DN_ODD, pd->regs + CSR1);
817 
818 	/*  deallocate memory  */
819 	dma_free_coherent(&pdev->dev, DT3155_BUF_SIZE, buf_cpu, buf_dma);
820 	if (tmp & BUSY_EVEN)
821 		return -EIO;
822 	return 0;
823 }
824 
825 static struct video_device dt3155_vdev = {
826 	.name = DT3155_NAME,
827 	.fops = &dt3155_fops,
828 	.ioctl_ops = &dt3155_ioctl_ops,
829 	.minor = -1,
830 	.release = video_device_release,
831 	.tvnorms = DT3155_CURRENT_NORM,
832 	.current_norm = DT3155_CURRENT_NORM,
833 };
834 
835 /* same as in drivers/base/dma-coherent.c */
836 struct dma_coherent_mem {
837 	void		*virt_base;
838 	dma_addr_t	device_base;
839 	int		size;
840 	int		flags;
841 	unsigned long	*bitmap;
842 };
843 
844 static int
dt3155_alloc_coherent(struct device * dev,size_t size,int flags)845 dt3155_alloc_coherent(struct device *dev, size_t size, int flags)
846 {
847 	struct dma_coherent_mem *mem;
848 	dma_addr_t dev_base;
849 	int pages = size >> PAGE_SHIFT;
850 	int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long);
851 
852 	if ((flags & DMA_MEMORY_MAP) == 0)
853 		goto out;
854 	if (!size)
855 		goto out;
856 	if (dev->dma_mem)
857 		goto out;
858 
859 	mem = kzalloc(sizeof(*mem), GFP_KERNEL);
860 	if (!mem)
861 		goto out;
862 	mem->virt_base = dma_alloc_coherent(dev, size, &dev_base,
863 							DT3155_COH_FLAGS);
864 	if (!mem->virt_base)
865 		goto err_alloc_coherent;
866 	mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
867 	if (!mem->bitmap)
868 		goto err_bitmap;
869 
870 	/* coherent_dma_mask is already set to 32 bits */
871 	mem->device_base = dev_base;
872 	mem->size = pages;
873 	mem->flags = flags;
874 	dev->dma_mem = mem;
875 	return DMA_MEMORY_MAP;
876 
877 err_bitmap:
878 	dma_free_coherent(dev, size, mem->virt_base, dev_base);
879 err_alloc_coherent:
880 	kfree(mem);
881 out:
882 	return 0;
883 }
884 
885 static void
dt3155_free_coherent(struct device * dev)886 dt3155_free_coherent(struct device *dev)
887 {
888 	struct dma_coherent_mem *mem = dev->dma_mem;
889 
890 	if (!mem)
891 		return;
892 	dev->dma_mem = NULL;
893 	dma_free_coherent(dev, mem->size << PAGE_SHIFT,
894 					mem->virt_base, mem->device_base);
895 	kfree(mem->bitmap);
896 	kfree(mem);
897 }
898 
899 static int
dt3155_probe(struct pci_dev * pdev,const struct pci_device_id * id)900 dt3155_probe(struct pci_dev *pdev, const struct pci_device_id *id)
901 {
902 	int err;
903 	struct dt3155_priv *pd;
904 
905 	err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
906 	if (err)
907 		return -ENODEV;
908 	err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
909 	if (err)
910 		return -ENODEV;
911 	pd = kzalloc(sizeof(*pd), GFP_KERNEL);
912 	if (!pd)
913 		return -ENOMEM;
914 	pd->vdev = video_device_alloc();
915 	if (!pd->vdev)
916 		goto err_video_device_alloc;
917 	*pd->vdev = dt3155_vdev;
918 	pci_set_drvdata(pdev, pd);    /* for use in dt3155_remove() */
919 	video_set_drvdata(pd->vdev, pd);  /* for use in video_fops */
920 	pd->users = 0;
921 	pd->pdev = pdev;
922 	INIT_LIST_HEAD(&pd->dmaq);
923 	mutex_init(&pd->mux);
924 	pd->vdev->lock = &pd->mux; /* for locking v4l2_file_operations */
925 	spin_lock_init(&pd->lock);
926 	pd->csr2 = csr2_init;
927 	pd->config = config_init;
928 	err = pci_enable_device(pdev);
929 	if (err)
930 		goto err_enable_dev;
931 	err = pci_request_region(pdev, 0, pci_name(pdev));
932 	if (err)
933 		goto err_req_region;
934 	pd->regs = pci_iomap(pdev, 0, pci_resource_len(pd->pdev, 0));
935 	if (!pd->regs) {
936 		err = -ENOMEM;
937 		goto err_pci_iomap;
938 	}
939 	err = dt3155_init_board(pdev);
940 	if (err)
941 		goto err_init_board;
942 	err = video_register_device(pd->vdev, VFL_TYPE_GRABBER, -1);
943 	if (err)
944 		goto err_init_board;
945 	if (dt3155_alloc_coherent(&pdev->dev, DT3155_CHUNK_SIZE,
946 							DMA_MEMORY_MAP))
947 		dev_info(&pdev->dev, "preallocated 8 buffers\n");
948 	dev_info(&pdev->dev, "/dev/video%i is ready\n", pd->vdev->minor);
949 	return 0;  /*   success   */
950 
951 err_init_board:
952 	pci_iounmap(pdev, pd->regs);
953 err_pci_iomap:
954 	pci_release_region(pdev, 0);
955 err_req_region:
956 	pci_disable_device(pdev);
957 err_enable_dev:
958 	video_device_release(pd->vdev);
959 err_video_device_alloc:
960 	kfree(pd);
961 	return err;
962 }
963 
964 static void
dt3155_remove(struct pci_dev * pdev)965 dt3155_remove(struct pci_dev *pdev)
966 {
967 	struct dt3155_priv *pd = pci_get_drvdata(pdev);
968 
969 	dt3155_free_coherent(&pdev->dev);
970 	video_unregister_device(pd->vdev);
971 	pci_iounmap(pdev, pd->regs);
972 	pci_release_region(pdev, 0);
973 	pci_disable_device(pdev);
974 	/*
975 	 * video_device_release() is invoked automatically
976 	 * see: struct video_device dt3155_vdev
977 	 */
978 	kfree(pd);
979 }
980 
981 static DEFINE_PCI_DEVICE_TABLE(pci_ids) = {
982 	{ PCI_DEVICE(DT3155_VENDOR_ID, DT3155_DEVICE_ID) },
983 	{ 0, /* zero marks the end */ },
984 };
985 MODULE_DEVICE_TABLE(pci, pci_ids);
986 
987 static struct pci_driver pci_driver = {
988 	.name = DT3155_NAME,
989 	.id_table = pci_ids,
990 	.probe = dt3155_probe,
991 	.remove = dt3155_remove,
992 };
993 
994 module_pci_driver(pci_driver);
995 
996 MODULE_DESCRIPTION("video4linux pci-driver for dt3155 frame grabber");
997 MODULE_AUTHOR("Marin Mitov <mitov@issp.bas.bg>");
998 MODULE_VERSION(DT3155_VERSION);
999 MODULE_LICENSE("GPL");
1000